JP2012159371A - Scan chain circuit, scan chain construction method, and test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan chain circuit and a scan chain construction method capable of suppressing the number of scan F/F transitions to reduce electrical power consumption.SOLUTION: An inventive scan chain circuit has a plurality of flip-flops 21 to 26, and shifts data held by each flip-flop from a head direction to a rear direction among the plurality of flip-flops 21 to 26. The plurality of flip-flops 21 to 26 are arranged in ascending order from smallness of the number of transitions of the data held by the flip-flop from the head direction to the rear direction of the scan chain circuit.

Description

  The present invention relates to a scan chain circuit, a scan chain construction method, and a test apparatus, and more particularly, to a scan chain circuit using a flip-flop, a construction method of the scan chain circuit, and a test apparatus used when constructing the scan chain circuit. .

  As LSIs become larger, various low-power technologies such as clock gating and multi-power supply design during normal operation have progressed. Here, there is room for improvement in the power reduction technology during the scan test, which is a test operation, and a technology that can further reduce power consumption than the currently proposed method for the scan shift operation during the scan test is desired. ing.

  Patent Document 1 is constructed by calculating a probability that a scan flip-flop (hereinafter referred to as a scan F / F) captures a logical value 1 and grouping the scan F / F for each arbitrary probability width. A scan chain is disclosed. The range of probability is, for example, 0 to 0.2, 0.2 to 0.4, 0.4 to 0.6, 0.6 to 0.8, 0.8 to 1.0, or the like. This minimizes the frequency with which adjacent scan F / Fs have different capture values as the scan chains are grouped with a probability range close to 1 or 0. The capture value is a value captured by the scan F / F. As a result, the number of scan F / F transitions during scan-out can be reduced, and power consumption can be reduced.

  Non-Patent Document 1 calculates a probability that capture values are the same (hereinafter referred to as correlation) for a scan F / F pair, and is constructed so that the sum of correlations in the entire scan chain is maximized. The chain is disclosed. As a result, the number of scan F / F transitions during scan-out can be reduced, and power consumption can be reduced.

  Patent Document 2 discloses a configuration in which flip-flops (hereinafter referred to as high power FFs) in which the number of rear stage gates driven in accordance with changes in data to be held are greater than or equal to a reference value are arranged on the scan-in side of the scan chain. Has been. The scan chain configured in this way can reduce power consumption during scan-out.

JP 2010-157209 A JP 2010-199106 A

Yu-Ze Wu, Mango C.T.Chao, "Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes" VTS 2008 4B_3

  The scan chain disclosed in Patent Document 1 reduces the frequency with which adjacent scan F / Fs have different capture values in a scan chain in which scan F / Fs having a logical value of 1 having a probability of taking about 1 are grouped. Can not do it. Therefore, such a scan chain has a problem that power consumption cannot be reduced.

  Further, the scan chain disclosed in Non-Patent Document 1 increases the scan F / F that causes a transition at the time of scan-out when a scan F / F with a high probability of transition of the capture value is arranged on the scan-in side. However, there is a problem that power consumption during the scan shift operation increases.

  In the scan chain disclosed in Patent Document 2, when the value captured in the high power FF is likely to transition, the scan F / F in the subsequent stage transitions due to the shift operation at the time of scan-out, and is consumed. There is a problem that electric power increases.

  The scan chain circuit according to the first aspect of the present invention has a plurality of flip-flops, and among the plurality of flip-flops, shifts data held in each flip-flop from the head direction to the tail direction. The plurality of flip-flops are arranged in ascending order from the least number of data transitions held from the head direction to the tail direction of the scan chain circuit. It is.

  By using such a scan chain circuit, a scan chain can be constructed according to the number of data transitions held by the flip-flop. Therefore, it is possible to reduce the probability that the capture value in the flip-flop transitions due to the data propagating through the scan chain.

  The scan chain construction method according to the second aspect of the present invention includes a plurality of flip-flops, and among the plurality of flip-flops, a logical value of 0 or 1 held by each flip-flop is viewed from the head direction. A scan chain construction method for constructing a scan chain that shifts with respect to the tail direction so that the number of data transitions held in ascending order from the head direction to the tail direction of the scan chain is ascending. The plurality of flip-flops are arranged.

  By using such a scan chain construction method, it is possible to construct a scan chain according to the number of data transitions held by the flip-flop. Therefore, it is possible to reduce the probability that the capture value in the flip-flop transitions due to the data propagating through the scan chain.

  The test apparatus according to the third aspect of the present invention includes a plurality of flip-flops, and shifts data held in each flip-flop among the plurality of flip-flops from the head direction to the tail direction. A test apparatus for constructing a scan chain circuit, wherein the calculation unit calculates information related to the number of times the data held in each of the plurality of flip-flops transitions, and the data transition number is in ascending order from the least A scan chain generation unit that generates scan chain construction information so as to arrange the plurality of flip-flops, and an execution unit that notifies the scan chain circuit insertion circuit of the scan chain construction information. Is.

  By using such a test apparatus, a scan chain can be constructed according to the number of data transitions held in the flip-flop. Therefore, it is possible to reduce the probability that the capture value in the flip-flop transitions due to the data propagating through the scan chain.

  According to the present invention, it is possible to provide a scan chain circuit, a scan chain construction method, and a test apparatus that can reduce power consumption by suppressing the number of scan F / F transitions.

FIG. 2 is a configuration diagram of a circuit in which a scan chain according to the first exemplary embodiment is inserted. 1 is a configuration diagram of a test apparatus according to a first embodiment. 4 is a processing flow of scan chain construction according to the first exemplary embodiment. 1 is a configuration diagram of a scan chain circuit according to a first exemplary embodiment; 1 is a configuration diagram of a scan chain circuit according to a first exemplary embodiment; FIG. 3 is a configuration diagram of a scan chain circuit according to a second exemplary embodiment; 10 is a processing flow of scan chain construction according to the second exemplary embodiment.

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. First, a configuration example of a circuit in which a scan chain according to the first exemplary embodiment of the present invention is inserted will be described with reference to FIG. The circuit into which the scan chain is inserted includes flip-flops (hereinafter referred to as F / F) 21 to 26, combinational circuits 30 to 32, a scan-in terminal 40, and a scan-out terminal 50.

  The F / F 21 performs a shift operation according to the input clock signal. The F / F 21 selects and holds (captures) either one of the signals output from the scan-in terminal 40 or the combinational circuit 31. The F / F 21 captures a signal output from the scan-in terminal 40 when holding a test pattern for executing a scan test. The F / F 21 captures a signal output from the combinational circuit 31 except when the test pattern is held. The F / F 21 outputs the captured value to the F / F 22 and the combinational circuit 30 in accordance with timing control by the clock signal.

  The F / F 22 selects and captures either the F / F 21 or the signal output from the combinational circuit 31. The F / F 22 captures a signal output from the F / F 21 when holding a test pattern for executing a scan test or when executing an operation of outputting a test result to the scan-out terminal 50. Further, the F / F 22 outputs a signal output from the combinational circuit 31 except when holding a test pattern for executing a scan test or executing an operation of outputting a test result to the scan-out terminal 50. To capture. The F / F 22 outputs the captured value to the F / F 23 and the combinational circuit 30 in accordance with timing control by the clock signal.

  Since the F / Fs 23 to 25 perform the same operation as the F / F 22, detailed description thereof is omitted. The F / F 26 outputs the held value to the scan-out terminal 50 and the combinational circuit 32. Other operations are the same as those of the F / F 22, and detailed description thereof is omitted.

  The F / Fs 21 to 26 are connected in series and constitute a scan chain that operates as a shift register. The scan chain outputs test pattern data scanned in from the scan-in terminal 40 to the combinational circuit 30 or 32 by a shift operation. The scan chain takes in data from the combinational circuit 30 or 31 and outputs the taken data to the scan-out terminal 50 by a shift operation. In the scan test, the test pattern data is input to the combinational circuit by the scan chain shift operation, and the output data of the combinational circuit is extracted to the flip-flop by the capture operation. Next, the output data taken out to the flip-flop is output to the scan-out terminal 50 by a shift operation. By comparing the data output to the scan-out terminal 50 with its expected value, it can be determined whether or not the combinational circuit is operating normally.

  The combinational circuits 30 to 32 are configured using a plurality of logic elements. That is, the combinational circuits 30 to 32 calculate the data received from the F / F and output the calculated result to each F / F. The scan-in terminal 40 is connected to the F / F 21 and outputs test pattern data to the F / Fs 21 to 26 via the F / F 21. The scan-out terminal 50 is connected to the F / F 26 and receives data captured by the F / Fs 21 to 26 via the F / F 26.

  Then, the structural example of the test apparatus 60 concerning Embodiment 1 of this invention is demonstrated using FIG. The test apparatus 60 is an apparatus different from an apparatus having a circuit in which a scan chain is inserted. The test apparatus 60 is used to control execution of a test in a circuit in which a scan chain is inserted. The test apparatus 60 includes a net list 61, a cell library 62, a calculation unit 63, a scan chain generation unit 64, and an execution unit 65.

  The netlist 61 holds the connection configuration pattern of the scan F / F and the combinational circuit in the circuit in which the scan F / F is inserted. Here, the F / F used in the scan chain is referred to as a scan F / F. The same applies to the following description. The cell library 62 holds a plurality of programs having specific functions. A CPU (not shown) in the test apparatus can execute a process using a program held in the cell library 62 according to the content to be processed.

  The calculation unit 63 uses the information held in the net list 61 and the cell library 62 to calculate information regarding the number of times the values captured by the respective scan F / Fs transition. The information regarding the number of times the value captured by each scan F / F transitions is, for example, the probability that each scan F / F holds 0 or 1 holds. As another example, a correlation indicating a probability that each scan F / F pair holds 0 or 1 may be used.

  The scan chain generation unit 64 determines the scan chain connection configuration based on the information calculated by the calculation unit 63. The process of determining the scan chain connection configuration will be described in detail later.

  The execution unit 65 notifies the connection structure of the scan chain determined by the scan chain generation unit 64 to the circuit into which the scan chain is inserted, and constructs the scan chain in the circuit.

  Next, the flow of processing for constructing a scan chain will be described with reference to FIG. The flow of processing for constructing a scan chain described in FIG. 3 will be described for an example in which a scan chain is constructed using the test apparatus 60 described above.

  First, the calculation unit 63 obtains the probability that each scan F / F captures a logical value 1 using circuit information and the like in the netlist 61 and the cell library 62 (S11). The calculation unit 63 extracts a scan F / F in the circuit and a connection configuration example of the combinational circuit from the net list 61, and extracts a scan pattern (test pattern) set to the scan F / F from the cell library 62. Using the extracted data, the calculation unit 63 applies a scan pattern to an assumed connection configuration, and performs a simulation on a value captured by the scan F / F when a test is executed. Accordingly, the test apparatus obtains the probability that the scan F / F captures the logical value 1. Here, the test apparatus may obtain the probability that the scan F / F captures the logical value 0.

  Next, the scan chain generation unit 64 constructs a scan chain using the probability that each scan F / F captures the logical value 1 (S12). A specific example of scan chain construction will be described with reference to FIGS. Scan F / Fs 1 to 12 are used for the scan chain. The test apparatus includes a plurality of scan F / Fs, a group including a scan F / F with a probability of capturing a logical value of 1 greater than 0.5, and a scan F / F with a probability of capturing a logical value of less than 0.5. And a group including F. Here, the scan F / F in which the probability of capturing the logical value 1 is 0.5 may be classified into either group. Further, the probability used as the threshold value in FIGS. 4 and 5 is not limited to 0.5, and other values may be used.

  The scan chain in FIG. 4 is a scan chain constructed by a scan F / F with a probability that the logical value 1 is captured is greater than 0.5. The scan chain in FIG. 5 is a scan chain constructed by a scan F / F with a probability that a logical value 1 is captured is smaller than 0.5.

  The scan chain in FIG. 4 shows a configuration in which scan F / Fs are connected in series between a scan-in terminal and a scan-out terminal. Further, from the scan-in terminal to the scan-out terminal, the connection is made in descending order in descending order of the probability that the logical value in each scan F / F becomes 1.

  The scan chain in FIG. 5 shows a configuration in which scan F / Fs are connected in series between a scan-in terminal and a scan-out terminal. Further, from the scan-in terminal to the scan-out terminal, the connections are made in ascending order from the lowest probability that the logical value in each scan F / F becomes 1.

  A scan F / F having a probability of capturing a logical value 1 of about 0.5 is connected to the rear of the scan chain of FIG. 4 and FIG. 5 configured in this manner (in the order close to the scan-out terminal). ing. When the value captured by the scan F / F having a probability of capturing the logical value 1 of about 0.5 is scanned out, the probability that the value captured in the scan F / F transitions increases. That is, the probability that the logical value captured by the scan F / F changes from 1 to 0 or from 0 to 1 increases. However, the scan F / F having a probability that the logical value 1 is captured is about 0.5 is arranged behind the scan chain. For this reason, the number of scan F / Fs through which transitions of captured values propagate due to scan shift is small. Therefore, the transition is propagated as compared with the case where the scan F / F having a probability that the scan F / F captures the logical value 1 is about 0.5 is connected in front of the scan chain (in the order close to the scan-in terminal). The number of scan F / Fs to be performed can be suppressed. Thereby, the power consumption of the scan chain circuit can be reduced.

  Further, a scan F / F having a probability of capturing a logical value 1 of 1 or 0 is connected to the front of the scan chain configured by such a method (in the order close to the scan-in terminal). When the value captured in the scan F / F whose probability of capturing the logical value 1 is close to 1 or 0 is scanned out, the probability that the value captured in the scan F / F transitions becomes low. That is, the probability that the logical value captured by the scan F / F changes is low. Since this scan F / F is arranged in front of the scan chain, even when a scan shift operation is performed, the number of scan F / Fs at which captured values transition is reduced. Therefore, the number of transition scan F / Fs is smaller than when scan F / Fs with a probability that the scan F / F captures a logical value 1 is close to 1 or 0 are connected to the back of the scan chain. . Thereby, the power consumption of the scan chain circuit can be reduced.

  Returning to FIG. 3, the scan chain generation unit 64 updates the net list to reflect the connection information of the newly constructed scan chain (S13). The updated netlist is stored in the netlist D1. Further, the execution unit 65 applies the scan chain connection information generated by the scan chain generation unit 64 to the circuit into which the scan chain is inserted.

  Next, the scan chain generation unit 64 or the CPU in the test apparatus generates a scan pattern based on the program information stored in the cell library D2 (S14). Further, the execution unit 65 sets a scan pattern for the scan F / F using the repeat fill function (S15). Here, the repeat fill function will be described.

  The repeat fill function is a function for setting the logical value set to the don't care bit of the scan pattern to the same value as the previous care bit. For example, an example in which a logical value 1 is set as a care bit in the first bit and a logical value 0 is set as a care bit in the fourth bit in a scan pattern of 8 bits will be described. In this case, the same logical value 1 as the first bit is set as the don't care bit in the second and third bits. Further, the same logical value 0 as the fourth bit is set as the don't care bit in the fifth to eighth bits. As a result, “11100000” is set as the scan F / F as the scan pattern. In this way, since the same logical values are arranged in the scan pattern, transition due to the scan pattern shift operation can be minimized. Thus, the repeat fill function is a function that can minimize the transition of the value captured by the scan F / F caused by the shift operation of the scan pattern.

  As described above, by using the scan chain circuit according to the first embodiment of the present invention, such a scan chain includes a scan F / F having a probability of capturing a logical value 1 of about 0.5. By disposing the F / F behind the scan chain (closer to the scan-out terminal), it is possible to suppress the propagation of transition due to the shift operation. Furthermore, by arranging a scan F / F with a probability of capturing a logical value 1 close to 1 or 0 in front of the scan chain (closer to the scan-in terminal), the scan F / F of the scan chain is further configured. The number of transitions can be minimized.

(Embodiment 2)
Subsequently, a construction example of the scan chain circuit according to the second exemplary embodiment of the present invention will be described with reference to FIG. In FIGS. 4 and 5 of the first embodiment of the present invention, the example in which the scan chain circuit is constructed based on the probability that each scan F / F captures the logical value 1 has been described. In FIG. 6 of Embodiment 2 of the present invention, a scan chain circuit is constructed based on the correlation between two scan F / Fs.

  The correlation between the scan F / Fs is the probability that the two scan F / Fs capture the same value. For example, in the scan chain circuit of FIG. 6, the probability that both the scan F / F4 and the scan F / F1 take the logical value 1 (1 is 100%) is 0.87, and the scan F / F1 The probability that both the scan F / F2 takes the logical value 1 is 0.63.

  The scan chain according to the second embodiment of the present invention is connected in descending order from a scan-in terminal to a scan-out terminal in descending order of correlation between scan F / Fs. That is, the scan F / F 4 and the scan F / F 1 having a correlation of 0.87 are connected to the place closest to the scan-in terminal. Further, the scan F / F 5 and the scan F / F 3 having the lowest correlation of 0.27 are connected to the place closest to the scan-out terminal.

  Subsequently, a flow of processing for constructing a scan chain according to the second exemplary embodiment of the present invention will be described with reference to FIG. First, the calculation unit 63 calculates a correlation between scan F / Fs using circuit information and the like in the netlist D1 and the cell library D2 (S21). For example, the calculation unit 63 extracts a scan F / F in the circuit and a connection configuration example of the combinational circuit from the netlist D1, and extracts a scan pattern (test pattern) set to the scan F / F from the cell library D2. . The calculation unit 63 uses the extracted data to calculate a probability that each scan F / F pair captures the logical value 1 when a scan pattern is applied to an assumed connection configuration and a test is executed. Perform a simulation. Thereby, the calculating part 63 calculates the correlation between all the scan F / Fs. Here, the calculation unit 63 may calculate the probability that each scan F / F pair captures the logical value 0.

  Since the process of step S22-step S25 is the same as that of step S12-step S15 in FIG. 3, detailed description is abbreviate | omitted.

  As described above, by using the scan chain circuit according to the second exemplary embodiment of the present invention, a scan F / F having a low correlation is connected to the rear of the scan chain (in the order close to the scan-out terminal). These scan F / Fs have a high probability that the values to be captured during the scan shift will transition. However, since the scan F / Fs are arranged behind the scan chain, the scan F / Fs in which transitions propagate due to the scan shifts. The number of is small. Accordingly, the number of scan F / Fs through which transition of captured values propagates is reduced compared with a case where scan F / Fs having low correlation are connected in the front of the scan chain (in order closer to the scan-in terminal) and consumed. Electric power can be reduced.

  Further, by using the scan chain circuit according to the second exemplary embodiment of the present invention, a scan F / F having a high correlation is connected in front of the scan chain. These scan F / Fs have a low probability of transition of values captured during scan shift. Since this scan F / F is arranged in front of the scan chain, the number of scan F / Fs that change as the scan shift operation proceeds decreases. Accordingly, the number of scan F / Fs that make a transition is smaller than when a scan F / F having a low correlation is connected in front of the scan chain, and power consumption can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

1-12 Scan F / F
21-26 F / F
30 to 32 combinational circuit 40 scan-in terminal 50 scan-out terminal 60 test apparatus 61 netlist 62 cell library 63 arithmetic unit 64 scan chain generation unit 65 execution unit

Claims (9)

A scan chain circuit that has a plurality of flip-flops and shifts data held in each flip-flop among the plurality of flip-flops from the head direction to the tail direction,
The plurality of flip-flops are:
A scan chain circuit arranged in ascending order from the least number of data transitions held in the scan chain circuit from the head direction to the tail direction. The plurality of flip-flops are:
Holds 0 or 1 as a logical value, and each flip-flop is in descending order from the highest probability that each flip-flop holds 0 from the head direction to the tail direction of the scan chain circuit, or each flip-flop The scan chain circuit according to claim 1, wherein the scan chains are arranged in descending order in descending order of probability of holding one. The plurality of flip-flops are:
2. The scan chain circuit according to claim 1, wherein the flip-flops are arranged in descending order in descending order of probability of holding the same data from the head direction to the tail direction of the scan chain circuit. The plurality of flip-flops are:
The first scan chain having a plurality of flip-flops having a probability of holding 1 greater than a predetermined threshold and the second scan chain having a plurality of flip-flops having a probability of holding 1 smaller than a predetermined threshold ,
The first scan chain is
The flip-flops are arranged in descending order from the highest probability of holding 1;
The second scan chain is
The scan chain circuit according to claim 2, wherein each of the flip-flops is arranged in ascending order from the lowest probability of holding 1. Scan chain construction having a plurality of flip-flops, and constructing a scan chain that shifts the logical value of 0 or 1 held by each flip-flop from the head direction to the tail direction among the plurality of flip-flops A method,
A method for constructing a scan chain, wherein the plurality of flip-flops are arranged in ascending order from the least number of data transitions held from the head direction to the tail direction of the scan chain. When arranging the plurality of flip-flops,
Calculating a probability that each of the plurality of flip-flops holds a logical value 1 or a probability that each of the plurality of flip-flops holds a logical value 0;
6. The scan chain construction method according to claim 5, wherein the plurality of flip-flops are arranged in descending order in descending order of probability of holding a logical value 1 or holding a logical value 0. When arranging the plurality of flip-flops,
Calculate the probability that adjacent flip-flops hold the same data from the head direction to the tail direction of the scan chain circuit,
6. The scan chain construction method according to claim 5, wherein the plurality of flip-flops are arranged in descending order in descending order of probability of holding the same data. Classifying a first group having a plurality of flip-flops with the calculated probability greater than a predetermined threshold and a second group having a plurality of flip-flops with the calculated probability less than a predetermined threshold;
In the first group, a scan chain is constructed so that the calculated probability is descending in descending order,
The scan chain construction method according to claim 6, wherein in the second group, a scan chain is constructed in ascending order from the lowest calculated probability. A test apparatus that has a plurality of flip-flops and constructs a scan chain circuit that shifts data held by each flip-flop among the plurality of flip-flops from the head direction to the tail direction,
An arithmetic unit that calculates information regarding the number of times data held in each of the plurality of flip-flops transitions;
A scan chain generation unit that generates scan chain construction information so as to arrange the plurality of flip-flops in ascending order from the least number of transitions of the data;
A test apparatus comprising: an execution unit that notifies the scan chain circuit insertion information of the scan chain construction information.

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