JP5107080B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of detecting a malfunction.

  In a semiconductor device, due to various variations and the like, variations also occur in path delays that terminate at a certain storage element. Although the path delay operates without any problem in the simulation, the actual machine may not operate because the timing constraint (setup violation) cannot be satisfied due to variations in the path delay.

  For this reason, in a semiconductor device, there is a case where a mechanism for dynamically detecting timing constraints is provided. Regarding this mechanism, for example, a circuit called Razor (hereinafter referred to as Razor circuit) shown in Non-Patent Document 1 is known. The Razor circuit shown in Non-Patent Document 1 is a circuit that combines a flip-flop circuit that captures data in synchronization with the rising edge of the clock signal clk and a latch circuit that captures data during the High period of the clock signal clk. The Razor circuit compares the output of the flip-flop circuit and the output of the latch circuit with a comparator, and selects the output of the flip-flop circuit or the output of the latch circuit, which is a normal logic, based on the comparison result. It was switched with.

  In the Razor circuit shown in Non-Patent Document 1, the latch circuit opens in synchronization with the timing at which the flip-flop circuit captures data, and the latch circuit captures data when the clock signal clk is High. That is, the Razor circuit shown in Non-Patent Document 1 malfunctions data that arrives from the rising edge of the clock signal clk to the High period of the clock signal clk using the time difference between the flip-flop circuit and the latch circuit (setup violation). It is detected as.

  Next, Patent Document 1 has a circuit configuration in which two sub-synchronization circuits having the same configuration as the main synchronization circuit are provided, and the sub-synchronization circuit operates at a double cycle of the main synchronization circuit. For this reason, in the circuit disclosed in Patent Document 1, a malfunction caused by a setup violation occurring in the main synchronization circuit can be recovered by the sub-synchronization circuit.

  Next, in Patent Document 2, a combinational logic circuit is interposed as a critical path between a sending-side flip-flop circuit and a receiving-side flip-flop circuit operating with the same clock signal clk. And in patent document 2, the delay state in the said critical path is measured and displayed on the exterior of a semiconductor device.

Dan Ernest et al., `` Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation '', IEEE MICRO, 2004, P.10-20 US Pat. No. 6,985,547 JP 2005-214732 A

  In order to provide a plurality of circuits shown in Non-Patent Document 1 in a semiconductor device and identify where a setup violation has occurred, it is necessary to extract error signals output from the respective circuits. However, a plurality of pins are required to extract the error signal. However, since the number of pins of the semiconductor device is limited, the conventional semiconductor device ORs the error signal output from the circuit shown in Non-Patent Document 1. It was common to bundle with a tree. For this reason, the conventional semiconductor device has a problem that it cannot be specified where the setup violation occurs.

  Further, in the circuits shown in Non-Patent Document 1, Patent Document 1 and Patent Document 2, even if a setup violation is detected and the state of the setup violation is recovered, a malfunction may be caused in the next-stage circuit.

  Furthermore, the conditions for detecting a setup violation in the semiconductor device are not constant and vary. Therefore, there is a problem that there is a circuit that cannot detect a setup violation when fixed to one condition.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can recognize a circuit malfunction (setup violation) during actual operation and that can identify the location of the circuit malfunction. It is another object of the present invention to provide a semiconductor device that does not cause malfunction in a circuit at the next stage when malfunction is repaired.

  One embodiment of the present invention is a semiconductor device including a plurality of logic circuits and a plurality of determination circuits that perform malfunction determination based on data from the logic circuits. The determination circuit includes a first register, a delay unit, a second register, a comparator, and a scan unit. The first register takes in data from the logic circuit at a predetermined timing of the clock signal. The delay means delays the clock signal. The second register is logically equivalent to the first register, and takes in data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay means. The comparator compares the output of the first register with the output of the second register and outputs an error signal. The scanning means holds the comparison result of the comparator, shifts the second register to a shift register, and propagates the error signal held in the second register to the next stage.

  According to the semiconductor device of the present invention, since the comparison result of the comparator is retained, the second register is provided with a shift register and the error signal retained in the second register is propagated to the next stage. It is possible to identify one or more locations where the occurrence of.

(Embodiment 1)
First, before describing the semiconductor device of the present invention, the configuration and driving of a Razor circuit disclosed in Non-Patent Document 1 will be described. FIG. 1 shows a circuit diagram of the Razor circuit, and FIG. 2 shows a timing chart of the Razor circuit.

  The Razor circuit shown in FIG. 1 includes a flip-flop circuit 101 that captures a data signal in synchronization with the rising edge of the clock signal clk, and a latch circuit 102 that captures a data signal during the High period of the clock signal clk. Further, in the Razor circuit shown in FIG. 1, the comparator 103 that compares the output Q1 of the flip-flop circuit 101 and the output Q2 of the latch circuit 102, and the logic stage L1 that is a logic circuit according to the result of the comparator 103 output. A selector circuit 104 that switches between the data signal D1 and the data signal Q2 output from the latch circuit 102 is provided. The latch circuit 102 shown in FIG. 1 takes in the data signal S1 output from the selector circuit 104 during the High period of the clock signal clk. 1 uses the time difference between the flip-flop circuit 101 and the latch circuit 102 to malfunction the event of the data signal that reaches from the rising edge of the clock signal clk to the High period of the clock signal clk ( Detected as setup violation).

  However, the malfunction detection performed by the Razor circuit has the following problems. First, in the timing chart for three cycles shown in FIG. 2, the timing is not in time only in the second cycle, a setup violation occurs, and the data arrives normally in the other cycles (first and third cycles). In the second cycle in this case, the flip-flop circuit 101 captures “1” because the event arrival of the data signal that changes from “1” to “0” is not in time at the rising timing of the clock signal clk. . On the other hand, the latch circuit 102 captures “0”, which is a data signal in which the clock signal clk is High. For this reason, the Razor circuit asserts an error signal as intended.

  Next, in the third period shown in FIG. 2, since a data signal event that changes from “0” to “1” arrives at the rising timing of the clock signal clk, a setup violation does not occur. However, the error signal asserted in the second period is not negated even in the third period. This is because the data signal D1 output from the logic stage L1 needs to be taken in at the rising timing of the clock signal clk in the third period, but the error signal in the second period is not negated. This is because the data signal Q <b> 2 output by is taken in.

  As a result, when the error signal is negated and the path from the logic stage L1 becomes active (upward arrow in FIG. 2), the flip-flop circuit 101 fetches “0” latched in the latch circuit 102. Therefore, only the latch circuit 102 captures the event of the data signal that changes from “0” to “1” (downward arrow in FIG. 2). Therefore, in the comparator 103, the data signal Q1 output from the flip-flop circuit 101 and the data signal Q2 output from the latch circuit 102 do not match, and an error signal is asserted even though no setup violation has occurred. End up.

  FIG. 3 shows a circuit diagram of a malfunction determination circuit (error detection flip-flop circuit (FF)) that solves the above-described problems. In the circuit shown in FIG. 3, an expected value register (Positive Slack) is provided by inserting a buffer 1 into the clock signal (Clk) line with respect to the register R1 which is a target register (TargetRegister). ExpectRegister) register R2. The register R1 receives the data signal D1 output from the preceding logic stage L1. On the other hand, the data signal Q1 output from the register R1 is output to the next logic stage L2 via the selection circuit 2 (Output signal) and also input to the comparator 3.

  The comparator 3 compares the data signal Q1 output from the register R1 with the data signal Q2 output from the register R2, and outputs an error signal (Error) if they do not match. That is, in the circuit shown in FIG. 3, the register R2 in which the setup violation condition is relaxed by inserting the buffer 1 in the clock line is provided, and the comparator 3 compares the outputs of the register R1 and the register R2, thereby causing a malfunction. Is detected. For this reason, in the circuit shown in FIG. 3, by providing the buffer 1, it is possible to avoid the problem that the error signal is asserted even though the setup violation does not occur unlike the Razor circuit.

  The circuit shown in FIG. 3 is a malfunction determination circuit that outputs the presence or absence of setup violation as an error signal, as described above. For this reason, in a semiconductor device (LSI or the like) including the circuit shown in FIG. 3, the circuit shown in FIG. 3 is replaced for a flip-flop circuit normally used for logic that is severe in timing. When a plurality of circuits shown in FIG. 3 are incorporated in the semiconductor device, it is necessary to specify from which circuit the error signal is output.

  However, since the number of pins of the semiconductor device is limited, it is not possible to assign pins to each error signal from each circuit, and the error signals are output outside the semiconductor device by bundling them with an OR tree (not shown). ) Therefore, in the circuit shown in FIG. 3, it can be determined that a setup violation has occurred in the semiconductor device, but it is impossible to identify which circuit has caused the setup violation.

  Therefore, the semiconductor device according to the present embodiment further includes means for scanning the register R2 of the expected value register shown in FIG. 3 as a shift register (hereinafter also referred to as scanning means), and using this means, an error signal is provided. Is propagated and pushed out to identify the offending circuit. The circuit configuration is effective not only for voltage control but also for failure location analysis using an actual operation (performance) pattern.

  Next, FIG. 4 specifically shows a circuit configuration provided with scanning means. However, the scanning unit shown in FIG. 4 is an example, and the present invention is not limited to this, and other circuit configurations may be used as long as the scanning unit has a similar function.

  In the circuit shown in FIG. 4, an AND circuit 4 is provided on the line of the clock signal Clk of the register R1. The AND circuit 4 includes an AND circuit 4a to which an inverted signal of a scan mode signal (SM) and a scan reset signal (Srst) are input, and an AND circuit 4b to which a clock signal Clk and an output of the AND circuit 4a are input. I have. In the circuit shown in FIG. 4, a multiplexer (MUX) 5 is provided in the previous stage of the register R2, and the MUX 5 has an error signal (Error) output from the comparator 3 in the previous stage, the output of the MUX 6, and Srst. Signal. The MUX 6 receives an error-in signal (ErrIn) equivalent to a scan-in signal (SI) in a normal scan cell, an Srst signal, and a data signal (DATA) from the preceding logic circuit.

  In the circuit shown in FIG. 4, the MUX 7 is used in place of the selection circuit 2 of the circuit shown in FIG. 3, but the functions are equivalent. The other circuits shown in FIG. 4 are the same as those shown in FIG. 3, and thus detailed description thereof is omitted.

  In the circuit shown in FIG. 4, the error out signal (ErrOut) that is the output of the register R2 is equivalent to the scan out signal (SO) in the normal scan cell, and the ErrOut signal of one error detection FF is the other error detection FF. A scan path is formed by connecting to the ErrIn signal.

  The SM signal is a signal for controlling the scan mode. When the signal is “0”, the normal operation mode is set, and the register R2 controls the MUX 6 so that the data signal can be taken in at the rising edge of the clock signal. Further, when the SM signal is “1”, the scan mode is set, and the register R2 controls the MUX 6 so that the value of the ErrIn signal can be taken in at the rising edge of the clock signal.

  Further, the Srst signal is a reset signal at the time of mode switching, and determines an initial state in each mode (normal or scan). That is, when the Srst signal is “0”, the register R2 takes in the value of the error signal via the MUX5, and when the Srst signal is “1”, the register R2 is the signal selected by the SM signal via the MUX5 ( (DATA or ErrIn) value. As a summary of the above, Table 1 shows a truth table when the register R2 is scanned. Note that “*” shown in Table 1 represents an arbitrary value. In addition, “(R2 &! R1) | (! R2 & R1)” shown in Table 1 holds the comparison result of the expected value in the register R2, and if the comparison result is “0” (no error), the register R1 Is output as it is, and when the comparison result is “1” (error), the inversion of the register R1 is output.

  Therefore, by scanning the register R2 and controlling the SM signal and the Srst signal as shown in Table 1, it is possible to propagate the error signal at the time of the setup violation and to specify the location of the setup violation. The circuit configuration not only identifies the location where the setup is violated, but also allows the initial value to be set in the register R2 via the scan path, as in a normal scan circuit.

  Further, in the circuit shown in FIG. 4, in the scan mode in which the SM signal is “1”, the clock signal Clk input to the register R1 is disabled by the AND circuit 4, and the circuit operation of the register R1 is stopped. Therefore, when the SM signal is “1” in the scan mode, the contents of the register R1 are held in the state before the clock signal is disabled, and the SM signal is “0” again in the normal operation mode. The operation of R1 can be resumed. In addition, since the circuit operation of the register R1 is stopped in the scan mode, power consumption during the period can be reduced.

  FIG. 5 is a circuit diagram in which four stages of the circuit shown in FIG. 4 are arranged to form a scan path from the ErrOut signal to the ErrIn signal of each circuit (S1 to S4). In FIG. 5, the logic stage L1 is connected to the preceding stage of the circuit S1, the logic stage L2 is connected to the preceding stage of the circuit S2, the logic stage L3 is connected to the preceding stage of the circuit S3, and the logic stage L4 is connected to the preceding stage of the circuit S4. Further, in FIG. 5, the ErrOut signal output from the circuit S4 is directly connected to the ErrIn signal of the circuit S1, so that the shift is completed and the initial state is restored. However, the present invention is not limited to this, and the ErrIn signal of the circuit S1 can be set to an arbitrary value from the external terminal.

  Next, the operation of the circuit shown in FIG. 5 will be described based on the timing chart shown in FIG. First, in the first cycle of the timing chart shown in FIG. 6, it is assumed that the circuit S2 has detected a setup violation malfunction. Since the value of the ErrOut signal is the normal operation mode, it is assumed that the value of the register R2 is not the error signal of each circuit S1 to S4, and the expected value in the period is “1” for all 4 bits. Note that the value of the register R1 of the circuit S2 is assumed to be a setup violation, and therefore does not match the expected value and is “0”.

  Next, in the second cycle, the SM signal becomes “1” and the mode is switched to the scan mode. At the same time, since the Srst signal is also asserted to “0”, the value of the error signal of each circuit is taken into the register R2. Since it is assumed that only the circuit S2 has malfunctioned in the first cycle, only the value of the ErrOut signal of the circuit S2 becomes “1” in the second cycle, and the ErrOut signal of the other circuits S1, S3, S4 The values are all “0”. Since the SM signal becomes “1”, all the clock signals supplied to the registers R1 in the circuits S1 to S4 are disabled.

  Next, since the Srst signal becomes “1” in the third period, the ErrOut signal of each circuit S1 to S4 captures the previous stage ErrOut signal. Therefore, the ErrOut signal of the circuit S3 takes in the value of the ErrOut signal in the circuit S2 in the second period and becomes “1”, and the ErrOut signals of the other circuits S1, S2, and S4 all become “0”. Here, the value of the ErrOut signal of the circuit S4 is supplied to the ErrOut signal of the circuit S1.

  Next, in the fourth period, the same process as in the third period is performed, and the ErrOut signal of the circuit S4 takes in the value of the ErrOut signal in the circuit S3 of the third period and becomes “1”, and the other circuit S1. , S2 and S3 are all “0”. Further, in the fifth cycle, the same processing as in the fourth cycle is performed, and the ErrOut signal of the circuit S1 takes in the value of the ErrOut signal in the circuit S4 of the fourth cycle and becomes “1”, and the other circuits S2, The ErrOut signals in S3 and S4 are all “0”. In the sixth cycle, the same process as in the fourth cycle is performed, and the ErrOut signal of the circuit S2 takes in the value of the ErrOut signal in the circuit S1 of the fifth cycle and becomes “1”, and the other circuits S1, S3, All the ErrOut signals in S4 are “0”.

  By repeating the above processing, the circuit shown in FIG. 5 sequentially shifts the value of the ErrOut signal, and the number of cycles from when the Srst signal becomes “1” until the value of the ErrOut signal is detected as “1”. By accounting for, it is possible to identify the circuit in which the malfunction occurred. In the present embodiment, since the ErrOut signal becomes “1” in the fourth period, it can be seen that a setup violation has occurred in the circuit S2. Even if a plurality of points have failed, they can be detected by the same method.

  Next, in the seventh cycle, the SM signal is switched to the normal mode “1” and the Srst signal is asserted to “1” at the same time, thereby causing the register R2 of the specific circuits S1 to S4 to have a value before starting the scan mode operation (see FIG. Automatically restored from the circuit configuration shown in FIG. However, since the clock signal Clk is negated during the SM signal = “1” or the Srst signal “0”, the value of each register R1 in the circuits S1 to S4 remains malfunctioning. Therefore, if necessary, the recovery method described in the following embodiment is performed and the operation is resumed.

  As described above, in the semiconductor circuit according to the present embodiment, by providing a means for scanning the register R2, it is possible to identify a circuit in which a malfunction due to a setup violation has occurred.

  Note that the circuit shown in FIG. 4 is intended for timing-critical registers (critical path endpoints) in the synchronous design section, so it can be applied to all digital design fields such as SOC (System On a Chip) and microcomputers. It is. The same applies to the circuits according to the embodiments described below.

  Specifically, FIG. 7 shows a block diagram of an application example of the semiconductor device according to this embodiment. In the semiconductor device illustrated in FIG. 7, the digital circuit 10 to which the malfunction determination circuit and the logic circuit (logic stage) illustrated in FIG. 4 are applied, the clock generator 11 that supplies the digital circuit 10 with the clock signal Clk, and the digital circuit 10. And a regulator 12 for supplying a voltage to the. Further, the semiconductor device shown in FIG. 7 includes a control circuit 13 that controls the clock generator 11 and the regulator 12 based on an error signal from the digital circuit 10, and a memory 14 that the digital circuit 10 appropriately refers to. . Note that the control circuit 13 also includes error rate calculation processing.

  Further, in the semiconductor device shown in FIG. 7, the error signal to the control circuit 13 is asserted, so that the control circuit 13 controls the clock generator 11 and the regulator 12 to realize low power consumption. In the semiconductor device shown in FIG. 7, when a malfunction such as a setup violation occurs, the malfunction location (circuit) can be specified by switching the scan mode and propagating the error signal to the outside. Further, in the semiconductor device employing the circuit shown in FIG. 4, it is possible to resume from the state stopped in the scan mode after recovering the malfunctioning portion (circuit).

(Embodiment 2)
In the circuit shown in FIG. 8, a path from the register R0 to the register R1 via the logic stage L1 is a critical path, and the data signal Q1 output from the register R1 is propagated to the next stage logic (logic stage L2). Here, in the circuit shown in FIG. 8, the clock signal C1 supplied to the register R1 is not the clock signal Clk supplied directly from the outside, but the enable signal (enable) in the AND circuit 20 functioning as clock control means. Signal) and a logical sum. The clock control means is not limited to an AND circuit, and may be any circuit having an equivalent function.

  In the circuit shown in FIG. 8, a register R2 in which the setup violation condition is relaxed by inserting the buffer B2 in the clock line is provided, and the output result comparison with the register R1 is performed by the comparator 3. Further, in the circuit shown in FIG. 8, when the Enable signal is “0”, the data signal Q2 output from the register R2 is fed back using the selection circuit 21 so that the data from the register R0 is not captured, and the Enable signal is In the case of “1”, the data signal D1 is fetched.

  However, in the circuit shown in FIG. 8, the clock signal C2 input to the register R2 on the expected value side is not a gated clock signal but a free run. Therefore, a clock event always occurs in the register R2, and the effect of reducing power consumption by driving the register R1 with a gated clock signal is reduced.

  Also, in normal circuit operation, the Enable signal is not changed during the dominant period ("H" period if positive edge) so that the waveform of the clock signal is not clipped. However, if there is a delay in the arrival of the Enable signal due to a drop in power supply voltage or a change in ambient temperature (so-called “Enable signal setup violation”), the clock signal will be clipped, affecting the signal propagation to the next stage and causing malfunctions. It becomes. FIG. 9 schematically shows how the clock signal is clipped.

  Therefore, in the semiconductor device according to the present embodiment, the power consumption reduction effect is improved by using the circuit shown in FIG. 10, and a setup violation of the Enable signal can be detected. In the circuit shown in FIG. 10, an AND circuit 22 is provided as clock control means so that the clock signal input to the register R2 is a gated clock signal. The clock control means is not limited to an AND circuit, and may be any circuit having an equivalent function.

  The AND circuit 22 receives the output of the register R3 functioning as a lock-up latch, the output of the register R4, and the clock signal delayed by the buffer B3. The register R3 receives the Enable signal and the clock signal delayed by the buffer B3. An Enable signal and a clock signal are input to the register R4. Since the other configuration of the circuit shown in FIG. 10 is the same as the circuit configuration shown in FIG. 8, the same components are denoted by the same reference numerals and detailed description thereof is omitted.

  Here, regarding the delay of the rise event of the enable signal as in clip A shown in FIG. 9, if the enable signal at the rise of the original clock signal is “L”, the clock signal to the register R2 is negated. It can be detected. That is, when the enable signal becomes “H” after the determination of clipping and a clock signal clipped to the register R1 is generated, the contents of the register R1 change and a difference occurs between the register R2 and the error signal. Will stand. If the contents of the register R1 do not change, data propagation to the subsequent stage does not occur, so there is no need to raise an error signal.

  Next, regarding the delay of the fall event of the Enable signal like the clip B shown in FIG. 9, the event passes only during the disable period of the clock signal (delayed clock signal) delayed by the buffer B3 as shown in FIG. Detection can be performed by inserting the register R3 of the lock-up latch. That is, when the Enable signal is negated between the rising edge of the clock signal and the rising edge of the delayed clock signal, the clock signal input to the register R2 is negated. Therefore, if the contents of the register R1 are changed, a difference occurs between the register R2 and an error signal is raised. If the contents of the register R1 do not change, data propagation to the subsequent stage does not occur, so there is no need to raise an error signal.

  In the circuit shown in FIG. 10, the register R2 having a margin (Positive Slack) is created by inserting a buffer B3 in the clock line with respect to the register R1 in actual operation. Then, a gated clock signal via the AND circuits 20 and 22 is input to each of the register R1 and the register R2. Here, in the circuit shown in FIG. 10, in order to prevent glitches, a lock-up latch register R3 is inserted before the AND circuit 22 as a fail-safe circuit in order to cut off an event during the “H” period of the delay clock signal.

  Further, in the circuit shown in FIG. 10, in order to determine whether the event content of the Enable signal is a rise event or a fall event, a register R4 is inserted and its output is connected to the input of the AND circuit 22. In the circuit shown in FIG. 10, the setup violation of the data signal can be detected (event detection between the clock signal C1 and the clock signal C2), and the setup violation of the enable signal can also be detected.

  Next, the operation of the circuit shown in FIG. 10 will be described with reference to the timing chart shown in FIG. First, a signal input to the clock pin of the register R1 is a clock signal C1, a signal input to the data input pin is a data signal D1, and a signal output from the data output pin is a data signal Q1. A signal input to the clock pin of the register R2 is a clock signal C2, a signal input to the data input pin is a data signal D2, and a signal output from the data output pin is a data signal Q2. Further, an error signal is output from the comparator 3 that compares the data signal Q1 and the data signal Q2. As described above, the clock signal C2 is delayed by the amount of buffer inserted by the buffer B3 with respect to the clock signal C1, and the event propagates.

  First, in the first period shown in FIG. 11, since the arrival of the rise event of the Enable signal is delayed, the clock signal C1 is clipped (hatched portion). Since the Enable signal is “L” when the clock signal C1 is a rise event, the output R4Enbl of the register R4 is also “L” although not shown. Therefore, in the first cycle, the clock signal C2 to the register R2 is negated. Therefore, when the data content in the register R1 changes, the result of the register R1 and the register R2 is different, so that the error signal is “1”. " That is, the circuit shown in FIG. 10 can detect a setup violation of the Enable signal. If there is no change in the data contents in the register R1, the error signal is not "1" and the clip of the clock signal C1 cannot be detected, but the event itself has not occurred and the subsequent circuit is affected. There is no need to assert this phenomenon.

  Next, in the second period shown in FIG. 11, the Enable signal is fixed to “H” before the rise event of the clock signals C1 and C2, but the arrival of the data event to the register R1 (change of the data signal D1). Is not in time for the rise event of the clock signal C1. Therefore, the results of the data signal Q1 and the data signal Q2 are different, and the error signal becomes “H”. That is, the circuit shown in FIG. 10 can detect a data signal setup violation.

  Next, in the third period shown in FIG. 11, since the arrival of the fall event of the Enable signal is delayed, the clock signal C1 is clipped (hatched portion). Since the Enable signal is “H” at the rise event of the clock signal C1, the output R4Enbl of the register R4 is also “H” (not shown). Therefore, in the third period, the Enable signal falls to “L” before the rise event of the clock signal C2, and the event is transmitted to the AND circuit 22 via the register R3 which is a lock-up latch. As a result, the register R2 The clock signal C2 to is negated. Further, when there is a change in the data contents in the register R1, the results of the register R1 and the register R2 are different, and the error signal is “1”. That is, the circuit shown in FIG. 10 can detect a setup violation of the Enable signal. If there is no change in the data contents in the register R1, the error signal does not become “1” and the clip of the clock signal C1 cannot be detected, but the event itself has not occurred and the subsequent circuit is affected. There is no need to assert this phenomenon.

  Next, in the fourth period shown in FIG. 11, since the Enable signal is “L”, both the clock signal C1 and the clock signal C2 are negated, so that the output result of the circuit shown in FIG. 10 is not affected. And in the 5th period shown in FIG. 11, since the same operation | movement as the 2nd period is performed, detailed description is abbreviate | omitted.

  As described above, since the semiconductor device according to the present embodiment uses the circuit shown in FIG. 10, the power consumption reduction effect can be improved and the setup violation of the Enable signal can be detected.

(Embodiment 3)
In the second embodiment, the setup violation of the data signal and the setup violation of the Enable signal can be detected, respectively. However, when the setup violation of the data signal and the Enable signal occurs in the same period, the setup violation cannot be detected. Therefore, in this embodiment, the setup violation of the data signal and the Enable signal that occur in the same cycle can be detected by using the circuit shown in FIG.

  Normally, the Enable signal is often used for bus (multi-bit) control. Therefore, in the circuit shown in FIG. 12, the Enable signal setup violation causes only the Enable signal to the circuit group controlled by the same Enable signal. A new circuit to detect this is added. In other words, the circuit shown in FIG. 12 includes registers R1 and R2, a comparator 3, and the like, and detects the data signal setup violations A1 to A3, and the Enable signal supplied in common to the circuits A1 to A3. Circuit B for detecting a setup violation.

  Circuits A1 to A3 shown in FIG. 12 have a configuration in which the registers R3 and R4 of the circuit shown in FIG. 10 are removed. On the other hand, the circuit B shown in FIG. 12 includes a register R3 to which the clock signal and the Enable signal are input, a register R4 to which the clock signal delayed by the buffer 30 and the Enable signal are input, the output of the register R3, and the register R4. And a comparator 31 for comparing outputs. Note that the configuration of the circuit B is not limited to the circuit configuration illustrated in FIG. 12 and may be a circuit configuration having an equivalent function.

  Here, the delay amounts of the buffer B3 of the circuits A1 to A3 and the buffer 30 of the circuit B depend on the slack amount in the previous stage logic of the target register, and optimum delay amounts are respectively set. Specifically, when the slack amount of the path from the Enable signal to each of the registers R1, R2, R3, and R4 is larger than the slack amount of the logic stage L1, the delay of the buffer B3 inserted in the previous stage of the register R2 The amount is larger than the delay amount of the buffer 30 inserted in the preceding stage of the register R4.

  In the circuit shown in FIG. 12, since the circuit group controlled by the same Enable signal is 3 bits, one circuit B is provided for three circuits A1 to A3. It is not limited to this. For example, if the circuit group controlled by the same Enable signal is 5 bits, one circuit B is provided for five circuits A1 to A5.

  Next, the operation of the circuit shown in FIG. 12 will be described with reference to the timing chart shown in FIG. First, a signal input to the clock pin of the register R1 is a clock signal C1, a signal input to the data input pin is a data signal D1, and a signal output from the data output pin is a data signal Q1. A signal input to the clock pin of the register R2 is a clock signal C2, a signal input to the data input pin is a data signal D2, and a signal output from the data output pin is a data signal Q2.

  A signal input to the clock pin of the register R3 is a clock signal C3, a signal input to the data input pin is a data signal D3, and a signal output from the data output pin is a data signal Q3. A signal input to the clock pin of the register R4 is a clock signal C4, a signal input to the data input pin is a data signal D4, and a signal output from the data output pin is a data signal Q4. Further, an error signal output from the comparator 3 that compares the data signal Q1 and the data signal Q2 is Error1, and an error signal output from the comparator 31 that compares the data signal Q3 and the data signal Q4 is Error2. . As described above, the clock signal C2 is delayed by the amount of the buffer inserted by the buffer B3 with respect to the clock signal C1, and the event is propagated. The clock signal C4 is inserted by the buffer 30 with respect to the clock signal C3. Propagate event with buffer delay.

  First, in the first period shown in FIG. 13, since the arrival of the rise event of the Enable signal is delayed, the clock signal C1 is clipped (hatched portion). In the circuit shown in FIG. 12, since the circuit that detects the setup violation of the data signal and the Enable signal is separated, the clip of the clock signal C1 cannot be detected as the Error1 signal that is the error detection signal of the data signal. However, in the first cycle shown in FIG. 13, the Error2 signal, which is the error detection signal of the Enable signal, is “H”, and the clip of the clock signal C1 is detected.

  Next, in the second period shown in FIG. 13, since the setup violation of the data signal has occurred, it is detected as the Error 1 signal. In the second period, the Error 2 signal, which is the error detection signal of the Enable signal, remains “L” and is not asserted.

  Next, in the third period shown in FIG. 13, since the arrival of the fall event of the Enable signal is delayed, the clock signal C1 is clipped (hatched portion). The setup signal violation of the Enable signal due to the clip of the clock signal C1 can also be detected when the Error2 signal becomes “H” as in the first cycle.

  Next, in the fourth period shown in FIG. 13, since the Enable signal is “L”, both the clock signal C1 and the clock signal C2 are negated, so that the output result of the circuit shown in FIG. 12 is not affected.

  Next, in the fifth period shown in FIG. 13, a setup violation occurs in both the data signal and the Enable signal. In the fifth period, the data signal and the Enable signal are in a competitive relationship. That is, since the arrival of the data signal event is delayed with respect to the rising edge of the clock signal Clk, the setup should be violated originally. However, when the clock signal C1 rises due to the clip of the clock signal C1, the event of the data signal occurs. Has reached. Therefore, the results of the data signal Q1 and the data signal Q2 are the same, the Error1 signal of the error detection signal for the data signal is not “H”, and the setup violation of the data signal cannot be detected. However, in the fifth period shown in FIG. 13, the Error2 signal of the error detection signal with respect to the Enable signal becomes “H”, and the clip of the clock signal C1 can be detected. Note that if the event arrival of the data signal is delayed from the time when the clock signal C1 rises, a setup violation of the data signal can also be detected.

  As described above, the semiconductor device according to the present embodiment can detect at least one of the data signal setup violation and the enable signal setup violation in the same cycle by using the circuit shown in FIG. Can do.

(Embodiment 4)
The circuit shown in FIG. 14 is provided with a register R2 that has a margin (Positive Slack) with respect to the register R1 that is an actual operation register as much as the buffer B2 that is a delay means is inserted in the clock line. A data signal D1 that is an output of the logic stage L1 is input to the register R1. A register R0 is connected to the preceding stage of the logic stage L1. On the other hand, the data signal Q 1 that is the output of the register R 1 is input to the comparator 3.

  The comparator 3 compares the data signal Q1 of the register R1 with the data signal Q2 output from the register R2, and outputs an error signal if they do not match. Therefore, the circuit shown in FIG. 14 can dynamically detect the setup violation of the register R1 by the delay of the buffer B2 inserted in the clock line. In the circuit shown in FIG. 14, the selection circuit 2 is provided before the next logic stage L2. The selection circuit 2 outputs the data signal Q1 from the register R1 to the logic stage L2 when the error signal output from the comparator 3 is “0”, and outputs the data signal from the register R2 when the error signal is “1”. Switching control is performed so that the data signal Q2 is output to the logic stage L2.

  In the normal path of the circuit shown in FIG. 14, the data signal D1 reaching the register R1 is taken in synchronization with the rising edge of the clock signal C1, and is propagated to the next logic stage L2 via the selection circuit 2. That is, the path path during normal operation is a path that passes through the register R1 and the selection circuit 2.

  However, when the circuit shown in FIG. 14 detects a malfunction and performs a repair operation, the data signal D2 that reaches the register R2 at the same time as the data signal D1 is delayed from the clock signal C1 by the buffer B2 that is a delay means. Based on the signal C2, it is taken in by the register R2. The data signal D2 taken into the register R2 is output as the data signal Q2, and propagates to the next logic stage L2 via the comparator 3 and the selection circuit 2. Therefore, when a malfunction is detected and a repair operation is performed, the broken line path shown in FIG. 14 becomes a path path during the repair operation, and the sum of the delay amount G1 of the buffer B2 and the delay amount G2 of the comparator 3 is a normal operation. Timing overhead for the path path of the hour. Therefore, if the next stage is timing critical, there is a possibility that a malfunction of the next stage path is induced by the delay amount G1 + G2 of the path route during the repair operation.

  Therefore, in the semiconductor device according to the present embodiment, the possibility of inducing a malfunction of the next-stage path is reduced by using the circuit shown in FIG. In the circuit shown in FIG. 15, the path from the register R0 to the register R1 via the logic stage L1 forms a critical path, and the data signal Q1 is output from the output pin of the register R1 and the next stage logic (logic stage L2 , Register R3). Further, in the circuit shown in FIG. 15, a register R2 in which the setup violation condition is relaxed by inserting a buffer B2 in the clock line is provided, and a comparator 3 for comparing the output of the register R1 and the output of the register R2 is provided. Yes.

  Further, in the circuit shown in FIG. 15, the selection circuit 2 is inserted after the registers R1 and R2. The selection circuit 2 controls to output the data signal Q1 when the error signal output from the comparator 3 is “0”, and to output the data signal Q2 when the error signal is “1”. The event propagation to the logic stage L2 is switched.

  In the circuit shown in FIG. 15, a plurality of circuits C1 to C3 including registers R1, R2, etc. are provided (three circuits in FIG. 15), and error signals from each circuit are bundled by an OR circuit 40. Therefore, if the error signal is asserted (“H”) in any one of the circuits C1 to C3, the output of the OR circuit 40 becomes “H”. Further, in the circuit shown in FIG. 15, the rising event of the OR circuit 40 is detected by the differentiation circuit 41 as a Detect signal (detect signal), and the clock signal supplied to the circuits C1 to C3 by the AND circuit 42 based on the Detect signal. Negate Clk. The cycle for negating the clock signal Clk may be set to an arbitrary cycle (usually one cycle) by a down counter, or may be set by a control signal from the system side.

  Here, the differentiation circuit 41 includes a register R4, a register R5, and an AND circuit 43. The register R4 receives an output from the OR circuit 40, a clock signal Clk, and a Power On Reset signal from the system. The register R5 receives the output of the register R4 and the clock signal Clk. The AND circuit 43 receives the output of the register R4 and the inverted output of the register R5, and outputs a Detect signal.

  The circuit shown in FIG. 15 detects the assertion of the error signal, disables the clock signal Clk of the target circuit, and performs a malfunction correction process within a period in which the clock signal is disabled. Further, in the circuit shown in FIG. 15, when the signal level of the error signal is detected, the clock signal after disabling is not restored, so the differentiation circuit 41 is provided to detect the edge instead of the signal level. In the circuit shown in FIG. 15, filtering is performed by the differentiation circuit 41 so as not to pick up a glitch of the error signal (a minute signal due to the clock phase difference). Although not shown in the circuit shown in FIG. 15, the malfunction correction cycle is limited by a counter so that the number of cycles is set in advance, or a control signal (Req) from the system is supplied to the AND circuit 42 and clocked. Controls the signal disable period.

  Next, the operation of the circuit shown in FIG. 15 will be described with reference to the timing chart shown in FIG. First, a signal input to the clock pin of the register R1 is a clock signal C1, a signal input to the data input pin is a data signal D1, and a signal output from the data output pin is a data signal Q1. A signal input to the clock pin of the register R2 is a clock signal C2, a signal input to the data input pin is a data signal D2, and a signal output from the data output pin is a data signal Q2. As described above, the event of the clock signal C2 is delayed by the buffer B2 by an amount corresponding to the insertion buffer with respect to the clock signal C1. Further, the data signal D1 captures the value of the SignalIn signal at the rising edge of the clock signal C1, and the event arrives through the delay of the logic stage L1. Similarly, the data signal D2 captures the value of the SignalIn signal at the rising edge of the clock signal C2, and the event arrives through the delay of the logic stage L1.

  First, in the first period shown in FIG. 16, since the rise events of the data signal D1 and the data signal D2 are performed before the rise event of the clock signal C1 and the clock signal C2, the registers R1 and R2 are The logic “1” is being taken in normally. However, the error signal becomes “1” due to the phase difference between the clock signal C1 and the clock signal C2, and accordingly, the Output signal in this period also becomes the value of the data signal Q2. Thereafter, the error signal returns to “0”, and accordingly, the Output signal is also switched to the value of the data signal Q1, and the operation is normally performed. However, the differentiating circuit 41 shown in FIG. 15 does not assert the Detect signal by filtering glitch pulses that are less than half a cycle. Therefore, the clock signal C1 and the clock signal C2 in the second period which is the next cycle are not disabled.

  Next, in the second period shown in FIG. 16, since the arrival of the fall event of the data signal D1 in the register R1 is not in time for the rise event of the clock signal C1, the data signal Q1 cannot capture “0”. However, since the arrival of the fall event of the data signal D2 in the register R2 is in time for the rise event of the clock signal C2, the data signal Q2 can capture “0”. Therefore, a difference occurs between the results of the register R1 and the register R2, and the result (error signal) of the comparator 3 becomes “1” (detects a setup violation).

  At this time, the path of the selection circuit 2 is switched to a path using the data signal Q2 as an output signal due to the error signal, and the output signal becomes “0”. Here, it is necessary to prevent the overhead for switching from the clock signal C1 to the clock signal C2 and the data signal Q2 to the Output signal from inducing a setup violation in the next stage. Therefore, the differentiating circuit 41 shown in FIG. 15 detects the rising edge of the error signal, confirms that it is not a glitch within half a cycle, and generates a positive pulse for the counter cycle in the Detect signal. In the present embodiment, assuming that the preset count value is 1, pulses are generated from the falling edge of the clock signal C1 to the falling edge of the clock signal C1 in the third cycle, which is the next cycle.

  In this embodiment, to simplify the description, the Detect signal is synchronized with the falling edge of the clock signal C1, but the Detect signal is synthesized in synchronization with a clock slightly faster than the clock signal C1, A configuration may be adopted in which a margin is provided for the malfunction detection period. Specifically, since a clock that is slightly faster than the clock signal C1 is clock-synthesized by the clock tree, it is theoretically possible to provide an arbitrary delay difference. Further, the circuit shown in FIG. 15 has a circuit configuration using a slightly faster clock instead of the falling edge of the clock signal C1.

  Next, in the third period shown in FIG. 16, the event of the register R0 that triggered the event from the SignalIn signal in the previous cycle (second period) reaches the data signal D1 and the data signal D2. However, the events of the clock signal C1 and the clock signal C2 are disabled, and the values of the data signal D1 and the data signal D2 are not captured as the data signal Q1 and the data signal Q2. That is, no event occurs in the Output signal. Therefore, the next-stage register R3 only needs to capture the value of the Output signal over two cycles of the second period and the third period, and a sufficient setup margin can be secured.

  If an event occurs in the SignalIn signal during the cycle (third period), the event is not propagated to the subsequent stage because the clock signals C1 and C2 are disabled. However, the above problem can be solved by adopting fail-safe means for handshaking the control signal (Req signal) and the Detect signal from the system that requests data propagation to the logic circuit such as the logic stage L1. That is, by this means, an event is not generated in the SignalIn signal while the Detect signal is asserted, and conversely, the Req signal may be negated while data preparation for the SignalIn signal is not completed.

  Next, in the fourth period shown in FIG. 16, the rise event of the data signal D1 and the data signal D2 held while the Detect signal is negated and the clock signal Clk is disabled is the clock signal C1 and the clock signal. Reached before the rise event of C2. Therefore, the register R1 and the register R2 can normally capture the logic “1”.

  As described above, the semiconductor device according to the present embodiment uses the circuit shown in FIG. 15 to reduce the possibility of inducing a malfunction of the next-stage path due to the delay amount of the path path during the repair operation. .

(Embodiment 5)
When the circuit shown in FIG. 15 is driven at the rated voltage, the setup time is observed, but when the delay increases as the drive voltage is lowered, the setup time is not observed and the metas becomes unstable. A table condition occurs. Specifically, this will be described with reference to a timing chart shown in FIG. First, when driven at the rated voltage, the register R1 captures the event of the data signal D1 at the rising edge of the clock signal C1 in the first cycle. However, in the timing chart shown in FIG. 17, the data signal Q1, which is the output of the register R1, changes from “0” to “1” in an unstable state (metastable) as the drive voltage is lowered. Similarly, at the rise of the clock signal C1 in the second cycle shown in FIG. 17, the data signal Q1 that is the output of the register R1 is unstable from “1” to “0” (metastable) as the drive voltage is lowered. It has transitioned to.

  Therefore, the semiconductor device according to the present embodiment employs a circuit in which a metastability detection circuit 50 is provided for the output of the register R1, as shown in FIG. In the circuit shown in FIG. 18, the metastable detection circuit 50 detects the occurrence of metastable, and controls so that the output of the circuit does not transition to an unstable state. That is, the metastability detection circuit 50 shown in FIG. 18 processes the output MSD signal and the output of the comparator 3 by the OR circuit 51, and outputs an error signal regardless of the output of the register R1 when the metastable is detected. H ”. The metastability detection circuit 50 controls the output of the register R2 to be selected by the selection circuit 2.

  A circuit diagram of the metastability detection circuit 50 is shown in FIG. A metastability detection circuit 50 shown in FIG. 19 includes a pair of a low threshold (Lvt) PMOS (P-channel Metal-Oxide Semiconductor) 52 and a high threshold (Hvt) NMOS (N-channel Metal-Oxide Semiconductor) 53. An inverter using a transistor is provided. Further, the metastability detection circuit 50 shown in FIG. 19 includes an inverter using a pair transistor of a high threshold PMOS 54 and a low threshold NMOS 55, and detects a metastable by an XOR circuit 56 that calculates XOR of both inverters. Yes.

  Next, the operation of the circuit shown in FIGS. 18 and 19 will be described with reference to the timing chart shown in FIG. Here, the output I1 is the inverter output of the low threshold PMOS 52 and the high threshold NMOS 53, the output I2 is the inverter output of the high threshold PMOS 54 and the low threshold NMOS 55, and the MSD is the XOR of the output I1 and the output I2. It is the result of logic. Although not shown in FIG. 18, the OR circuit 40 and the differentiation circuit 41 shown in FIG. 15 are provided at the output destination of the error signal, and the clock signal C1 is based on the Detect signal that is the output of the differentiation circuit 41. , C2 are controlled.

  First, in the first period shown in FIG. 20, the data signals D1 and D2 transition from “0” to “1” simultaneously with the rise of the clock signal C1, but the data signal Q1 is metastable because of the drive voltage step-down. It is in a table state. Since the output I1 is less sensitive to the transition output from “1” to “0” than the output I2, the output I2 changes to “0” faster than the output I1 and is output with a slight delay. I1 transitions to “0”. The MSD between the delay difference between the output I1 and the output I2 becomes “1”, and the metastable can be detected. In response to the metastable detection result (MSD = “1”), the error signal becomes “1”, and the Detect signal becomes “1”.

  Next, in the second period shown in FIG. 20, in response to the Detect signal being “1”, the clock signals C1 and C2 are negated, and the result of the output Q is restored during this period.

  Next, in the third period shown in FIG. 20, the data signals D1 and D2 transition from “1” to “0” simultaneously with the rise of the clock signal C1, but the data signal Q1 is changed to decrease the drive voltage. Metastable state. The cycle is opposite to the case of the first cycle, and the output I2 is faster than the output I2 because the sensitivity of the transition output from “0” to “1” is poor compared to the output I1. The output I2 changes to “1” with a slight delay. The MSD between the delay difference between the output I1 and the output I2 becomes “1”, and the metastable can be detected. In response to the metastable detection result (MSD = “1”), the error signal becomes “1”, and the Detect signal becomes “1”.

  Next, in the fourth period shown in FIG. 20, in response to the Detect signal being “1”, the clock signals C1 and C2 are negated, and the result of the output Q is restored during this period.

  Next, in the fifth cycle shown in FIG. 20, since the data signals D1 and D2 transition from “0” to “1” before the rising of the clock signal C1, the data signals Q1 and Q2 are both “normally”. 1 "can be captured.

  As described above, since the circuit shown in FIGS. 18 and 19 is employed in the semiconductor device according to the present embodiment, the presence or absence of metastable occurrence can be detected, and the circuit output Q transitions to an unstable state. Can be controlled to not. In the malfunction determination circuit according to the present embodiment, the circuit configuration including the differentiation circuit and the selection circuit 2 has been described. However, the present invention is not limited to this, and a configuration without the differentiation circuit and the selection circuit 2 is illustrated in FIG. The circuit may further include a circuit that detects a setup violation of the Enable signal shown in FIG.

(Embodiment 6)
The circuit shown in FIG. 21 is provided with a register R2 that has a margin (Positive Slack) with respect to the register R1 that is an actual operation register as much as the buffer chain B2 that is a delay means is inserted into the clock line. . The data signal D1 output from the logic stage L1 is input to the register R1. A register R0 is connected to the preceding stage of the logic stage L1. On the other hand, the data signal Q1 output from the register R1 is input to the next logic stage L2 and also to the comparator 3.

  The comparator 3 compares the data signal Q1 output from the register R1 with the data signal Q2 output from the register R2, and outputs an error signal if they do not match. Therefore, the circuit shown in FIG. 21 can dynamically detect the setup violation of the register R1 by the delay of the buffer chain B2 inserted in the clock line. In the circuit shown in FIG. 21, a selection circuit 50 is provided to adjust the delay amount of the buffer chain B2. The selection circuit 50 is driven based on a selection signal Sel input from the outside. Then, the delay amount (Delay) of the buffer chain B2 included in the similar circuit (error detection FF) is uniformized with an optimum value in all of the plurality of circuits. However, there is actually a close relationship between the delay amount to be inserted and the speed margin, and it is necessary to increase the delay amount to be inserted in a path with a smaller speed margin. However, the excessively inserted delay amount causes a circuit scale and power consumption overhead and also has a problem that the hold tolerance is weakened. On the contrary, there is a problem that an excessively inserted delay amount increases the area where the expected value register (R2) fails as well as the operation target register (R1), and the malfunction detection spot becomes narrow.

  Therefore, in this embodiment, delay paths are grouped according to a speed margin, and an optimum delay amount is inserted into each group. FIG. 22 is a graph showing the relationship between the slack amount corresponding to the speed margin and the number of passes. In the graph shown in FIG. 22, with respect to the slack amount from 0 to 1 shown on the horizontal axis, for example, four stages of buffers having a delay amount of 0.5 ns are inserted, and for the slack amount from 1 to 2, Three stages of the buffers are inserted, two stages of the buffers are inserted for the slack amounts from 2 to 3, and four stages of the buffers are inserted for the slack amounts from 3 to 4. Thereby, in this Embodiment, the overhead of an area or power consumption can be suppressed, maintaining an operation margin.

  Before concrete description, the circuit (error detection FF) shown in FIG. 23A is symbolized as shown in FIG. The number B at the center of FIG. 23B shows the number of stages of the buffer B2 inserted in the clock line of the register R2 shown in FIG. For example, B-1 shown in FIG. 23B indicates that one stage of buffer is inserted. In the circuit shown in FIG. 23A, the larger the buffer amount, the larger the delay difference between the register R1 and the register R2, and the greater the margin for detecting malfunction (detection margin). There is a problem that an increase in scale, an increase in power consumption, and a hold margin phenomenon occur. Further, the circuit shown in FIG. 23A is almost the same as the circuit configuration shown in FIG.

  Next, FIG. 24 shows a circuit configuration when four circuits (U1, U2, U3, U4) shown in FIG. In FIG. 24, the circuit in FIG. 23A is represented by using FIG. 23B symbolized. In the circuit configuration shown in FIG. 24, a preceding stage (logic stage) having a different logic amount is inserted in each circuit (U1, U2, U3, U4). Therefore, the speed margin (slack) with respect to the frequency of each circuit (U1, U2, U3, U4) is set to 0 ns, 0.5 ns, 1.0 ns, and 1.5 ns, respectively. Further, the delay amount per stage of the buffer to be inserted is 0.5 ns. In the circuit configuration shown in FIG. 24, the buffer inserted in each circuit (U1, U2, U3, U4) has one stage.

  Next, the operation of the circuit configuration shown in FIG. 24 will be described with reference to the timing chart shown in FIG. In the timing chart shown in FIG. 25, it is assumed that the power supply voltage is lowered every time the cycle progresses so that a delay overhead of 0.5 ns is generated at the data terminal D of each circuit (U1, U2, U3, U4). . Therefore, in the fourth period, the slack of 1.5 ns is reduced compared to the first period (delay increase of 1.5 ns).

  In the first cycle shown in FIG. 25, the setup violation of the circuit U1 can be detected (the other circuits U2, U3, U4 have no setup violation). However, after the second period, the setup violation can be detected because the margin of the register R2, which is the phase difference of the clock signal C2 with respect to the clock signal Clk, is insufficient even though the circuit U1 has caused the setup violation. Absent.

  Next, FIG. 26 shows a timing chart when the buffer amount is increased to four stages in the circuit configuration shown in FIG. Similarly to the above, FIG. 26 also assumes that the power supply voltage is lowered each time the cycle progresses so that a delay overhead of 0.5 ns occurs at the data terminal D of each circuit (U1, U2, U3, U4). . Accordingly, in the fourth period, the slack of 1.5 ns is reduced with respect to the first period.

  In the first cycle shown in FIG. 26, the setup violation of the circuit U1 can be detected (the other circuits U2, U3, U4 have no setup violation). However, after the second period, the setup violation can be detected until the fourth period in which the circuit U1 causes the setup violation.

  On the other hand, with respect to the circuit U2, the setup violation is detected for the first time in the second period, and then the setup violation can be detected until the fourth period. Regarding the circuit U3, the setup violation is detected for the first time in the third period, and thereafter, the setup violation can be detected until the fourth period. Regarding the circuit U4, the setup violation is detected for the first time in the fourth period.

  Therefore, it is only necessary to detect setup violations in the second cycle and thereafter for the circuit U2, in the third and subsequent cycles for the circuit U3, and in the fourth and subsequent cycles for the circuit U4. In the normal circuit design, the lower limit of the voltage operation is determined, and it is not necessary to secure a margin amount exceeding it. Therefore, by reducing the delay amount inserted into the circuit (U1, U2, U3, U4) as the slack amount increases, the overhead of area and power consumption can be suppressed as much as possible without reducing the margin for detecting malfunction. it can.

  Next, FIG. 27 shows a circuit configuration in which the delay amount to be inserted is optimized based on the timing charts shown in FIG. 25 and FIG. In the circuit configuration shown in FIG. 27, the number of buffer stages is adjusted so that the delay amount increases as the slack amount decreases. Specifically, in the circuit configuration shown in FIG. 27, since the slack amount of the circuit U1 is as small as 0 ns, a four-stage buffer (B4) is provided, and the circuit U2 having a slack amount of 0.5 ns has a three-stage buffer (B3). ), A circuit U3 having a slack amount of 1.0 ns is provided with a two-stage buffer (B2), and a circuit U4 having a slack amount of 1.5 ns is provided with a one-stage buffer (B1).

  That is, in the circuit configuration of the semiconductor device according to the present embodiment, after the circuit layout, the slack amount of each delay path is analyzed, and a circuit (error detection FF) having a slack amount that falls within the delay amount of one buffer stage is grouped. And bundle them. In the circuit configuration of the semiconductor device according to the present embodiment, an optimum buffer is inserted into the grouped circuit (error detection FF).

  The timing chart shown in FIG. 28 explains the operation of the circuit configuration shown in FIG. In the circuit configuration shown in FIG. 27, detection is correctly performed at a location where a setup violation check is necessary (a point where the data signal D changes at a location surrounded by a broken line). That is, in the timing chart shown in FIG. 28, the setup violation occurs after the first cycle for the circuit U1, after the second cycle for the circuit U2, after the third cycle for the circuit U3, and after the fourth cycle for the circuit U4. Can be detected.

(Embodiment 7)
In the fifth embodiment, the malfunction determination circuit (error detection FF) included in the semiconductor device is grouped according to the slack amount, and an optimum amount of buffer is inserted into the malfunction determination circuit of each group. However, a circuit with an extremely small amount of slack in a semiconductor device has a problem in that a large number of buffers need to be inserted, resulting in an increase in area and power consumption overhead.

  Below, it demonstrates using a specific example. In the circuit shown in FIG. 29, the path having the register R3 as an end point has a timing critical path from the register R1 to the register R3, and also has other paths such as from the register R2 to the register R3. . FIG. 30 shows a circuit configuration when the register R3 shown in FIG. 29 is replaced with the malfunction determination circuit (error detection FF) described in FIG. In the circuit configuration shown in FIG. 30, the path from the register R1 to the register R3-1 is a timing critical path, but there is also a path from the register R2 to the register R3-2 in addition to this path.

  However, if it is assumed that the path from the register R2 to the register R3-2 causes a hold violation, it is necessary to insert a buffer or a delay cell in the path from the register R2 to the register R3-2 as a countermeasure against the hold violation. . That is, when the delay amount of the buffer 1 inserted into the clock line of the register R3-2 is large, the delay amount of the buffer 1 is set in the path from the register R2 to the register R3-2 as in the circuit configuration shown in FIG. It is necessary to insert a delay means 60 such as an equivalent buffer or delay cell. For this reason, the circuit configuration shown in FIG. 31 has a problem that the overhead increases in terms of area and power consumption.

  Therefore, in the semiconductor device according to the present embodiment, in a circuit configuration having a path that causes a hold violation, a lockup latch and an inversion FF are inserted instead of a buffer and a delay cell to be inserted as a countermeasure against the hold violation. That is, in the present embodiment, as shown in FIG. 32, a register R4 that functions as a lock-up latch is inserted in a path from the register R2 to the register R3-2. Alternatively, as shown in FIG. 33, a register R4 functioning as an inversion FF is inserted in a path from the register R2 to the register R3-2.

  In the circuit configuration shown in FIG. 32 or the circuit configuration shown in FIG. 33, a half cycle of the clock signal is obtained by inserting a register R4 functioning as a lock-up latch or an inverting FF instead of inserting many buffer cells and delay cells. A minute delay can be earned, and a hold violation can be resolved. Further, the circuit configuration shown in FIG. 32 and the circuit configuration shown in FIG. 33 do not require insertion of a large number of buffer cells and delay cells unlike the circuit configuration shown in FIG. Overhead can be reduced.

  Next, the operation of the circuit configuration shown in FIG. 30 causing the hold violation will be described with reference to the timing chart shown in FIG. In the circuit configuration shown in FIG. 30, the path from the register R1 to the register R3-1 causes a setup violation, and the expected value is obtained from the path from the register R1 to the register R3-2. In the circuit configuration shown in FIG. 30, the path from the register R2 to the register R3-2 is a path that causes a hold violation. In the following description of the operation, it is assumed that the logic of each timing path is positive in any state in order to simplify the operation.

  First, in the first period shown in FIG. 34, the content of the register R1 changes from “0” to “1” at the rising edge of the clock signal C1.

  Next, in the second period shown in FIG. 34, the value is determined according to the rise event of the register R1 in the first period. However, since the register R3-1 causes a setup violation, “1” is set. It cannot be imported and remains “0”. On the other hand, the register R3-2 can normally capture “1” by the delayed clock signal C2. Further, the next fall event from “1” to “0” occurs in the register R1.

  Next, in the third period shown in FIG. 34, as in the second period, the value is determined according to the fall event of the register R1 in the second period, but the register R3-1 causes a setup violation. Therefore, “0” cannot be captured, and the final value “1” in the previous cycle is captured. On the other hand, the register R3-2 can normally capture “0” by the delayed clock signal C2.

  Next, in the fourth period shown in FIG. 34, the content of the register R2 transitions from “0” to “1” at the rising edge of the clock signal C1. Therefore, the event in the register R2 is originally scheduled to be reflected as a transition of the registers R3-1 and R3-2 in the fifth cycle which is the next cycle. However, since the register R3-2 causes a hold violation, “1” is fetched in the fourth period as indicated by an arrow in the drawing. That is, in the fourth period, the register R3-2 that is an expected value register holds an incorrect result.

  Next, in the fifth cycle shown in FIG. 34, the content of the register R2 transitions from “1” to “0” at the rising edge of the clock signal C1. Therefore, the event in the register R2 is originally scheduled to be reflected as the transition of the registers R3-1 and R3-2 in the 6th cycle which is the next cycle. However, since the register R3-2 causes a hold violation, “0” is fetched in the fifth period as indicated by the arrow in the figure as in the fourth period.

  Next, as a countermeasure against the hold violation, the operation of the circuit configuration shown in FIG. 32 or FIG. 33 in which a register R4 functioning as a lock-up latch or an inversion FF is inserted in the path from the register R2 to the register R3-2. This will be described using the timing chart.

  In the timing chart shown in FIG. 35, the event propagation is performed with the clock signal C2 delayed by the amount of the buffer inserted with respect to the clock signal C1. In the timing chart shown in FIG. 35, each of the registers R1, R2, and R3-1 captures a data signal at the rising edge of the clock signal C1, and the register R3-2 captures a data signal at the rising edge of the clock signal C2. Assume that the register R4 captures data at the falling edge of the clock signal C1.

  Next, in the timing chart shown in FIG. 35, the operation from the first period to the third period is equivalent to the operation of the timing chart shown in FIG.

  Next, in the fourth period shown in FIG. 35, the content of the register R2 changes from “0” to “1” at the rising edge of the clock signal C1. The register R3-2 is a path that causes a hold violation. However, as shown in FIG. 32 or FIG. 33, a lockup latch or an inversion FF is inserted between the register R2 and the register R3-2. For this reason, in the fourth period shown in FIG. 35, the event “1” generated in the register R2 is not directly taken into the register R3-2, but temporarily appears in the register R4 at the falling edge of the clock signal C1 as indicated by the arrow in the figure. After being fetched, it is fetched into the register R3-2 in the fifth cycle.

  Next, in the fifth cycle shown in FIG. 35, “1” taken into the register R4 is taken into the register R3-1 at the rising edge of the clock signal C1, and taken into the register R3-2 at the rising edge of the clock signal C2. In addition, the content of the register R2 changes from “1” to “0” at the rising edge of the clock signal C1, but the register R3-2 directly takes in the event “0” generated in the register R2 as in the fourth period. Instead, as indicated by the arrow in the figure, it is once taken into the register R4 at the falling edge of the clock signal C1.

  Next, in the sixth cycle shown in FIG. 35, “0” taken into the register R4 is taken into the register R3-1 at the rising edge of the clock signal C1, and taken into the register R3-2 at the rising edge of the clock signal C2.

  As described above, in the semiconductor device according to the present embodiment, the circuit configuration shown in FIG. 32 or FIG. 33 is employed to reduce overhead in terms of area and power consumption and to avoid malfunction due to hold violation. The data can be transferred correctly.

(Embodiment 8)
In the sixth embodiment, delay paths are grouped according to a speed margin, and an optimum delay amount is inserted for each group. Specifically, the effect of suppressing an increase in circuit scale and power consumption by individually inserting the buffer B2 and setting the optimum insertion buffer amount in the circuit (error detection FF) of FIG. 23 has been described. However, changing the amount of insertion buffer individually means assigning one clock domain for each error detection FF, and when actually placing and routing, clock skew and latency control do not work well, There may be a case where a desired circuit scale and power consumption cannot be obtained.

  Therefore, in the present embodiment, an optimal grouping method that takes the above risks into account will be described. First, FIG. 36 shows a flowchart of a grouping algorithm performed in the present embodiment. For example, the case where there are 21 delay paths will be described with reference to the flowchart shown in FIG. The negative slack amount (Negative-Slack) of 21 passes is 0.048, 0.048, 0.045, 0.045, 0.036, 0.035, 0.033, 0.027, 0.024, 0.022, 0.021, 0.019, 0.017, 0.015, 0.015, 0.008, 0.007, 0.006, respectively. , 0.005, 0.001, and 0.001. Note that the normal negative slack amount (Negative-Slack) is a negative value, but in order to simplify the explanation, all are expressed as positive values.

  In step S1 of the flowchart shown in FIG. 36, the maximum and minimum negative slack amounts (Maximum-Negative-Slack (MaxNS), Minimum-Negative-Slack (MinNS: initial value is 0)), total negative slack amount (Total-Negative -Slack (TNS)) is calculated. Further, the TNS calculated in step S1 is set as the initial criterion. Specifically, MaxNS = 0.048, MinNS = 0.0, TNS = 0.478.

  Next, in step S2, an arbitrary negative slack amount from MaxNS to MinNS is selected as DivNS (selected value), and all delay paths belonging to MaxNS to DivNS are selected as group A and all delays belonging to DivNS to MinNS. Divide the path into group B. As shown in FIG. 37 showing slack timing at 0.7 V, the delay path from MaxNS to MinNS is divided into group A and group B with DivNS as a boundary. Further, in step S2, the sum of the differences from the individual delay paths belonging to group A to DivNS and the sum of the differences from the individual delay paths belonging to group B to MinNS are calculated, and the sum of both differences is calculated as an evaluation function. As the total negative slack amount (TNS).

  Next, in step S3, DivNS is swept sequentially from MaxNS to MinNS, and DivNS that minimizes the total negative slack amount (TNS) that is an evaluation function is obtained. Specifically, in the above example, DivNS is swept from MaxNS (0.048) to MinNS (0.0) to determine the DivNS that minimizes TNS. In this example, since the DivNS sweep accuracy is 0.01, there are five possible values for DivNS: 0.00, 0.01, 0.02, 0.03, and 0.04. The possible TNS for each DivNS is TNS = 0.478 when DivNS = 0.00, TNS = 0.328 when DivNS = 0.01, TNS = 0.258 when DivNS = 0.02, TNS = 0.268 when DivNS = 0.03, and DivNS = 0.04 TNS = 0.318.

  Next, in step S4, a value obtained by performing predetermined weighting on the minimum DivNS obtained in step S3 is compared with the criteria before the current division. If it is larger, the process ends. Is accepted and the obtained value is updated as a new criterion. In the above example, the minimum value of TNS is 0.258 when DivNS = 0.02, so this value is compared with the initial criteria (0.478). If the weighting function at this time is 1.5 * TNS + 0.05, the weighted value is 0.437, which is below the criteria, so this division is accepted and divided as follows. Group A is 0.048, 0.048, 0.045, 0.045, 0.036, 0.035, 0.033, 0.027, 0.024, 0.022, 0.021, and Group B is 0.019, 0.017, 0.015, 0.015, 0.008, 0.007, 0.006, 0.005, 0.001, 0.001. . At this time, the criteria are updated from 0.478 to 0.258.

  Next, in step S5, the same is recursively performed for the two groups after the division. The minimum value of TNS in group A is 0.084 when DivNS = 0.04, and the weighted value is 0.176, and the division is accepted. The criteria at this time are updated to 0.084. Further, the minimum value of TNS in group B is 0.054 when DivNS = 0.01, and the weighted value is 0.131, and the division is accepted. The criteria at this time are updated to 0.054.

  Therefore, the groups after acceptance of the above division are as follows. Group A-A (GA-A) is 0.048, 0.048, 0.045, 0.045, Group A-B (GA-B) is 0.036, 0.035, 0.033, 0.027, 0.024, 0.022, 0.021, Group B-A (GB-A ) Is 0.019, 0.017, 0.015, 0.015, and Group BB (GB-B) is 0.008, 0.007, 0.006, 0.005, 0.001, 0.001. At this time, with respect to Group A-A, Group B-A, and Group B-B, the division with DivNS accuracy 0.01 cannot be performed any more, so the division process is stopped and only the group A-B is continued.

  The minimum value of TNS in group A-B is 0.028 when DivNS = 0.03, and the weighted value is 0.092, which exceeds the criterion 0.084, so the division is rejected. Therefore, when the 21 paths that are the delay paths are divided by applying the algorithm shown in FIG. 36, grouping is performed in the above four ways (group A-A, group AB, group BA, group BB). Is done.

  Next, the effect when grouping delay paths using the algorithm shown in FIG. 36 will be described. FIG. 38 is a schematic diagram for explaining the delay paths subjected to the above grouping. In the conventional method, a buffer that compensates for a delay of a maximum slack of 0.048 ns is inserted in all 21 paths. Assuming that the hold overhead function is the delay amount * the number of paths, the overhead index is 0.048 * 21 = 1.008.

  On the other hand, in the present embodiment, since the insertion delay amount is critical slack of each group, the insertion delay amount of group A-A remains 0.048 ns as shown in FIG. ns, group B-A is reduced to 0.019 ns, and group BB is reduced to 0.008 ns. As a result, the overhead index becomes 0.048 * 4 + 0.036 * 7 + 0.019 * 4 + 0.008 * 6 = 0.568.

  Therefore, it can be seen that the overhead index is reduced to 0.568 / 1.008 * 100 = 56.3%. FIG. 38 shows the number of insertion buffers to be inserted in each group. The conventional method and group A-A are 5, group A-B is 4, group B-A is 2, group B-B. Is 1.

  Furthermore, in this embodiment, the logic can be divided as shown in FIG. 39, and a part of the processes can be processed in advance to reduce the latency.

  In the error detection, if any one of the error detection FFs distributed in the application circuit fails, an alert signal to that effect must be issued, and thus the logical sum of each error detection signal must be taken. In the conventional method, since error detection for all 21 paths is performed after a clock phase difference of maximum slack of 0.048 ns, 21 input logical sums have to be processed all at once. This process required 100 ps.

  On the other hand, in this embodiment, since the insertion delay amount becomes the critical slack of each group, the insertion delay amount of group A-A remains 0.048 ns as shown in FIG. ns, group B-A is 0.019 ns, group BB is 0.008 ns, error detection is performed at each timing, and each logical sum precedes in the order of group BB, group BA, group AB Can be processed automatically. Assuming that the logical sum processing up to group A-B has been completed up to the clock phase difference of group A-A, in the present embodiment, the total of these propagation signals and four paths belonging to group A-A is calculated. It is only necessary to process a 5-input logical sum. Assume that this process requires 40 ps. Therefore, in this embodiment, it can be seen that the latency is also reduced to 40/100 * 100 = 40.0%.

It is a circuit diagram of a circuit which is a premise of the present invention. It is a timing chart of the circuit used as the premise of this invention. FIG. 3 is a circuit diagram of a malfunction determination circuit according to the first embodiment of the present invention. FIG. 3 is a circuit diagram of a malfunction determination circuit according to the first embodiment of the present invention. It is a circuit diagram which shows the structure at the time of providing the several malfunction determination circuit based on Embodiment 1 of this invention. 3 is a timing chart of the malfunction determination circuit according to the first embodiment of the present invention. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. It is a circuit diagram used as the premise of the malfunction determination circuit based on Embodiment 2 of this invention. It is the schematic for demonstrating the clip of a clock signal. It is a circuit diagram of a malfunction determination circuit according to the second embodiment of the present invention. It is a timing chart of the malfunction determination circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram of a malfunction determination circuit according to Embodiment 3 of the present invention. It is a timing chart of the malfunction determination circuit which concerns on Embodiment 3 of this invention. It is a circuit diagram used as the premise of the malfunction determination circuit based on Embodiment 4 of this invention. It is a circuit diagram of the malfunction determination circuit based on Embodiment 4 of this invention. It is a timing chart of the malfunction determination circuit which concerns on Embodiment 4 of this invention. It is the schematic for demonstrating a metastable. FIG. 10 is a circuit diagram of a malfunction determination circuit according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram of a metastability detection circuit according to a fifth embodiment of the present invention. It is a timing chart of the malfunction determination circuit based on Embodiment 5 of this invention. It is a circuit diagram used as the premise of the malfunction determination circuit based on Embodiment 6 of this invention. It is a figure which shows the relationship between slack amount and pass amount. It is a circuit diagram of the malfunction determination circuit based on Embodiment 6 of this invention. It is a circuit diagram which shows the structure at the time of providing the several malfunction determination circuit based on Embodiment 6 of this invention. It is a timing chart of the malfunction determination circuit based on Embodiment 6 of this invention. It is a timing chart of the malfunction determination circuit based on Embodiment 6 of this invention. It is a circuit diagram which shows another structure at the time of providing the several malfunction determination circuit based on Embodiment 6 of this invention. It is a timing chart of the malfunction determination circuit based on Embodiment 6 of this invention. It is a figure for demonstrating a hold violation. It is a figure for demonstrating hold violation. It is a figure for demonstrating the countermeasure of a hold violation. It is a circuit diagram of a malfunction determination circuit according to a seventh embodiment of the present invention. It is a circuit diagram of a malfunction determination circuit according to a seventh embodiment of the present invention. 6 is a timing chart of a malfunction determination circuit in which a hold violation has occurred. It is a timing chart of the malfunction determination circuit based on Embodiment 7 of this invention. It is a flowchart for demonstrating the algorithm which concerns on Embodiment 8 of this invention. It is a figure for demonstrating the delay path grouped by the algorithm which concerns on Embodiment 8 of this invention. It is a schematic diagram for demonstrating the effect of the algorithm which concerns on Embodiment 8 of this invention. It is a schematic diagram for demonstrating the effect of the algorithm which concerns on Embodiment 8 of this invention.

Explanation of symbols

  1,30 buffer, 2,21,50 selection circuit, 3,31,56 comparator, 4,20,22,42,43 AND circuit, 5,6,7 MUX, 10 digital circuit, 11 clock generator, 12 Regulator, 13 Control circuit, 14 Memory, 40, 51 OR circuit, 41 Differentiation circuit, 60 Delay means, 50 Metastability detection circuit, 52, 54 PMOS, 53, 55 NMOS, 56 XOR circuit.

Claims (12)

A semiconductor device comprising a plurality of logic circuits and a plurality of determination circuits that perform malfunction determination based on data from the logic circuits,
The determination circuit includes:
A first register for fetching data from the logic circuit at a predetermined timing of a clock signal;
Delay means for delaying the clock signal;
A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay means;
A comparator that compares the output of the first register with the output of the second register and outputs an error signal;
A semiconductor device comprising: scanning means for holding the comparison result of the comparator while shifting the second register to a shift register and propagating the error signal held in the second register to the next stage. A semiconductor device comprising a plurality of logic circuits and a plurality of determination circuits that perform malfunction determination based on data from the logic circuits,
  The determination circuit includes:
  First clock control means for controlling transmission of the clock signal based on the enable signal;
  A first register for fetching data from the logic circuit at a predetermined timing of the clock signal controlled by the first clock control means;
  Delay means for delaying the clock signal;
  Second clock control means for controlling transmission of the clock signal through the delay means based on the enable signal;
  A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal controlled by the second clock control means;
  A comparator that compares the output of the first register with the output of the second register and outputs an error signal;
  A fail-safe circuit that is inserted into the line of the enable signal that is input to the second clock control means and prevents the glitch from riding on the clock signal that has passed through the delay means;
  A semiconductor device comprising: a third register that is inserted before the second clock control means and determines the event content of the enable signal. A semiconductor device comprising a plurality of logic circuits and a plurality of determination circuits that perform malfunction determination based on data from the logic circuits,
  The determination circuit includes:
  First clock control means for controlling transmission of the clock signal based on the enable signal;
  A first register for fetching data from the logic circuit at a predetermined timing of the clock signal controlled by the first clock control means;
  First delay means for delaying the clock signal;
  Second clock control means for controlling transmission of the clock signal through the first delay means based on the enable signal;
  A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal controlled by the second clock control means;
  A comparator that compares the output of the first register with the output of the second register and outputs an error signal;
  A semiconductor device, further comprising: a detection circuit that detects a setup violation of the enable signal for a plurality of the determination circuits whose clock signals are controlled by the same enable signal. The semiconductor device according to claim 3,
  The detection circuit includes:
  A third register for capturing the enable signal at a predetermined timing of the clock signal;
  Second delay means for delaying the clock signal;
  A semiconductor device comprising: a fourth register that is logically equivalent to the third register that takes in the enable signal at a predetermined timing of the clock signal that has passed through the second delay means. A semiconductor device comprising a plurality of logic circuits and a plurality of determination circuits that perform malfunction determination based on data from the logic circuits,
  The determination circuit includes:
  A first register for fetching data from the logic circuit at a predetermined timing of a clock signal;
  Delay means for delaying the clock signal;
  A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay means;
  A comparator that compares the output of the first register with the output of the second register and outputs an error signal;
  A selection circuit that selects either the output of the first register or the output of the second register based on the error signal and propagates to the logic circuit in the next stage;
  A semiconductor device comprising: a differential circuit that filters a glitch of the error signal, detects a rising edge of the error signal, and controls the clock signal to stop for a predetermined period. The semiconductor device according to claim 5,
  The differentiating circuit handshakes a detect signal for controlling the clock signal and a control signal for requesting data propagation to the logic circuit so that the event of the data signal does not occur during the stop period of the clock signal. A semiconductor device further comprising fail-safe means for controlling the semiconductor device. The semiconductor device according to claim 5 or 6, wherein
  A metastability detection circuit for detecting metastable at a stage subsequent to the first register;
  2. A semiconductor device according to claim 1, wherein when the metastable is detected, the determination circuit always determines a malfunction based on an output of the metastability detection circuit. A semiconductor device comprising a plurality of logic circuits and a plurality of determination circuits that perform malfunction determination based on data from the logic circuits,
  The determination circuit includes:
  A first register for fetching data from the logic circuit at a predetermined timing of a clock signal;
  Delay means for delaying the clock signal;
  A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay means;
  A comparator that compares the output of the first register with the output of the second register and outputs an error signal;
  A metastability detection circuit for detecting metastable at a subsequent stage of the first register;
  2. A semiconductor device according to claim 1, wherein when the metastable is detected, the determination circuit always determines a malfunction based on an output of the metastability detection circuit. A semiconductor device according to claim 7 or claim 8, wherein
  The metastability detection circuit includes:
  A first inverter composed of a first PMOS and a second NMOS having a threshold higher than that of the first PMOS;
  A second inverter composed of a third PMOS and a fourth NMOS having a lower threshold than the third PMOS;
  A semiconductor device comprising: a logic circuit that performs an XOR operation between the output of the first inverter and the output of the second inverter. A semiconductor device comprising a plurality of logic circuits and a plurality of determination circuits that perform malfunction determination based on data from the logic circuits,
  The determination circuit includes:
  A first register for fetching data from the logic circuit at a predetermined timing of a clock signal;
  Delay means for delaying the clock signal;
  A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay means;
  A comparator that compares the output of the first register with the output of the second register and outputs an error signal;
  A semiconductor device, wherein a plurality of the determination circuits are grouped in a unit in which a delay amount of the delay means can be controlled, and the delay means having a delay amount corresponding to the determination circuits belonging to each group is provided. A semiconductor device comprising a plurality of logic circuits and a plurality of determination circuits that perform malfunction determination based on data from the logic circuits,
  The determination circuit includes:
  A first register for fetching data from the logic circuit at a predetermined timing of a clock signal;
  Delay means for delaying the clock signal;
  A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay means;
  A comparator that compares the output of the first register with the output of the second register and outputs an error signal;
  A semiconductor device, wherein a lock-up latch or an inversion flip-flop circuit is inserted on a path in which a hold violation occurs before the determination circuit. The semiconductor device according to claim 10,
  The grouping is
  Calculate the maximum and minimum values from the negative slack amount for each pass,
  Dividing into a group from the maximum value to the selected value and a group from the selected value to the minimum value, find the sum of the differences from the selected value or the minimum value in each group, and sum the sum As an evaluation function,
  Obtaining the selected value that minimizes the evaluation function;
  Compare the processing value weighted with a predetermined weight on the selection value that is the minimum, and stop the division if it is large, if it is small, approve the division and update the setting value to the processing value,
  A semiconductor device, wherein a plurality of groups are formed by recursively dividing the divided groups up to a predetermined condition.

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