JP2008042367A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of recognizing a circuit malfunction (a setup contravention) during an actual operation without lowering the throughput of the whole system. <P>SOLUTION: The semiconductor device has a first register R1, a delay means B2, a second register R2, and a comparator 1. The first resistor R1 takes in a data from a logic circuit (L1) at the fixed timing of a clock signal. The delay means B2 delays the clock signal. The second register R2 is logically equivalent to the first register R1, and takes in the data from the logic circuit (L1) at the fixed timing of the clock signal through the delay means B2. The comparator 1 compares an output Q1 from the first register R1 and the output Q2 from the second register R2, and outputs a first error signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of detecting a malfunction.

  In a semiconductor device, due to various variations and the like, variations also occur in path delays that terminate at a certain storage element. The path delay operates without any problem in the simulation, but the actual machine sometimes fails to satisfy the timing constraint (setup violation) due to variations in the path delay.

  Therefore, the semiconductor device sometimes has a mechanism for dynamically detecting timing constraints. Regarding this mechanism, for example, a circuit called Razor (hereinafter referred to as Razor circuit) shown in Non-Patent Document 1 is known. The Razor circuit shown in Non-Patent Document 1 is a circuit that combines a flip-flop circuit that captures data in synchronization with the rising edge of the clock signal clk and a latch circuit that captures data during the High period of the clock signal clk. The Razor circuit includes a comparator that compares the output of the flip-flop circuit and the output of the latch circuit, and a selector circuit that switches between the normal logic and the output of the latch circuit based on the result of the comparator. .

  In the Razor circuit shown in Non-Patent Document 1, the latch circuit opens in synchronization with the timing at which the flip-flop circuit captures data, and the clock signal clk captures data in the High period. That is, the Razor circuit shown in Non-Patent Document 1 uses the time difference between the flip-flop circuit and the latch circuit as a malfunction (setup violation) for data that arrives from the rising edge of the clock signal clk to the High period of the clock signal clk. Can be detected.

  Next, Patent Document 1 has a circuit configuration in which two sub-synchronization circuits having the same configuration as the main synchronization circuit are provided, and the sub-synchronization circuit operates at a double cycle of the main synchronization circuit. Therefore, in the circuit shown in Patent Document 1, the malfunction caused by the setup in the main synchronization circuit can be recovered by the sub synchronization circuit.

  Next, in Patent Document 2, a combinational logic circuit is interposed as a critical path between a sending-side flip-flop circuit and a receiving-side flip-flop circuit operating with the same clock signal clk. In Patent Document 2, the delay state in the critical path is measured and displayed outside the LSI.

Dan Ernest et al., `` Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation '', IEEE MICRO, 2004, P.10-20 US Pat. No. 6,985,547 JP 2005-214732 A

  However, in the circuit shown in Non-Patent Document 1, since the error signal is asserted due to the setup violation until the next cycle, the error signal is asserted even if the setup violation does not occur in the next cycle. There was a problem. Therefore, in the circuit shown in Non-Patent Document 1, in order to avoid the problem, data (normal logic) is fetched after adding a cycle for negating the error signal to the cycle next to the cycle in which the error signal is asserted. I had to. For example, even if a period is added to avoid the above problem in the circuit shown in Non-Patent Document 1, there remains a problem that the throughput of the entire system is reduced.

  In the circuit shown in Non-Patent Document 1, when a certain path from one register output to a register input is shorter than the enable period of the latch circuit (High period of the clock signal clk), the event is an event that passes through the critical path. In some cases, it is not possible to distinguish whether the path is reflected in the result of the next cycle, resulting in an erroneous determination.

  Furthermore, since the circuit shown in Patent Document 1 retains the state immediately before (one cycle before), it sometimes fails to correctly detect a malfunction due to a setup violation. Further, the circuit shown in Patent Document 1 has a problem that the circuit scale becomes large due to the configuration. In Non-Patent Document 1 and Patent Document 1, there is also a problem that it cannot be applied to a product that should not generate an error because it is a response after an error has occurred due to a setup violation.

  In Patent Document 2, when a setup violation occurs, the normal logic cannot be detected, and the setup violation state cannot be recovered.

  Therefore, an object of the present invention is to provide a semiconductor device that can recognize a circuit malfunction (setup violation) during actual operation without reducing the throughput of the entire system. Another object of the present invention is to provide a semiconductor device that can increase the reliability of a product by combining with a recovery function.

  According to another aspect of the present invention, there is provided a first register that takes in data from a logic circuit at a predetermined timing of a clock signal, a delay unit that delays the clock signal, and a logic circuit at a predetermined timing of the clock signal that has passed through the delay unit. A second register that is logically equivalent to the first register, and a first comparator that compares the output of the first register with the output of the second register and outputs a first error signal.

  In the semiconductor device according to the present invention, the first register, the second register that captures data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay unit, the output of the first register, and the output of the second register Since the first comparator for comparison is provided, it becomes possible to recognize a circuit malfunction (setup violation) during actual operation, and the reliability of the product can be improved by combining with the recovery function.

  First, before describing the semiconductor device of the present invention, the configuration and driving of a Razor circuit disclosed in Non-Patent Document 1 will be described. FIG. 1 shows a circuit diagram of the Razor circuit, and FIG. 2 shows a timing chart of the Razor circuit.

  In FIG. 1, a flip-flop circuit 101 that captures data in synchronization with the rising edge of the clock signal clk, a latch circuit 102 that captures data during the high period of the clock signal clk, an output Q1 of the flip-flop circuit 101, and a latch circuit The comparator 103 is configured to compare with the output Q2 of 102, and the selector circuit 104 switches between the output D1 (data) of the logic stage L1 and the output Q2 of the latch circuit 102 according to the result of the comparator 103. In the circuit shown in FIG. 1, the latch circuit 102 opens in synchronization with the timing when the flip-flop circuit 101 takes in data from the output S1 of the selector circuit 104, and the clock signal clk takes in data during the High period. In the circuit shown in FIG. 1, using the time difference between the flip-flop circuit 101 and the latch circuit 102, data arriving from the rising edge of the clock signal clk to the High period of the clock signal clk is detected as a malfunction (setup violation). ing.

  However, the malfunction detection performed by the Razor circuit has the following problems. First, in the timing chart for three periods shown in FIG. 2, only the second period is not in time and a setup violation occurs, and the data arrives normally in the other periods (first and third periods). First, focusing on the second period, the flip-flop circuit 101 captures “1” because the arrival of data changing from “1” to “0” is not in time at the rising timing of the clock signal clk. On the other hand, the latch circuit 102 captures “0” because the clock signal clk captures data in the High period. For this reason, the Razor circuit asserts an error signal as intended.

  However, paying attention to the third period, since the data that changes from “0” to “1” has arrived at the rising timing of the clock signal clk, a setup violation does not occur. However, the error signal asserted in the second period is not negated even in the third period. This is because the error signal in the second cycle is not negated at the rising timing of the clock signal clk in the third cycle, but the error signal in the second cycle is not negated. This is because the output Q2 is taken in.

  As a result, when the error signal is negated and the path from the output D1 of the logic stage L1 becomes active (upward arrow in FIG. 2), the flip-flop circuit 101 captures “0” latched in the latch circuit 102. Therefore, only the latch circuit 102 that becomes active captures data that changes from “0” to “1” (downward arrow in FIG. 2). Therefore, in the comparator 103, the output Q1 of the flip-flop circuit 101 and the output Q2 of the latch circuit 102 do not match, and an error signal is asserted even though no setup violation has occurred.

  Conventionally, in order to avoid the above problem, when an error occurs, the output Q1 is fetched after stalling for one cycle and negating the error signal. Therefore, the throughput of the entire system has been reduced.

  In the Razor circuit shown in FIG. 1, the change timing of input data is monitored. However, it is not only the critical path that generates the output D1 of the logic stage L1, but all the inputs of the logic cone. In FIG. 3, the critical path is a path from the start point P1 to the output D1 of the logic stage L1 as an end point. The logic cone is logic composed of one output and multiple inputs. If the broken line in FIG. 3 is defined as a cell, the output D1 of the logic stage L1 is the same logic cone as P1 and P2.

  Here, if one path in the logic cone is a path from the start point P2 of FIG. 3 to the output D1 of the logic stage L1 of the end point, for example, the data passing through the path is the enable period of the latch circuit 102. It may be shorter than (High period of the clock signal clk). In such a case, the Razor circuit shown in FIG. 3 determines whether the data passes through the critical path, or reflects the path reflected in the result of the next cycle (from P2 through the logic stage L1 in synchronization with the rise of the clock signal clk). Thus, it cannot be distinguished whether the path is via a path that reaches the latch circuit 102). Therefore, the Razor circuit shown in FIG. 3 makes an erroneous determination based on the path data reflected in the result of the next period.

  Next, a setup violation is defined. FIG. 4 shows a path from the logic stage L1 to the logic stage L2. In FIG. 4, the propagation time of the clock signal clk from the input point of the clock signal clk to the clock pin of the register R0 is TdR0 (clk), and the propagation time of the data from the clock pin of the register R0 to the output pin is TdR0 (clk−Q ). In FIG. 4, the propagation time of data from the output pin to the data pin of the register R1 via the logic stage L1 is TdL0, and the propagation time of the clock signal clk from the input point of the clock signal clk to the clock pin of the register R1. Is TdR1 (clk). Further, in FIG. 4, the setup timing check value of the register R1 is TsR1, and the cycle of the clock signal clk is Tp.

  In the case of setting as shown in FIG. 4, a setup violation occurs when the relationship of TdR0 (clk) + TdR0 (clk−Q) + TdL0 + TsR1> Tp + TdR1 (clk) is established.

  In the present invention, TdR0 (clk), TdL0, TsR1, and TdR1 (clk) in the above formulas are set up using a delay difference between a register that is devised in terms of the circuit in an embodiment described later and an actual operation register. Violations are detected dynamically.

(Embodiment 1)
FIG. 5 shows a circuit diagram of the semiconductor device according to the present embodiment. In FIG. 5, a register R2 having a margin (Positive Slack) is provided for the register R1 that is an actual operation register by the amount of insertion of the buffer chain B2 that is a delay means in the clock line. Then, the output D1 (data) of the logic stage L1 is input to the register R1. A register R0 is connected to the preceding stage of the logic stage L1. On the other hand, the output Q1 of the register R1 is input to the next logic stage L2 and also to the comparator 1.

  The comparator 1 compares the output Q1 of the register R1 and the output Q2 of the register R2, and outputs an error signal when they do not match. Therefore, the circuit shown in FIG. 5 can dynamically detect the setup violation of the register R1 by the delay of the buffer chain B2 inserted in the clock line. In the circuit shown in FIG. 5, the selection circuit 2 is provided to adjust the delay amount of the buffer chain B2. The selection circuit 2 is driven based on a selection signal Sel input from the outside.

  The circuit shown in FIG. 5 is intended for timing critical registers (critical path endpoints) in the synchronous design unit, and can therefore be applied to all digital design fields such as SOC (System On a Chip) and microcomputers. .

  Specifically, an application example such as the block diagram shown in FIG. 6 can be considered. In FIG. 6, a digital circuit 10 (semiconductor circuit) to which the circuit shown in FIG. 5 is applied, a clock generator 11 that supplies a clock signal clk to the digital circuit 10, and a regulator 12 that supplies a voltage to the digital circuit 10 are provided. I have. Further, FIG. 6 includes a control circuit 13 that controls the clock generator 11 and the regulator 12 based on an error signal from the digital circuit 10, and a memory 14 that the digital circuit 10 appropriately refers to. Note that the control circuit 13 also includes error rate calculation processing. In FIG. 6, the error signal to the control circuit 13 is asserted, so that the control circuit 13 controls the clock generator 11 and the regulator 12 to realize low power consumption.

  Next, in the circuit shown in FIG. 5, the path from the register R0 to the register R1 via the logic stage L1 is a critical path. Then, the output Q1 of the register R1 is propagated to the next logic stage L2. In the circuit shown in FIG. 5, the register R2 in which the setup violation condition is relaxed is provided by inserting the buffer chain B2 into the clock line, and the result comparison with the register R1 is performed by the comparator 1.

  Next, driving of the circuit shown in FIG. 5 will be described with reference to the time chart of FIG. In FIG. 7, the signal at the clock pin of the register R1 is the clock signal C1, the signal at the data input pin of the register R1 is the output D1, and the signal at the data output pin of the register R1 is the output Q1. Further, in FIG. 7, the signal at the clock pin of the register R2 is the clock signal C2, the signal at the data input pin of the register R2 is the output D2, and the signal at the data output pin of the register R2 is the output Q2. The clock signal C2 propagates with a delay by the amount of the buffer chain B2 inserted with respect to the clock signal C1.

  First, in the first period, the transition of the output D1 / D2 from “0” to “1” (hereinafter also referred to as a rise event) is performed before the rising of each clock signal C1 / C2. Therefore, the register R1 and the register R2 can normally capture the logic “1”. Note that the timing at which the register R1 and the register R2 take in logic “1” slightly shifts due to the delay difference between the clock signal C1 and the clock signal C2, and therefore the error signal of the comparator 1 temporarily becomes “1”. This temporary hazard can be deleted by the next process.

  Next, in the second period, the transition of the output D1 / D2 from “1” to “0” (hereinafter also referred to as “fall event”) is performed before the rising of each clock signal C1 / C2. Therefore, the register R1 and the register R2 can normally capture logic “0”.

  Next, in the third period, the rise event of the output D1 / D2 is performed before the rising of each clock signal C1 / C2. Therefore, the register R1 and the register R2 can normally capture the logic “1”.

  Next, in the fourth period, the fall event of the output D1 / D2 is performed after the clock signal C1 rises and before the clock signal C2 rises. That is, the arrival of data in the register R1 is not in time for the rise of the clock signal C1. Therefore, the output Q1 of the register R1 takes in “1” instead of “0”, and a malfunction due to a setup violation occurs. As a result, in the circuit shown in FIG. 5, the output Q1 of the register R1 and the output Q2 of the register R2 are different and the output of the comparator 1 is “1”, so that a malfunction can be detected.

  Therefore, in the semiconductor device according to the present embodiment, by monitoring the error signal and performing system control, it is possible to detect a malfunction of the register R1 that is the target of the actual operation and to count the “1” period of the error signal. This makes it possible to calculate the error rate.

  Further, since the delay amount of the buffer chain B2 inserted into the clock line can be controlled by the selection signal Sel as shown in FIG. 5, it can be tuned so as not to cause a hold error for the register R2. . By providing a mechanism capable of adjusting the delay amount, it is possible to prevent malfunction due to insufficient hold margin.

  In addition, by making the inside of the frame surrounding the registers R1 and R2, the buffer chain B2, the comparator 1 and the selection circuit 2 shown in FIG. 5 into cells, it is easy to design the SOC and microcomputer without degrading the system performance. Can be incorporated.

  In this embodiment, the buffer chain B2 is provided as the delay means. However, the present invention is not limited to this, and without providing the buffer chain B2, the transistor size and circuit topology of the register R2 can be changed. The circuit topology may be changed. Thereby, the register R2 can obtain a timing margin by delaying the clock signal clk with respect to the register R1, and conversely, the timing can be tightened by advancing the clock signal clk with respect to the register R1. Become.

(Embodiment 2)
FIG. 8 shows a circuit diagram of the semiconductor device according to the present embodiment. The circuit shown in FIG. 8 is provided with a register R2 having a timing (Positive Slack) as much as the insertion of the buffer B2 as a delay means in the clock line with respect to the register R1 as an actual operation register. Then, the output D1 (data) of the logic stage L1 is input to the register R1. A register R0 is connected to the preceding stage of the logic stage L1. On the other hand, the output Q1 of the register R1 is input to the next logic stage L2 and also to the comparator 1.

  The comparator 1 compares the output Q1 of the register R1 with the output Q2 of the register R2, and outputs a first error signal. Therefore, the circuit shown in FIG. 8 can dynamically detect the setup violation of the register R1 by the delay of the buffer B2 inserted in the clock line.

  Further, in the circuit shown in FIG. 8, the clock signal clk before the buffer B1 in the clock tree and after the buffer B0 is used to make the timing stricter than the register R1 by the delay of the buffer B1 (Negative Slack). It has. The comparator 3 compares the output Q1 of the register R1 with the output Q3 of the register R3, and outputs a second error signal. Therefore, the circuit shown in FIG. 8 can dynamically detect the setup violation of the register R1 by the delay of the buffer B1 inserted in the clock line.

  Here, in the operation of the actual circuit, necessary data passes through the register R1, and the register R3 is merely used as a monitor. Therefore, the malfunction of the register R3 does not affect the actual operation. Therefore, in the semiconductor device according to the present embodiment, it is possible to recognize the critical point from the operation limit value by controlling the voltage and the frequency using the register R3, and the voltage and the frequency can be detected without causing the actual circuit to malfunction. Can recognize the lower frequency limit.

  Next, driving of the circuit shown in FIG. 8 will be described with reference to the time chart of FIG. In FIG. 9, the signal at the clock pin of the register R1 is the clock signal C1, the signal at the data input pin of the register R1 is the output D1, and the signal at the data output pin of the register R1 is the output Q1. Further, in FIG. 9, the signal at the clock pin of the register R2 is the clock signal C2, the signal at the data input pin of the register R2 is the output D2, and the signal at the data output pin of the register R2 is the output Q2. In FIG. 9, the signal at the clock pin of the register R3 is the clock signal C3, the signal at the data input pin of the register R3 is the output D3, and the signal at the data output pin of the register R3 is the output Q3.

  The clock signal C2 is delayed by the amount of the buffer B2 inserted with respect to the clock signal C1, and the clock signal C1 is propagated with a delay of the amount of the buffer B1 inserted with respect to the clock signal C3. The output of the comparator 1 that compares the output Q1 and the output Q2 is output E1, and the output of the comparator 3 that compares the output Q1 and output Q3 is the output E2. The output of the register 4 that captures the output E1 at the timing of the clock signal C1 is a first error signal, and the output of the register 5 that captures the output E2 at the timing of the clock signal C1 is a second error signal.

  First, in the first period, the rise event of the outputs D1 / D2 / D3 is performed before the rising of each clock signal C1 / C2 / C3. Therefore, the register R1, the register R2, and the register R3 can normally capture the logic “1”.

  Next, in the second period, a fall event of the outputs D1 / D2 / D3 is performed after the rising of the clock signal C3 and before the rising of the clock signals C1 and C2. That is, the arrival of data in the register R3 is not in time for the rise of the clock signal C3. For this reason, the output Q3 of the register R3 takes in "1" instead of "0", resulting in a malfunction due to a setup violation. As a result, in the circuit shown in FIG. 8, the output Q1 of the register R1 is different from the output Q3 of the register R3, the output E2 of the comparator 3 is “1”, and a malfunction is detected. The interval is “1”.

  Next, in the third period, the rise event of the output D1 / D2 / D3 is performed before the rising of each clock signal C1 / C2 / C3. Therefore, the register R1, the register R2, and the register R3 can normally capture the logic “1”. Also, the output E2 asserted in the second cycle is normally negated.

  Next, in the fourth period, a fall event of the outputs D1 / D2 / D3 is performed after the rising of the clock signals C1 and C3 and before the rising of the clock signal C2. That is, the arrival of data in the registers R1 and R3 is not in time for the rise of the clock signals C1 and C3. For this reason, the output Q1 of the register R1 and the output Q3 of the register R3 take in “1” instead of “0”, and a malfunction occurs due to a setup violation. As a result, in the circuit shown in FIG. 8, the output Q1 of the register R1 is different from the output Q2 of the register R2, the output E1 of the comparator 1 is “1”, and a malfunction is detected. The interval is “1”.

  Therefore, in the semiconductor device according to the present embodiment, the second error signal is monitored, and system control is performed when the second error signal becomes “1”, thereby causing no malfunction in the register R1 that is the target of actual operation. A malfunction can be detected. Further, in the semiconductor device according to the present embodiment, the error rate can be calculated by counting the “1” period of the first error signal. In the circuit shown in FIG. 8, a configuration in which the selection amount 2 shown in FIG. 5 is provided for the buffers B0, B1, and B2 to adjust the delay amount can be adopted.

(Embodiment 3)
FIG. 10 shows a circuit diagram of the semiconductor device according to the present embodiment. The circuit shown in FIG. 10 is basically the same as the circuit shown in FIG. 5 except that an output selection circuit 6 is added. The output selection circuit 6 outputs the output Q1 of the register R1 to the logic stage L2 when the error signal output from the comparator 1 is “0”, and outputs the output Q2 of the register R2 when the error signal is “1”. Is controlled to be output to the logic stage L2.

  Next, driving of the circuit shown in FIG. 10 will be described with reference to the time chart of FIG. In FIG. 11, the signal at the clock pin of the register R1 is the clock signal C1, the signal at the data input pin of the register R1 is the output D1, and the signal at the data output pin of the register R1 is the output Q1. Further, in FIG. 11, the signal at the clock pin of the register R2 is the clock signal C2, the signal at the data input pin of the register R2 is the output D2, and the signal at the data output pin of the register R2 is the output Q2. The clock signal C2 propagates with a delay by the amount of the buffer B2 inserted with respect to the clock signal C1.

  First, in the first period, the rise event of the output D1 / D2 is performed before the rising of each clock signal C1 / C2. Therefore, the register R1 and the register R2 can normally capture the logic “1”. Note that the timing at which the register R1 and the register R2 take in logic “1” slightly shifts due to the delay difference between the clock signal C1 and the clock signal C2, and therefore the error signal of the comparator 1 temporarily becomes “1”. Along with this, the output (Output signal) to the logic stage L2 also becomes the value of the output Q2 fetched in the previous period during that period, but after that, it switches to the output to the output Q1 and operates normally.

  However, in order to complete this system path, in addition to the normal logic, the path via the clock pin (C2) of the register R2, the data output pin (Q2) of the register R2, the output selection circuit 6 and the logic stage L2. However, it is necessary to satisfy the setup of the next stage register.

  Next, in the second period, a fall event of the output D1 / D2 is performed after the rising of the clock signal C1 and before the rising of the clock signal C2. That is, the arrival of data in the register R1 is not in time for the rise of the clock signal C1. Therefore, the output Q1 of the register R1 takes in “1” instead of “0”, and a malfunction due to a setup violation occurs. However, in the register R2, since the arrival of the fall event of the output D2 is in time for the rise of the clock signal C2, the output Q2 of the register R2 can capture “0”.

  Here, due to the difference between the output Q1 of the register R1 and the output Q2 of the register R2, the error signal which is the output of the comparator 1 becomes “1”, and a malfunction can be detected. Since the output selection circuit 6 switches to the path for outputting the output Q2 to the logic stage L2 by the error signal, correct data can be propagated to the logic stage L2 without lowering the throughput.

  Next, in the third period, the rise event of the output D1 / D2 is performed before the rising of each clock signal C1 / C2. Therefore, the register R1 and the register R2 can normally capture the logic “1”. Also, the error signal asserted in the second cycle is also normally negated (logic “0”), and the output Q1 is output as the Output signal.

  Next, in the fourth period, the arrival of the fall event of the output D1 is not in time for the rise of the clock signal C1, as in the second period. Therefore, due to the difference between the output Q1 of the register R1 and the output Q2 of the register R2, the error signal that is the output of the comparator 1 becomes “1”, and a malfunction can be detected. The output signal is switched to a path for outputting the output Q2 to the logic stage L2 by the error signal, and correct data is propagated to the logic stage L2.

  As described above, the semiconductor device according to the present embodiment includes the output selection circuit 6 that outputs either the output Q1 of the register R1 or the output Q2 of the register R2 to the logic stage L2 based on the first error signal. Therefore, since recovery is possible during actual operation, it is not necessary to secure an operation margin unnecessarily, which can contribute to improvement in yield.

(Embodiment 4)
FIG. 12 shows a circuit diagram of the semiconductor device according to the present embodiment. The circuit shown in FIG. 12 is basically the same as the circuit shown in FIG. 5 except that a clock control circuit 7 that is controlled based on a change in the previous register is added. The clock control circuit 7 includes a logic circuit 71 that takes an exclusive OR (EOR) of the input to the register R0 and the output from the register R0, and the clock signal clk that has passed through the output G2 of the logic circuit 71 and the buffer B2. And a logic circuit 72 that takes a logical product (AND) of

  However, the clock signal clk supplied to the register R2 is delayed by the amount of the inserted buffer B2 compared to the clock signal supplied to the register R0. Therefore, in order to obtain an effective delay amount, it is necessary to make adjustments using techniques such as buffer cell insertion, wiring length adjustment, and wiring physical property adjustment. In the semiconductor device according to the present embodiment, the output Q1 of the register R1 and the output Q2 of the register R2 are not compared in all cycles, but are compared only when there is a change in the register R0. Low power consumption can be realized by suppressing the activity rate.

  Next, driving of the circuit shown in FIG. 12 will be described with reference to the time chart of FIG. In FIG. 13, the signal at the clock pin of the register R0 is the clock signal C0, the signal at the data input pin of the register R0 is the output D0, and the signal at the data output pin of the register R0 is the output Q0. In FIG. 13, the signal at the clock pin of the register R1 is the clock signal C1, the signal at the data input pin of the register R1 is the output D1, and the signal at the data output pin of the register R1 is the output Q1.

  Further, in FIG. 13, the signal at the clock pin of the register R2 is the clock signal C2, the signal at the data input pin of the register R2 is the output D2, and the signal at the data output pin of the register R2 is the output Q2. The clock signal C2 propagates with a delay by the amount of the buffer B2 inserted with respect to the clock signal C1.

  First, in the first cycle, the rise event of the output D1 / D2 is performed before each clock signal C1 / C2 rises. Therefore, the register R1 and the register R2 can normally capture the logic “1”. Note that the output G2 becomes “1” during a period in which the output D0 and the output Q0 are different, and the delay amount of the buffer B2 is adjusted so that the clock signal C2 rises and the register R2 can take in data during the period. Yes.

  Further, the timing at which the register R1 and the register R2 take in the logic “1” slightly shifts due to the delay difference between the clock signal C1 and the clock signal C2 by the buffer B2, so that the error signal of the comparator 1 temporarily becomes “1”. Become. However, after that, when the output Q2 normally captures “1”, the error signal returns to “0”.

  Next, in the second period, since there is no difference between the output D0 and the output Q0, that is, an event (data) for the register R0 does not occur, the clock signal C2 is not supplied to the register R2. Therefore, power consumption associated with activation of the register R2 can be reduced.

  Next, in the third period, the fall event of the output D1 in the register R1 is not in time for the rise of the clock signal C1, and therefore the register R1 cannot capture “0”. However, regarding the register R2, since the output D0 and the output Q0 are different, the output G2 becomes “1”, and the clock signal C2 delayed by the buffer B2 with respect to the clock signal C1 is input. Since the clock signal C2 rises with a delay corresponding to the buffer B2, the register R2 can normally capture the logic “0”. Therefore, the output (error signal) of the comparator 1 becomes “1” due to the difference in the result between the output Q1 of the register R1 and the output Q2 of the register R2, and a malfunction can be detected.

  Next, in the fourth period, as in the second period, since there is no difference between the output D0 and the output Q0, that is, no event (data) is generated for the register R0, the clock signal C2 is not supplied to the register R2. Therefore, power consumption associated with activation of the register R2 can be reduced.

  Next, in the fifth period, the rise event of the output D1 / D2 is performed before the rising of each clock signal C1 / C2. Therefore, the register R1 and the register R2 can normally capture the logic “1”. Note that the error signal asserted in the third cycle is also normally negated (logic “0”) in the cycle.

(Embodiment 5)
FIG. 14 shows a path from the logic stage L1 through the register R1 to the logic stage L2, and a path from the logic stage L1 ′ through the register R1 to the logic stage L2. In FIG. 14, the AND circuit 8 which is the final logic of the logic stage L1 and the logic stage L1 ′ is shared. That is, the logic stage L1 shown in the first to fourth embodiments is a circuit in which the logic stage L1 shown in FIG. 14 and the AND circuit 8 are combined (a portion surrounded by a broken line).

  In the semiconductor device according to the present embodiment, the final logic of the logic stage L1 and the logic stage L1 'is separated and configured using the configuration of FIG. FIG. 15 is a circuit diagram of the semiconductor device according to the present embodiment. In FIG. 15, it is assumed that a path from the register R0 to the register R1 via the logic stage L1 and the input pin A of the AND circuit 8 is a critical path. Data is propagated to the other input pin B of the AND circuit 8 from the other logic stage L1 '.

  Further, in the circuit shown in FIG. 15, a register R 1-1 is inserted before the input pin A of the AND circuit 9. As a result, the path from the register R0 to the register R1-1 has a timing margin corresponding to the AND circuit 8 with respect to the path from the register R0 to the register R1, which is the original critical path. Similarly, the path from the logic stage L1 'to the register R1-2 has a timing margin corresponding to the AND circuit 8 with respect to the path from the logic stage L1' to the register R1.

  In the circuit shown in FIG. 15, in order to realize the original logic for the register R1, an AND circuit 9 is inserted after the registers R1-1 and R1-2, and the result is captured by the register R2. Here, in the circuit shown in FIG. 15, the register R1-1, the register R1-2, and the AND circuit 9 constitute a logic generating unit that generates data with a margin in timing corresponding to the logic of the final stage. .

  Further, in the circuit shown in FIG. 15, by providing the register R1-1 and the register R1-2, the register R1 ′ is provided at the subsequent stage of the register R1 in order to synchronize with the register R2 with a delay of one cycle from the register R1. Provided. Therefore, as in the first embodiment, the setup violation of the register R1 can be determined by comparing the output of the register R1 'with the output of the register R2 by the comparator 1.

  Next, driving of the circuit shown in FIG. 15 will be described with reference to the time chart of FIG. In FIG. 16, a signal at the input pin A of the AND circuit 8 is an input 8A, and a signal at the input pin B of the AND circuit 8 is an input 8B. In FIG. 16, the clock signal is clk, the signal at the data input pin of the register R1 is output D1, and the signal at the data output pin of the register R1 is output Q1. In FIG. 16, the signal at the data output pin of the register R1-1 is output Q1-1, the signal at the data output pin of the register R1-2 is output Q1-2, and the signal at the data output pin of the register R1 ′. Is the output Q1 ', and the signal at the data output pin of the register R2 is the output Q2. In this embodiment, the input 8B is fixed to “1”. Further, since the output Q1 'is simply an in-phase transfer of the output Q1 shifted by one cycle, detailed description thereof will be omitted below.

  First, in the first period, since the input 8B is fixed to “1”, the rise event of the input 8A propagates to the output D1. Since the rise event of the output D1 is performed before the rise of each clock signal clk, the register R1 and the register R1-1 can normally capture the logic “1”.

  Next, in the second cycle, each of the register R1 ′ and the register R2 takes in “1” based on the results of the output Q1 and the output Q1-1 in the first cycle, and an error signal is obtained by comparing the output Q1 ′ with the output Q2. Becomes “0”. In the register R1, the rising of the clock signal clk is not in time for the fall event at the input 8A to propagate to the output D1. Therefore, register 1 cannot capture logic “0”. However, in the register R1-1, since the rising of the clock signal clk occurs after the fall event at the input 8A, the logic “0” can be normally captured.

  Next, in the third period, the values of the output Q1 'and the output Q2 do not match due to the results of the register R1 and the register R1-1 in the second period, and the error signal is "1", so that a malfunction can be detected. In the register R1, since the rise event at the input 8A propagates to the output D1 and the rise event of the clock signal clk is in time at the timing, both the register R1-1 and the register R1 normally capture the logic “1”. Can do.

  Next, in the fourth period, the same situation as in the second period occurs, and as a result, the error signal becomes “0”. In the fifth cycle, the same situation as in the third cycle occurs, and as a result, the error signal becomes “1”, and a malfunction is detected.

  In the present embodiment, the configuration in which only the final logic of the logic stage L1 is separated is shown as shown in FIG. 15, but the present invention is not limited to this, and a configuration in which a plurality of stages including the final logic are separated from the logic stage L1. But you can.

(Embodiment 6)
FIG. 17 shows a circuit diagram of the semiconductor device according to the present embodiment. In the circuit shown in FIG. 17, it is assumed that the path from the register R0 to the register R1 via the logic stage L1 is a critical path. In the circuit shown in FIG. 17, a pin for inputting a TestMode signal is provided, and the TestMode signal is controlled to take “1” only during a startup operation test and take “0” during a normal operation.

  Accordingly, in the circuit shown in FIG. 17, each logic gate in the critical path is set to “1” so that only the critical path is activated using the TestMode signal and the OR circuit 20 (which becomes an AND circuit depending on the circuit configuration). Fixed to “or” “0”. In the circuit shown in FIG. 17, the TestMode signal and the OR circuit 20 constitute a logic fixing means.

  Further, it is determined whether the activated critical path is inverted logic or non-inverted logic. When the critical path is not inverted, the inverter 21 is inserted into the output of the logic stage L1 to set the inverted logic. Then, the inverted logic is looped back to the register R0 during the operation test via the register 22. As a result, control is performed so that the register R1 can perform toggle output.

  In the circuit shown in FIG. 17, an inverter 23 is provided at the output of the register R2 so that the register R2 can perform toggle output. In the circuit shown in FIG. 17, by providing an input pin for the TestMode signal, the registers R0 and R2 can be set to the same initial value during an operation test by direct reset or scanning.

  Next, driving of the circuit shown in FIG. 17 will be described with reference to the time chart of FIG. In FIG. 18, the clock signal is clk, the signal at the data input pin of the register R1 is output D1, and the signal at the data output pin of the register R1 is output Q1. In FIG. 18, a signal obtained by inverting the output of the register R2 by the inverter 23 is used as the output Q2. In this embodiment, the TestMode signal is fixed to “1”, the TestMode signal is set to “0” after the operation test is completed, and the circuit shown in FIG. 17 is switched from the test mode to the normal operation mode.

  First, in the first cycle, the rise event at the output D1 is performed before the rise of the clock signal clk, so that the register R1 can normally capture the logic “1”. The register R2 captures the toggle logic “1” at the rising edge of the clock signal clk by initializing the output Q2 to “0”. For this reason, the values of the output Q1 and the output Q2 input to the comparator 1 match, and the output error signal is “0”.

  Next, in the second period, since the fall event at the output D1 is not in time for the rise of the clock signal clk, the register R1 cannot take in the logic “0”. On the other hand, the register R2 fetches logic “0” because it toggles regardless of the logic of the register R1. Therefore, in the circuit shown in FIG. 17, the logics of the register R1 and the register R2 do not match, and the error signal becomes “1” to detect a malfunction.

  Next, in the third cycle, the same situation as in the first cycle occurs, and as a result, the error signal becomes “0”. In the fourth period, the same situation as in the second period occurs, and as a result, the error signal becomes “1”, and a malfunction can be detected. Further, in the fifth cycle, a situation similar to that in the first cycle occurs, and as a result, the error signal becomes “0”.

(Embodiment 7)
FIG. 19 shows a circuit diagram of the semiconductor device according to the present embodiment. The circuit shown in FIG. 19 uses the configuration of FIG. 14 described in the fifth embodiment and separates the final logic (AND circuit 25) of the logic stage L1 and the logic stage L1 ′. In FIG. 19, it is assumed that the path from the register R0 to the register R1 via the logic stage L1 and the input pin A of the AND circuit 25 is a critical path. Then, an event (data) is propagated from the other logic stage L1 ′ to the other input pin B of the AND circuit 25. Note that the logic stage L1 shown in the first to fourth embodiments is a circuit in which the logic stage L1 shown in FIG. 19 and the AND circuit 25 are combined (a portion surrounded by a broken line).

  In the circuit shown in FIG. 19, a register R2 and a register R3 having the same circuit configuration as that of the circuit configuration realizing the logic cone of the register R1 are provided. Further, the register R2 has a function of activating only a part of the critical path (path passing through the input pin A of the AND circuit 25). This mechanism is a function for fixing a path passing through the input pin A of the AND circuit 26 using the data fixing Mode signal and the OR circuit 27. That is, in the circuit shown in FIG. 19, the data fixing Mode signal and the OR circuit 27 constitute a logic fixing means for activating the AND logic of the final stage that is a part of the critical path of the logic stage L1.

  Even if the signal is fixed, the register R2 can be used as a monitor for the register R1, which is an actual operation circuit, because the operating condition of the speed surface of the critical path is the same as that of the register R1. That is, the register R2 can be used to determine the setup violation of the register R1.

  On the other hand, the register R3 determines whether the logic L3 of the path activated in the register R2 (the logic indicated by the arrow in FIG. 19) is inverted or non-inverted. (If it is non-inverted, the inverter 28 is not inserted), and logical compression is used as an expected value. However, it is assumed that the determination of inversion / non-inversion logic and the accompanying insertion of the inverter 28 are recognized and set at the time of design.

  Thereby, the register R3 is advantageous in that the delay difference obtained by subtracting the inverter 28 from the logic L3 is compared with the register R2, and the setup violation of the registers R1 and R2 occurring within the range can be detected dynamically.

  Next, driving of the circuit shown in FIG. 19 will be described with reference to the time chart of FIG. In FIG. 20, a signal at the input pin A of the AND circuit 26 is an input 26A, and a signal at the input pin B of the AND circuit 26 is an input 26B. In FIG. 16, the clock signal is clk, the signal at the data input pin of the register R2 is output D2, and the signal at the data output pin of the register R2 is output Q2. In FIG. 16, the signal at the data input pin of the register R3 is output D3, and the signal at the data output pin of the register R3 is output Q3. In the present embodiment, the input 26B is fixed to “1” by the data fixing Mode signal and the OR circuit 27. Further, as described above, the event (data) propagates to the output D3 at a timing faster than that of the output D2. In the present embodiment, the AND circuit 26 has normal rotation logic, and the inverter 28 is not inserted in the previous stage of the register R3.

  First, in the first period, a rise event at the input 26A is propagated to the output D2, and is performed before the rising of the clock signal clk. Therefore, both the register R2 and the register R3 can normally capture the logic “1”. As a result, in the comparator 1, the output Q2 of the register R2 matches the output Q3 of the register R3, and the error signal becomes “1”.

  Next, in the second period, the fall event at the input 26A propagates to the output D2, and the rising of the clock signal clk is not in time for that timing. Therefore, the register R2 cannot capture logic “0”. On the other hand, since the clock signal clk rises after the fall event of the output D3, the register R3 can normally capture logic “0”. As a result, in the comparator 1, the output Q2 of the register R2 and the output Q3 of the register R3 do not coincide with each other, the error signal becomes “1”, and a malfunction is detected.

  Next, in the third cycle, the same situation as in the first cycle occurs, and as a result, the error signal becomes “0”. In the fourth period, the same situation as in the second period occurs, and as a result, the error signal becomes “1”. Further, in the fifth cycle, a situation similar to that in the first cycle occurs, and as a result, the error signal becomes “0”.

  In this embodiment, as shown in FIG. 19, only the final logic of the logic stage L1 is separated. However, the present invention is not limited to this, and a plurality of stages including the final logic are separated from the logic stage L1. But you can.

(Embodiment 8)
FIG. 21 shows a circuit diagram of the semiconductor device according to the present embodiment. In the circuit shown in FIG. 21, a path from the register R0 via the logic stage L1 to the register R1 is a critical path, and the output Q1 of the register R1 is propagated to the next stage logic (logic stage L2). In the circuit shown in FIG. 21, the clock signal C1 supplied to the register R1 is not a clock signal clk supplied directly from the outside, but is a signal obtained by ORing the enable signal in the AND circuit 30. Yes.

  In the circuit shown in FIG. 21, a register R2 in which the setup violation condition is relaxed by inserting a buffer B2 in the clock line is provided, and an output result comparison with the register R1 is performed by the comparator 1. Further, in the circuit shown in FIG. 21, when the enable signal is “0”, the output Q2 of the register R2 is fed back using the selection circuit 31 so that the data from the register R0 is not taken in, and the enable signal is “1”. In the case, the output D1 is captured. In the circuit shown in FIG. 21, the selection circuit 31 constitutes a logic selection unit.

  Next, driving of the circuit shown in FIG. 21 will be described with reference to the time chart of FIG. In FIG. 22, the signal at the clock pin of the register R1 is the clock signal C1, the signal at the data input pin of the register R1 is the output D1, and the signal at the data output pin of the register R1 is the output Q1. In FIG. 22, the signal at the clock pin of the register R2 is the clock signal C2, the signal at the data input pin of the register R2 is the output D2, and the signal at the data output pin of the register R2 is the output Q2. The clock signal C2 is delayed from the clock signal C1 by the amount of the inserted buffer B2.

  First, since the enable signal is “1” in the first period, both the register R1 and the register R2 take in data from the outputs D1 and D2 when the clock signals C1 and C2 rise. However, in the first cycle, the rise event at the output D1 is not in time for the rise of the clock signal C1, so that the register R1 cannot capture the logic “1”. On the other hand, since the rise of the clock signal C2 occurs after the rise event of the output D1 occurs, the register R2 can normally capture the logic “1”. Therefore, in the comparator 1, since the values of the output Q1 and the output Q2 do not match, the error signal becomes “1” and a malfunction is detected.

  Next, since the enable signal remains “1” in the second period, both the register R1 and the register R2 take in data from the outputs D1 and D2 when the clock signals C1 and C2 rise. That is, since the rise of the clock signal C1 occurs after the rise event of the output D1 occurs, the register R1 can normally capture the logic “0”. Further, since the rise of the clock signal C2 occurs after the rise event of the output D2, the register R2 can normally capture the logic “0”. Accordingly, in the comparator 1, the values of the output Q1 and the output Q2 match, and the error signal becomes “0”.

  Next, in the third period, since the enable signal becomes “0”, the clock signal C1 does not rise with respect to the register R1. Therefore, the register R1 holds the value of the output Q1 of the previous cycle as it is. In FIG. 22, since the rising edge of the clock signal C1 does not occur, the timing of taking in the output Q1 in the third cycle (denoted as X in the drawing) is not shown.

  On the other hand, in the register R2, although the rise of the clock signal C2 occurs, the output of the selection circuit 31 is switched by the enable signal to form a feedback loop of the output Q2, and “0” of the previous period is taken in. Accordingly, in the comparator 1, the values of the output Q1 and the output Q2 match, and the error signal becomes “0”.

  Next, since the enable signal remains “1” in the fourth period, the value of the previous period is held as it is in the third period. Accordingly, in the comparator 1, the values of the output Q1 and the output Q2 match, and the error signal becomes “0”.

  Next, since the enable signal is “1” in the fifth cycle, both the register R1 and the register R2 take in data from the outputs D1 and D2 when the clock signals C1 and C2 rise. Accordingly, in the comparator 1, the values of the output Q1 and the output Q2 match, and the error signal becomes “0”. Note that the timing at which the register R1 and the register R2 take in logic “1” slightly shifts due to the delay difference between the clock signal C1 and the clock signal C2, and therefore the error signal of the comparator 1 temporarily becomes “1”.

  The timing chart of FIG. 22 shows an example of detecting a setup violation of the data signal in the circuit shown in FIG. 21, but the timing chart of FIG. 23 shows an example of detecting the setup violation of the enable signal in the circuit shown in FIG. explain.

  First, in the first cycle of FIG. 23, the rise event of the enable signal is delayed from the rising edge of the clock signal clk, but the delay is smaller than the delay of the buffer B2. Therefore, the clock signal C1 lacks a pulse due to the delay of the enable signal. However, since the clock signal C1 rises after the rise event of the output D1, the register R1 can normally capture logic “1”. Further, since the rise of the clock signal C2 occurs after the rise event of the enable signal occurs, the register R2 can normally capture the logic “1”. Accordingly, in the comparator 1, the values of the output Q1 and the output Q2 match, and the error signal becomes “0”. Note that the timing at which the register R1 and the register R2 take in logic “1” slightly shifts due to the delay difference between the clock signal C1 and the clock signal C2, and therefore the error signal of the comparator 1 temporarily becomes “1”.

  Next, in the second cycle of FIG. 23, the enable signal falls to “0” and the clock signal C1 does not enter the register R1, so the register R1 holds the state “1” of the previous cycle. On the other hand, since the clock signal C2 delayed by the inserted buffer B2 is input to the register R2, and the selection circuit 31 selects a path for taking in the output Q2 instead of the output D1, as a result, the state “1” of the previous cycle is changed. Will hold. Accordingly, in the comparator 1, the values of the output Q1 and the output Q2 match, and the error signal becomes “0”.

  Next, the third period in FIG. 23 is a case where the rise event of the enable signal is delayed from the rise of the clock signal clk, and the delay is larger than the delay of the buffer B2. In this case, the clock signal C1 lacks a pulse due to the delay of the enable signal. However, since the clock signal C1 rises after the fall event of the output D1, the register R1 can normally capture logic “0”. However, since the rise event of the enable signal is not in time for the rise of the clock signal C2, the register R2 selects the path for taking in the output Q2 instead of the data from the output D1, and holds the logic “1”. Therefore, in the comparator 1, the values of the output Q1 and the output Q2 do not match, and the error signal becomes “1”.

  Next, in the fourth period of FIG. 23, as in the second period, the value of the previous period is held as it is, the output Q1 and the output Q2 remain inconsistent, and the error signal remains “1”. Further, in the fifth cycle of FIG. 23, the rise event of the enable signal is earlier than the rise of the clock signal clk, so that the rise of the clock signal clk and the clock signal C1 coincide. Since the clock signal C1 and the clock signal C2 rise after the rise event of the output D1, the register R1 and the register R2 can normally capture the logic “1”. Accordingly, in the comparator 1, the values of the output Q1 and the output Q2 match, and the error signal becomes “0”.

  As described above, the semiconductor device according to the present embodiment can detect not only the setup violation of the data signal but also the setup violation of the enable signal.

(Embodiment 9)
FIG. 24 shows a circuit diagram of the semiconductor device according to the present embodiment. In the circuit shown in FIG. 24, a plurality of circuits shown in FIG. 5 are provided, and outputs Ea to Ex of the comparators 1 a to 1 x of each circuit are input to the OR circuit 40. In the circuit shown in FIG. 24, the output from the OR circuit 40 is input to the control circuit 13 shown in FIG. 6 as an error signal, and the clock signal clk and voltage supplied to each circuit are controlled. In the circuit shown in FIG. 24, an OR circuit 40 that performs an OR operation on the outputs Ea to Ex constitutes an error signal generation circuit.

  That is, the circuit shown in FIG. 24 can detect the presence or absence of a setup violation for a plurality of paths from the logic stage L1 to the logic stage L2. In addition, the present embodiment is not limited to the path from the logic stage L1 to the logic stage L2. By applying the circuit configuration shown in FIG. 5 to various paths, it is possible to check whether there is a setup violation that occurs in each path. Can be detected.

  As described above, since the semiconductor device according to the present embodiment can detect setup violations of a plurality of paths, the clock signal clk and the voltage are not optimized based only on a certain path (for example, a critical path). As a result, the entire circuit can be driven optimally. In other words, in this embodiment, the present invention can be applied not only to a critical path but also to a register of a delay path within a specific range, and normal operation can be confirmed on all the paths, thereby further reducing power consumption.

(Embodiment 10)
FIG. 25 shows a circuit diagram of the semiconductor device according to the present embodiment. In the circuit shown in FIG. 25, the clock signal clk before the buffer B1 in the clock tree and after the buffer B0 is used to tighten the timing by the delay of the buffer B1 with respect to the register R1 that is the actual operation register (Negative Slack). ) A register R3 is provided. The comparator 3 compares the output Q1 of the register R1 with the output Q3 of the register R3 and outputs an error signal. Therefore, the circuit shown in FIG. 25 can dynamically detect a hold violation from the register R0 to the register R1 by the delay of the buffer B1 inserted in the clock line.

  Next, driving of the circuit shown in FIG. 25 will be described with reference to the time chart of FIG. First, in the circuit shown in FIG. 25, the path from the register R0 to the register R1 has almost no delay and is a critical path for the hold operation. Of course, even if simulation is performed in the circuit shown in FIG. 25, a hold timing error does not occur. Further, a logic state may be interposed between paths from the register R0 to the register R1.

  In FIG. 26, the signal at the clock pin of the register R1 is the clock signal C1, the signal at the data input pin of the register R1 is the output D1, and the signal at the data output pin of the register R1 is the output Q1. Further, in FIG. 26, the signal at the clock pin of the register R3 is the clock signal C3, the signal at the data input pin of the register R3 is the output D3, and the signal at the data output pin of the register R3 is the output Q3.

  The clock signal C1 propagates with a delay by the amount of the buffer B1 inserted with respect to the clock signal C3. The output of the comparator 3 that compares the output Q1 and the output Q3 is an error signal.

  First, in the first period, the rise event of the output D1 / D3 from the output Q0 of the register R0 is performed after the rise of each clock signal C1 / C3. Therefore, the register R1 and the register R3 can normally capture logic “0”. That is, the register R1 and the register R3 do not capture the next logic “1”.

  Next, in the second cycle, the fall event of the output D1 / D3 arrives earlier than the rising edge of the clock signal C1 due to reasons such as variations in path delay, and the register R1 is not the previous logic “1”. The next logic “0” of the output Q0 output at the same cycle clock is fetched. That is, the register R1 malfunctions due to a hold timing error. However, since the clock signal C3 rises earlier than the clock signal C1 by the buffer B1, the register R3 can normally capture the previous logic “1”. Therefore, the output Q1 of the register R1 and the output Q3 of the register R3 are different, and the error signal of the comparator 3 is “1”, and a malfunction is detected.

  Next, in the third period, the rise event of the output D1 / D3 is performed after the rise of each clock signal C1 / C3. Therefore, the register R1 and the register R3 can normally capture logic “0”. That is, the register R1 and the register R3 do not capture the next logic “1”. Also, the error signal that was asserted in the second cycle is normally negated.

  Next, in the fourth period, as in the second period, the fall event of the output D1 / D3 arrives earlier than the rising edge of the clock signal C1, and the register R1 is not the previous logic “1” but the same cycle clock. The next logic “0” of the output Q0 output in step S3 is taken in. That is, the register R1 malfunctions due to a hold timing error. However, since the clock signal C3 rises earlier than the clock signal C1 by the buffer B1, the register R3 can normally capture the previous logic “1”. Therefore, the output Q1 of the register R1 and the output Q3 of the register R3 are different, and the error signal of the comparator 3 is “1”, and a malfunction is detected.

  Next, in the fifth cycle, as in the third cycle, the rise event of the output D1 / D3 is performed after the rising of each clock signal C1 / C3. Therefore, the register R1 and the register R3 can normally capture logic “0”. That is, the register R1 and the register R3 do not capture the next logic “1”. Also, the error signal that was asserted in the fourth cycle is normally negated.

  Therefore, in the semiconductor device according to the present embodiment, the register is logically equivalent to the register R1, but the clock line has a strict timing with respect to the register R1 by delay control (buffer cell insertion, wiring length adjustment, wiring physical property adjustment). Since R3 is provided, the hold violation of the register R1 can be dynamically detected by comparing the outputs Q1 and Q3 with each other.

It is a circuit diagram of a circuit which is a premise of the present invention. It is a timing chart of the circuit used as the premise of this invention. It is a circuit diagram of a circuit which is a premise of the present invention. It is a figure explaining a setup violation. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. 4 is a timing chart of the semiconductor device according to the first embodiment of the present invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 2 of this invention. It is a timing chart of the semiconductor device concerning Embodiment 2 of the present invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 3 of this invention. 6 is a timing chart of the semiconductor device according to the third embodiment of the present invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 4 of this invention. 6 is a timing chart of the semiconductor device according to the fourth embodiment of the present invention. It is a figure for demonstrating the semiconductor device which concerns on Embodiment 5 of this invention. FIG. 10 is a circuit diagram of a semiconductor device according to a fifth embodiment of the present invention. 10 is a timing chart of the semiconductor device according to the fifth embodiment of the present invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 6 of this invention. 10 is a timing chart of the semiconductor device according to the sixth embodiment of the present invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 7 of this invention. It is a timing chart of the semiconductor device concerning Embodiment 7 of the present invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 8 of this invention. It is a timing chart of the semiconductor device which concerns on Embodiment 8 of this invention. It is a timing chart of the semiconductor device which concerns on Embodiment 8 of this invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 9 of this invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 10 of this invention. It is a timing chart of the semiconductor device which concerns on Embodiment 10 of this invention.

Explanation of symbols

1, 3 Comparator, 2, 31 selection circuit, 4, 5, 22 register, 6 output selection circuit, 7 clock control circuit, 8, 9, 25, 30 AND circuit, 10 digital circuit, 11 clock generator, 12 regulator , 13 control circuit, 14 memory, 20, 26, 40 OR circuit, 21, 23, 28 inverter, 71, 72 logic circuit, 101 lip-flop circuit, 102 latch circuit, 103 comparator, 104 selector circuit.

Claims (14)

A first register for fetching data from the logic circuit at a predetermined timing of the clock signal;
Delay means for delaying the clock signal;
A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay means;
A semiconductor device comprising: a first comparator that compares the output of the first register with the output of the second register and outputs a first error signal. The semiconductor device according to claim 1,
A third register that is logically equivalent to the first register and that captures data from the logic circuit at an early timing relative to the clock signal;
The semiconductor device further comprising: a second comparator that compares the output of the first register and the output of the third register and outputs a second error signal. The semiconductor device according to claim 1 or 2, wherein
A delay amount adjusting circuit for adjusting a delay amount of the delay means;
And a control circuit for controlling the delay amount adjusting circuit based on the first error signal. The semiconductor device according to claim 1 or 2, wherein
The delay unit sets a delay amount by changing a transistor size or a circuit topology of the second register with respect to the first register. A semiconductor device according to any one of claims 1 to 4, wherein
A semiconductor device, further comprising: an output selection circuit that outputs either the output of the first register or the output of the second register to a logic circuit in a next stage based on the first error signal. A semiconductor device according to any one of claims 1 to 5,
A semiconductor device, further comprising: a clock control circuit that inputs the clock signal that has passed through the delay means to the second register only when a previous register input to the logic circuit changes. A first register for fetching data from the logic circuit at a predetermined timing of the clock signal;
Logic generation means for generating data having a margin in timing for at least the last stage of the logic circuit;
A second register that is logically equivalent to the first register and captures the output of the logic generation means at a predetermined timing of the clock signal;
A period adjustment register disposed downstream of the first register and configured to adjust a timing shift by the logic generation unit;
A semiconductor device comprising: a comparator that compares an output of the cycle adjustment register with an output of the second register and outputs an error signal. A first register for fetching data from the logic circuit at a predetermined timing of the clock signal;
A second register that is logically equivalent to the first register and that captures data from the logic circuit at a predetermined timing of the clock signal;
A comparator that compares the output of the first register with the output of the second register and outputs an error signal;
A semiconductor device comprising: logic fixing means for fixing logic of the logic circuit and activating a predetermined path. A first register for fetching data from the logic circuit at a predetermined timing of the clock signal;
Logic fixing means for fixing and activating the logic of at least the final stage of the logic circuit;
A second register that is logically equivalent to the first register and that captures data from the logic fixing means at a predetermined timing of the clock signal;
A third register for fetching data from the logic circuit excluding at least the final stage logic of the logic circuit at a predetermined timing of the clock signal;
A semiconductor device comprising: a comparator that compares the output of the second register and the output of the third register and outputs an error signal. Clock control means for controlling the transmission of the clock signal based on the enable signal;
A first register for fetching data from a logic circuit at a predetermined timing of the clock signal transmitted from the clock control means;
Delay means for delaying the clock signal;
A second register that is logically equivalent to the first register and that captures data at a predetermined timing of the clock signal that has passed through the delay means;
Logic selection means for selecting either data from the logic circuit or the output of the second register in the previous cycle based on the enable signal, and setting the data to be input to the second register;
A semiconductor device comprising: a comparator that compares the output of the first register and the output of the second register and outputs an error signal. A semiconductor device according to any one of claims 1 to 10,
A semiconductor device characterized in that all or part of a circuit including the first register and the second register is formed into a cell. A first register for fetching data from the logic circuit at a predetermined timing of the clock signal;
Delay means for delaying the clock signal;
A second register that is logically equivalent to the first register, fetches data from the logic circuit at a predetermined timing of the clock signal that has passed through the delay means;
A plurality of semiconductor circuits each comprising a comparator for comparing the output of the first register and the output of the second register and outputting a comparison signal;
An error signal generation circuit that performs predetermined processing on the plurality of comparison signals in the plurality of semiconductor circuits to generate an error signal;
A clock signal generation circuit for controlling the frequency of the clock signal based on the error signal;
And a regulator circuit that controls a voltage supplied to the plurality of semiconductor circuits based on the error signal. Delay means for generating a second clock signal obtained by delaying the first clock signal for a predetermined period;
A first register for capturing data from a logic circuit at a predetermined timing of the second clock signal;
A second register that is logically equivalent to the first register and that captures data from the logic circuit at a predetermined timing of the first clock signal;
A semiconductor device comprising: a comparator that compares the output of the first register and the output of the second register and outputs an error signal. The semiconductor device according to claim 13,
The delay unit sets a delay amount by changing a transistor size or a circuit topology of the second register with respect to the first register.

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