JP2010071750A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of apparently increasing a time usable for computing in combinational circuits and of inspecting both of setup time errors and hold time errors. <P>SOLUTION: The semiconductor device includes a first latch 112, a second latch 113 connected in parallel with the first latch for inputting output data of data treatment circuits, a first clock controller 115 supplying a reference clock clk and a second clock clk-δ with a phase put forward from the reference clock, a first comparator 114 comparing latch data of the first latch and latch data of the second latch and generating an error signal depending on the comparison result, and a controller 170; in which the first latch 112 synchronizes with the second clock and latches the input data and outputs the latch data to a data pass and the comparator, and the second latch 113 synchronizes with the reference clock and latches the input data and outputs the latch data to the comparator 114. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device adapted to lower power consumption, for example.

  Recently, Razor-FF circuit technology, Canary-FF circuit technology, and the like have been proposed as technologies for reducing power consumption of semiconductor devices (see Non-Patent Documents 2 and 3).

If a design margin is provided for guaranteeing operation when the power supply voltage is lowered during operation, the performance of the semiconductor circuit is degraded.
Therefore, in the above technique, a design method has been proposed in which it is not necessary to consider a design margin for guaranteeing the operation by detecting an error on an actual chip during a low power consumption operation (when the power supply voltage is lowered). .

  The above circuit has a parallel latch configuration that connects a latch formed by a flip-flop FF used in a synchronous circuit and a latch formed by a flip-flop FF that operates stably in parallel.

  FIG. 1 is a schematic diagram and timing diagram of a commonly used latch.

The latch 1 formed by the D-type flip-flop DFF has a function of sending a signal in synchronization with the clock CLK, and has three terminals of an input (INPUT) D, a clock (CLOCK) CLK, and an output (OUTPUT) Q. is doing.
The input INPUT to the terminal D needs to reach the latch 1 earlier than the setup time TSUP based on the clock CLK.
Further, the input INPUT needs to maintain the data value during the hold time THLD after the clock CLK is input.
When operating at a high frequency, an important concern is whether data can reach the input D earlier than the setup time TSUP.

<Parallel latch>
2A and 2B are diagrams illustrating a semiconductor device in which latches disclosed in Non-Patent Document 1 are connected in parallel.

  The semiconductor device 10 basically includes a combinational circuit 11, a first latch 12, a second latch 13, and a comparator 14.

  As described above, the semiconductor devices 10 and 10A have the first latch (Output latch) 12 that becomes the data path itself, and the second latch (Extra latch) 13 for performing data inspection.

The semiconductor device 10 in FIG. 2A is a case where a delay time δ is added to the output data of the combinational circuit 12 and input to a second latch 13.
The semiconductor device 10A of FIG. 2B is a case where a delay time δ is added to the clock Clk and input to a second latch (Extra latch).

  FIG. 3 is a diagram illustrating a timing example of the semiconductor device 10A of FIG.

In a semiconductor device that dynamically optimizes power consumption, the power supply voltage Vdd is lowered to reduce AC power.
At this time, since the frequency of the product is constant, there is no room for data to reach the clock, and a setup time error is likely to occur in the first latch (Output latch) 12.
Therefore, in the semiconductor device 10A, a more stable latch operation is realized by supplying a clock obtained by adding a delay time δ to the second latch (Extra latch) 13.

The power supply voltage Vdd is lowered, the outputs of the first latch (output latch) 12 and the second latch (extra latch) 13 are compared by the comparator 14, and if there is a difference, an erroneous signal is output by the first latch 12. An error signal is output by judging that the data has been output.
In the semiconductor device 10A, when this error signal is generated, the signal transmitted in error is returned, the power supply voltage is restored, and reprocessing is performed.
In this way, the parallel latch is used to check for malfunctions occurring in one latch.
2002 IEEE Design & Test of Computers, iRoC Technologies 2004 IEEE Computer Society, Michigan / ARM, Razor-FF 2007 International Symposium of Quality Design, A Simple Flip-Flop Circuit for Typical Case Design for DFM Japanese Patent Laid-Open No. 9-139731

  As mentioned above, Razor-FF, Canary-FF, etc. that inspect whether the signal reaching the latch (FF) from the combinational circuit matches the timing margin of the latch (FF) in order to operate as a synchronous circuit Has been.

  However, although the above-described circuit has a function of checking the timing validity of the signal, it cannot improve the time processed by the combinational circuit and improve the timing itself in the latch (FF).

  It is an object of the present invention to provide a semiconductor device capable of apparently increasing the time that can be used for computation in a combinational circuit.

  A semiconductor device according to a first aspect of the present invention includes a data processing circuit that outputs data to be transmitted, a first latch that latches output data of the data processing circuit, and input of output data of the data processing circuit. On the other hand, a second latch connected in parallel with the first latch, a clock controller for supplying a reference clock and a second clock whose phase is advanced from the reference clock, latch data of the first latch, Comparing the latch data of the second latch and generating an error signal according to the comparison result, and according to the error signal, the data processing circuit or the first latch and the second latch And a controller for controlling at least one of the operating states, wherein the first latch latches input data in synchronization with the second clock. Outputs latched data to the data path and the comparator, the second latch latches the input data in synchronism with the reference clock, and outputs the latched data to the comparator.

  A semiconductor device according to a second aspect of the present invention includes a transmission-side semiconductor circuit that transmits transmission data to a data path, a reception-side semiconductor circuit that receives transmission data propagated through the data path, and a controller. The transmission-side semiconductor circuit includes a first data processing circuit that outputs data to be transmitted, a first latch that latches output data of the first data processing circuit, and a first data processing circuit. A second latch connected in parallel to the first latch for the input of output data, a first reference clock, and a first clock for supplying a second clock whose phase is advanced from that of the first reference clock. A first controller that compares the latch data of the first latch and the latch data of the second latch and generates a first error signal according to the comparison result. The first latch latches input data in synchronization with the second clock, outputs the latch data to the data path and the first comparator, and the second latch The input data is latched in synchronization with a reference clock, the latch data is output to the first comparator, and the transmission side semiconductor circuit latches the transmission data propagated through the data path; A fourth latch connected in parallel to the third latch with respect to the input of the transmission data, a second data processing circuit for processing the third latch data, and a second reference clock are supplied A second comparator that compares the third latch data with the fourth latch data and generates a second error signal according to the comparison result. The third latch latches input data in synchronization with the second reference clock, outputs the latch data to the second data processing circuit, and the fourth latch The input data is latched in synchronization with the second reference clock, and the latched data is output to the second comparator. The controller is configured to output the first data processing circuit or at least according to the first error signal. The operating state of at least one of the first latch and the second latch is controlled.

  Preferably, at least the first latch and the second latch have a first power supply for supplying an operating voltage whose value can be changed in accordance with a first control signal, and the controller has the first power supply. When the operation voltage is set lower than the normal operation voltage supplied from the first power source by the control signal 1, the first error signal is output from the first latch and the output from the second latch. If the data indicates that the data is different, the first control signal is output to the first power supply so that the operating voltage is at least higher than the set low operating voltage.

  Preferably, the first clock controller supplies the first reference clock to the first data processing circuit, and the first data processing circuit performs data synchronization in synchronization with the first reference clock. If the first error signal indicates that the output data of the first latch is different from the output data of the second latch, the controller performs processing and output. The controller temporarily stops the supply of the first reference clock to the first data processing circuit, and sends the first control signal to the first operation signal so that the operation voltage becomes the normal operation voltage. Output to the clock controller and the first power source.

  Preferably, the first clock controller supplies the first reference clock to the first data processing circuit, and the first data processing circuit performs data synchronization in synchronization with the first reference clock. The second clock controller supplies the second reference clock to the second data processing circuit, and the second data processing circuit is synchronized with the second reference clock. And when the first error signal indicates that the output data of the first latch is different from the output data of the second latch, the controller executes the first clock signal. The controller temporarily stops the supply of the first reference clock to the first data processing circuit, and the second clock controller temporarily stops the second reference clock. The first control signal is sent to the first clock controller and the first power supply so that the operating voltage becomes higher than at least the set low operating voltage. And outputs the second control signal to the second clock controller.

  Preferably, when the first error signal indicates that the output data of the first latch is different from the output data of the second latch, the controller sets the operating voltage to the normal voltage. The first control signal is output to the first power supply so that the operating voltage is

  Preferably, the controller has a second power supply for supplying an operating voltage whose value can be changed in accordance with a second control signal to at least the third latch and the fourth latch. When the operation voltage is set to be lower than the normal operation voltage supplied from the second power source by the control signal 2, the second error signal is output from the third latch and the output from the fourth latch. When the data indicates that the data is different, the second control signal is output to the second power supply so that the operating voltage is at least higher than the set low operating voltage.

According to the present invention, the output data of the data processing circuit is latched by the first latch in synchronization with the second clock whose phase is advanced from the reference clock. The latch data of the second latch is output to the data path and the comparator.
The output data of the data processing circuit is latched in the second latch in synchronization with the reference clock. The latch data of the second latch is output to the comparator.
In the comparator, the latch data of the first latch and the latch data of the second latch are compared, and an error signal corresponding to the comparison result is supplied to the controller.
In the controller, the operation state of at least one of the data processing circuit or the first latch and the second latch is controlled in accordance with the error signal.

  According to the present invention, it is possible to apparently increase the time that can be used for computation in the combinational circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 4 is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present invention.

  The semiconductor device 100 includes a transmission-side semiconductor circuit 110, a reception-side semiconductor circuit 120, a first power supply 130, a second power supply 140, a first clock generation unit 150, a second clock generation unit 160, and a controller 170. Have.

The transmission-side semiconductor circuit 110 operates by receiving the supply of the operating voltage Vdd1 from the first power supply 130 and the supply of the clock clk having a predetermined frequency generated by the first clock generation unit 150.
The transmission-side semiconductor circuit 110 includes a first logic circuit 111 as a first data processing circuit, a first latch 112, a third latch 113, a first comparator 114, and a first clock controller 115. ing.

The first logic circuit 111 performs a logical operation in synchronization with the first reference clock clk supplied from the first clock controller 115, and outputs the operation result to the first latch 112 and the second latch 113. .
When the supply of the first reference clock clk from the first clock controller 115 is stopped, the first logic circuit 111 stops the calculation and output operation during the stop period.

The first latch 112 is formed by a D-type flip-flop (FF1), and has three terminals of an input D, a clock CLK, and an output Q.
The first latch 112 supplies a signal in synchronization with the second clock clk-δ, which is supplied to the second latch 113 by the first clock controller 115 and whose phase is advanced by δ from the first reference clock clk. Has a function to send out.
The first latch 112 basically has the input data FF1 from the first logic circuit 111 to the terminal D. In needs to reach the first latch 112 earlier than the setup time TSUP based on the second clock clk-δ.
The first latch 112 receives the input data FF1 fetched from the terminal D. It is necessary to maintain the data value for the hold time THLD after the second clock clk-δ is input.
The first latch 112 receives the latch data from the terminal Q to the data FF1. out is output to the receiving-side semiconductor circuit 120 via the first comparator 114 and the data path DP.

The second latch 113 is formed by a D-type flip-flop (FF1 ′) and has three terminals of an input D, a clock CLK, and an output Q.
The second latch 113 has a function of sending a signal in synchronization with the first reference clock clk supplied to the second latch 113 by the first clock controller 115.
The second latch 113 basically has the input data FF1 from the first logic circuit 111 to the terminal D. In needs to reach the second latch 113 earlier than the setup time TSUP based on the first reference clock clk.
Further, the second latch 113 receives the input data FF1 fetched from the terminal D. It is necessary to maintain the data value for the hold time THLD after the first reference clock clk is input.
The second latch 113 receives the latch data from the terminal Q to the data FF1 ′. out is output to the first comparator 114.

The first comparator 114 outputs the output data FF1 of the first latch 112. out and output data FF1 ′ of the second latch 113 out is compared, and when both data match, the error signal c1 “out” is set to a low level, and if it does not match, it is set to a high level.
The first comparator 114 receives the first error signal c1 out is output to the controller 170.

The first clock controller 115 receives the clock clk supplied from the first clock generation unit 150 and supplies it to the first logic circuit 111 as the first reference clock clk.
The first clock controller 115 supplies the clock clk to the second latch 113, and supplies the second clock clk-δ obtained by advancing the phase of the first reference clock clk by δ to the first latch 112. To do.
The first clock controller 115 can stop the supply of the first reference clock clk to the first logic circuit 111 for a predetermined period in accordance with the first control signal CTL12 of the controller 170.

  FIGS. 5A and 5B are diagrams illustrating an example of a circuit for generating the first reference clock clk of the first clock generation unit 140 and the second clock clk-δ whose phase is advanced by δ.

FIG. 5A shows that the first reference clock clk propagates through the buffer BF2 formed by the transistor having the standard threshold voltage Vth, and the second clock clk-δ that is earlier by the phase δ is lower than the standard. In this example, a buffer BF1 formed by a transistor having a threshold value is propagated.
Buffers BF1 and BF2 are configured, for example, by connecting two CMOS inverters in series.
The threshold value of the MOS transistor can be adjusted by, for example, a silicon process.
In this way, the delay time difference can be realized by propagating the clock through the buffers BF1 and BF2 having different threshold values.
Alternatively, an early phase clock can be formed by changing the threshold value Vth by controlling the substrate bias of the transistor used for generating the second clock clk-δ.

FIG. 5B shows an example in which a clock having a delay time more than necessary when the clock clk is distributed and whose phase is delayed is used as a standard clock, and a clock having a minimum delay time is used as the second clock clk-δ. is there.
In this example, the threshold values of the MOS transistors forming the buffers BF3 and BF3-1 to BF3-4 are set to the same threshold value.

  FIG. 6 is a diagram for explaining the characteristic configuration and function of the transmission-side semiconductor circuit 110 according to the present embodiment.

The transmission-side semiconductor circuit 110 according to the present embodiment applies a second clock clk-δ having an early phase to the first latch 112 and sends out the data by so-called flying.
A normal first reference clock clk is applied to the second latch 113 arranged in parallel with the first latch 112 with respect to the data input line to obtain a stable output.
The outputs of the first latch 112 and the second latch 113 are compared by the first comparator 114 to check whether the data sent from the first latch 112 is correct.
If a wrong signal is sent out as a result of the inspection, the signal is returned or replaced. In particular, the sent signal has the effect of making the time allowed to pass through the data path (DP) processed in the combinational circuit before reaching the next latch apparently, so that it is effective to block between blocks and chips. This is effective when a signal is propagated over a long distance.
The control according to the inspection and the inspection result is performed by the controller 170. This control will be described in detail later.

The receiving-side semiconductor circuit 120 receives the supply of the operating voltage Vdd2 from the second power supply 140 and operates by receiving the supply of the second reference clock clk having a predetermined frequency generated by the second clock generator 160.
The receiving-side semiconductor circuit 120 includes a second logic circuit 121 as a second data processing circuit, a third latch 122, a fourth latch 123, a second comparator 124, a second clock controller 125, and a delay unit. 126.

The second logic circuit 121 outputs the output data FF2 of the third latch 122 in synchronization with the second reference clock clk supplied from the second clock controller 125. Perform logical operation on out.
When the supply of the second reference clock clk from the second clock controller 125 is stopped, the second logic circuit 121 stops the arithmetic operation and the output operation during the stop period.

The third latch 122 is formed by a D-type flip-flop (FF2), and has three terminals of an input D, a clock CLK, and an output Q.
The third latch 122 has a function of sending out a signal in synchronization with the second reference clock clk supplied by the second clock controller 125.
The third latch 122 basically has the input data FF2 propagated through the data path DP to the terminal D. In needs to reach the third latch 122 earlier than the setup time TSUP based on the second reference clock clk.
The third latch 122 receives the input data FF2 fetched from the terminal D. It is necessary to maintain the data value during the hold time THLD after the second reference clock clk is input.
The third latch 122 receives the latch data from the terminal Q to the data FF2 “out” is output to the second logic circuit 121 and the second comparator 124.

The fourth latch 123 is formed by a D-type flip-flop (FF2 ′) and has three terminals of an input D, a clock CLK, and an output Q.
The fourth latch 123 has a function of sending a signal in synchronization with the second reference clock clk supplied to the fourth latch 123 by the second clock controller 125.
The fourth latch 123 basically has the input data FF2 propagated through the data path DP to the terminal D. It is necessary to reach FF2′_in in which in has passed through the delay 126 to the fourth latch 123 earlier than the setup time TSUP based on the second reference clock clk.
Further, the fourth latch 123 receives the input data FF2 fetched from the terminal D. It is necessary to maintain the data value during the hold time THLD after the second reference clock clk is input.
The fourth latch 123 receives the latch data from the terminal Q to the data FF2 ′. out is output to the second comparator 124.

The second comparator 124 outputs the output data FF2 of the third latch 122. out and output data FF2 ′ of the fourth latch 123 out and when both data match, the error signal c2 “out” is set to a low level, and if it does not match, it is set to a high level.
The second comparator 124 receives the second error signal c2 out is output to the controller 170.

The second clock controller 125 receives the clock clk supplied from the first clock generation unit 140 and supplies it to the second logic circuit 121, the third latch 122, and the fourth latch 123.
The second clock controller 125 can stop supplying the clock clk to the second logic circuit 121 for a predetermined period in accordance with the second control signal CTL22 of the controller 170.

The first power supply 130 supplies the operating voltage Vdd1 to the transmission-side semiconductor circuit 110.
The first power supply 130 is configured to be able to change the operating voltage Vdd1 supplied to the transmission-side semiconductor circuit 110 by the first control signal CTL11 of the controller 170.
The first power supply 130 can normally supply the voltage Vdd1 at 1.0 V, for example, and set the voltage Vdd1 to a low voltage such as 0.8 V in accordance with the instruction of the first control signal CTL11. is there.
Further, the first power supply 130 can raise and lower the voltage Vdd1 by, for example, 0.05V as one step by the first control signal CTL11 of the controller 170.
The first power supply 130 directly sets the voltage Vdd1 once set to a low voltage such as 0.8V by the first control signal CTL11 of the controller 170 to the original 1.0V instead of stepping up and down by one step. It is also possible to return.

The second power supply 140 supplies the operating voltage Vdd2 to the receiving-side semiconductor circuit 120.
The second power supply 140 is configured to be able to change the operating voltage Vdd2 supplied to the receiving-side semiconductor circuit 120 by the second control signal CTL21 of the controller 170.
The second power supply 140 normally supplies the voltage Vdd2 at, for example, 1.0V, and can supply the voltage Vdd2 set to a low voltage such as 0.8V in accordance with the instruction of the second control signal CTL21. is there.
The second power supply 140 directly increases the voltage Vdd2 once set to a low voltage such as 0.8V by the second control signal CTL21 of the controller 170 to the original 1.0V instead of stepping up and down by one step. It is also possible to return.
The second power supply 140 can raise and lower the voltage Vdd2 by, for example, 0.05 V as one step by the second control signal CTL21 of the controller 170.

  The first clock generation unit 150 supplies a clock clk having a predetermined frequency to the first clock controller 115 of the transmission-side semiconductor circuit 110.

  The second clock generation unit 160 supplies a clock clk having a predetermined frequency to the second clock controller 125 of the reception-side semiconductor circuit 120.

Note that the operating voltage Vdd1 from the first power supply 130 and the operating voltage Vdd2 from the second power supply 140 may have the same or different values at normal times.
Similarly, the frequency of the clock clk by the first clock generation unit 150 and the frequency of the clock clk by the second clock generation unit 160 may be the same frequency or different frequencies.

The controller 170 receives the error signal c1 of the first comparator 114 of the transmission-side semiconductor circuit 110. out and the error signal c2 of the comparator 1124 of the receiving-side semiconductor circuit 120 The values of the operating voltages Vdd1 and Vdd2 are controlled according to the supply level of out.

The controller 170 is operated at a normal voltage of 1.0 V, and the error signal c1 out, c2 When out is at a low level, the first control signal CTL11 is output to the first power supply 130 so as to set the operating voltage Vdd1 to 0.8 V, for example, in order to realize a low power consumption operation.
The controller 170 receives the first error signal c1 When out is received at a high level, the control signal CTL12 is output to the first clock controller 115 so that the supply of the clock clk to the first logic circuit 111 of the transmission-side semiconductor circuit 110 is stopped by one clock.
The controller 170 receives the first error signal c1 When out is received at a high level, the control signal CTL22 is output to the second clock controller 125 so that the supply of the clock clk to the second logic circuit 121 of the reception-side semiconductor circuit 120 is stopped by one clock.
The controller 170 receives the first error signal c1 When out is received at a high level, the data of the first latch 112 and the second latch 113 are different and an error has occurred, and the control signal CTL11 is returned to the first power supply 130 so that the operating voltage Vdd1 is returned to 1.0V. Output to.
The controller 170 sends a second error signal c2 If out is received at a high level, the first control signal CTL11 is output to the first power supply 130 so that the operating voltage Vdd1 is returned to 1.0 V, assuming that the failure is detected in advance, although it is not an actual failure.

The controller 170 also sends an error signal c1. out, c2 When out is at a low level, the second control signal CTL21 is output to the second power supply 140 so as to set the operating voltage Vdd2 to, for example, 0.8V in order to realize a low power consumption operation.
In this case, the controller 170 sends the second error signal c2 When out is received at a high level, the second control signal CTL21 is output to the second power supply 140 so as to return the operating voltage Vdd2 to 1.0 V, assuming that the failure is detected in advance, although it is not an actual failure.

Next, the operation of the configuration shown in FIG. 4 will be described with reference to FIGS.
FIG. 7 is a timing chart for explaining the operation of the semiconductor device according to the present embodiment.
FIG. 8 is a flowchart for explaining the operation of the semiconductor device according to the present embodiment.

First, the controller 170 supplies the first control signal CTL11 to the first power supply 130 and the second control signal CTL21 to the second power supply 140 in order to operate at a normal voltage of 1.0V.
As a result, the first power supply 130 supplies the normal operating voltage Vdd 1 of 1.0 V to the transmission-side semiconductor circuit 110. Similarly, the second power supply 140 supplies a normal operating voltage Vdd2 of 1.0 V to the receiving-side semiconductor circuit 120.

The controller 170 outputs the first control signal CTL12 so as to supply a clock to the first clock controller 115 of the transmission-side semiconductor circuit 110.
Accordingly, the first clock controller 115 supplies the first reference clock clk to the first logic circuit 111 and the second latch 113, and the phase of the first latch 112 is advanced by δ from the clock clk ( The second clock clk-δ is supplied.

Further, the controller 170 outputs the second control signal CTL22 so as to supply a clock to the second clock controller 125 of the receiving-side semiconductor circuit 120.
As a result, the second clock controller 125 supplies the second reference clock clk to the second logic circuit 121, the third latch 122, and the fourth latch 123.

In this state, in the transmission-side semiconductor circuit 110, the first logic circuit 111 performs a logical operation in synchronization with the clock clk, and the result is output to the first latch 112 and the second latch 113.
The first latch 112 receives the input data FF1. in is latched in synchronization with the second clock clk-δ whose phase is δ earlier than the first reference clock clk, and the latched data is the data signal FF1. The data is output to the data path DP and the first comparator 114 as out.
The second latch 113 receives the input data FF1. in is latched in synchronization with the first reference clock clk, and the latch data is transferred to the data signal FF1 ′. The result is output to the first comparator 114 as out.
The first comparator 114 outputs the output data FF1 of the first latch 112. out and output data FF1 ′ of the second latch 113 Compare out. Then, the comparator 114 displays the comparison result between the two data as an error signal c1. It outputs to the controller 170 as out.

In addition, the data signal FF1 output from the first latch 112 out is propagated through the data path DP, and the data signal FF2 is transmitted to the receiving-side semiconductor circuit 120. Input as in.

The reception side semiconductor circuit 120 monitors the reception state.
The third latch 122 receives the input data FF2 in is latched in synchronization with the second reference clock clk, and the latched data is the data signal FF2. It is output to the second logic circuit 121 and the second comparator 124 as out.
The fourth latch 123 receives the input data FF2 data FF2 ′ in which the in is delayed by the delay unit 126 in is latched in synchronization with the second reference clock clk, and the latch data is transferred to the data signal FF2 '. It outputs to the 2nd comparator 124 as out.
The second comparator 124 outputs the output data FF2 of the third latch 122. out and output data FF2 ′ of the fourth latch 123 Compare out. The comparator 124 then compares the comparison result between the two data with the error signal c2. It outputs to the controller 170 as out.

The controller 170 is operated at a normal voltage of 1.0 V, and the error signal c1 out, c2 When out is at a low level, control as shown in FIG. 8 is performed.

The controller 170 outputs the first control signal CTL11 to the first power supply 130 so as to set the operating voltage Vdd1 to 0.8 V, for example, in order to realize the low power consumption operation (ST1).
Then, in the semiconductor circuit 110 on the transmission side, the first logic circuit 111 performs a logical operation in synchronization with the clock clk under the operating voltage of 0.8 V, and the result is output to the first latch 112 and the second latch 113. Is done.
The first latch 112 receives the input data FF1. in is latched in synchronization with the clock clk-δ whose phase is δ earlier than the clock clk, and the latched data is the data signal FF1 The data is output to the data path DP and the first comparator 114 as out.
The second latch 113 receives the input data FF1. in is latched in synchronization with the clock clk, and the latched data is transferred to the data signal FF1 ′. The result is output to the first comparator 114 as out.
The first comparator 114 outputs the output data FF1 of the first latch 112. out and output data FF1 ′ of the second latch 113 Compare out. Then, the comparator 114 displays the comparison result between the two data as an error signal c1. It outputs to the controller 170 as out.

  Here, the controller 170 receives the first error signal c1. It is determined whether or not “out” is received at a high level (ST2).
  The controller 170 receives an error signal c1 When out is received at a high level, the first control signal CTL12 is output to the first clock controller 115 so that the supply of the clock clk to the first logic circuit 111 of the transmission-side semiconductor circuit 110 is stopped for one clock. (ST3).
  Similarly, the controller 170 receives an error signal c1. When out is received at a high level, the second control signal CTL22 is output to the second clock controller 125 so that the supply of the clock clk to the second logic circuit 121 of the receiving-side semiconductor circuit 120 is stopped by one clock. (ST4).
  The controller 170 also sends an error signal c1. If out is received at a high level, it is assumed that an error has occurred, and the first control signal CTL11 is output to the first power supply 130 so that the operating voltage Vdd1 is returned to 1.0 V (ST5).

As described above, when the supply of the clock clk to the first logic circuit 111 is stopped once and the operation voltage Vdd1 is returned to the original normal voltage, the first latch 112 is connected to the first logic circuit 111 from the first logic circuit 111. Can be latched with a margin (ST6).
That is, since the data from the first logic circuit 111 of the transmission-side semiconductor circuit 110 has arrived reliably in the state before the operating voltage Vdd1 is lowered, the first latch 112 operates reliably.

  When the supply of the clock clk to the second logic circuit 121 is stopped once, the third latch 122 latches the data from the first latch 112 of the transmission-side semiconductor circuit 110, and the second latch Can be sent to the logic circuit 121 (ST7).

  When an error occurs in the above processing, it is possible to perform control such as raising the operating voltage Vdd1 from that during normal operation.

In addition, the controller 170 receives the second error signal c2. If out is received at a high level (ST8), the first control signal CTL11 is supplied to the first power supply 130 so that the operating voltage Vdd1 is returned to 1.0 V, assuming that the failure has been detected in advance, although it is not an actual failure. Output (ST9).

In addition, the controller 170 receives an error signal c1. out, c2 When out is at a low level, the second control signal CTL21 can be output to the second power supply 140 so that the operating voltage Vdd2 is set to 0.8 V, for example (ST10).
In this case, the controller 170 sends the second error signal c2 When out is received at a high level (ST11), the second control signal CTL21 is sent to the second power supply 140 so that the operating voltage Vdd2 is returned to 1.0 V, assuming that the failure has been detected in advance, although it is not an actual failure. Output (ST12).

In the timing chart of FIG. 7, Vdd1 is lowered from normal operation (ST1), the comparator 114 receives the error signal C1_OUT (ST2), and the comparator 124 also receives the error signal C2_OUT (ST8).

According to the present embodiment described above, the first latch 112 is supplied to the second latch 113 by the first clock controller 115, and the second latch whose phase is advanced by δ from the first reference clock clk. It has a function of sending out a signal in synchronization with the clock clk-δ.
The second latch 113 has a function of sending a signal in synchronization with the clock clk supplied to the second latch 113 by the first clock controller 115.
The first comparator 114 outputs the output data FF1 of the first latch 112. out and output data FF1 ′ of the second latch 113 When the two data are matched with each other, the error signal c1 “out” is set to a low level, and if it does not match, it is set to a high level.
The controller 170 then sends an error signal c1. Control of the operating voltage Vdd1 and supply of a clock to the logic circuit are performed according to out.
That is, according to this embodiment, the validity of a signal can be inspected by combining a clock with an advanced phase and parallelization of a latch, and a mode having the following functions can be realized.
(1) A signal is sent by flying from the first latch to the combinational circuit, and the time that can be used for the calculation in the combinational circuit is apparently increased.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is the figure which shows the schematic and timing of the latch which is generally used. It is a figure which shows the semiconductor device which connected the latch currently disclosed by the nonpatent literature in parallel. FIG. 3 is a diagram illustrating a timing example of the semiconductor device in FIG. It is a figure showing an example of composition of a semiconductor device concerning one embodiment of the present invention. It is a figure which shows the example of a production | generation circuit of clock clk-delta which advanced the clock clk of the 1st clock generation part 0, and the phase by (delta). It is a figure for demonstrating the characteristic structure and function of the transmission side semiconductor circuit which concerns on this embodiment. 6 is a timing chart for explaining the operation of the semiconductor device according to the embodiment. 3 is a flowchart for explaining the operation of the semiconductor device according to the embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor device, 110 ... Transmission side semiconductor circuit, 111 ... Logic circuit, 112 ... 1st latch, 113 ... 3rd latch, 114 ... Comparator, 115 ...・ Clock controller, 120... Receiving side semiconductor circuit, 121... Logic circuit, 122... Third latch, 123... Fourth latch, 124. , 126 ... delay unit, 130 ... first power source, 140 ... second power source, 15 ... first clock generation unit, 160 ... second clock generation unit, 170 ··controller.

Claims (11)

A data processing circuit for outputting data to be transmitted;
A first latch for latching output data of the data processing circuit;
A second latch connected in parallel with the first latch with respect to input of output data of the data processing circuit;
A clock controller for supplying a reference clock and a second clock having a phase advanced from the reference clock;
A comparator that compares the latch data of the first latch with the latch data of the second latch and generates an error signal according to the comparison result;
A controller for controlling an operation state of at least one of the data processing circuit or the first latch and the second latch in response to the error signal,
The first latch is
The input data is latched in synchronization with the second clock, the latch data is output to the data path and the comparator,
The second latch is
A semiconductor device that latches input data in synchronization with the reference clock and outputs the latched data to the comparator. A power supply for supplying an operating voltage whose value can be changed according to a control signal to at least the first latch and the second latch;
The controller
The error signal indicates that the output data of the first latch is different from the output data of the second latch when the control signal is set to an operating voltage lower than a normal operating voltage supplied from the power source. 2. The semiconductor device according to claim 1, wherein the control signal is output to the power supply so that the operating voltage is higher than at least the set low operating voltage. The clock controller
Supplying the reference clock to the data processing circuit;
The data processing circuit
Data processing and output are performed in synchronization with the reference clock,
The controller
When the error signal indicates that the output data of the first latch is different from the output data of the second latch, the clock controller temporarily stops supplying the reference clock to the data processing circuit. The semiconductor device according to claim 2, wherein the control signal is output to the clock controller and the power supply so that the operating voltage is higher than at least the set low operating voltage. The controller
When the error signal indicates that the output data of the first latch is different from the output data of the second latch, the control signal is set so that the operating voltage becomes the normal operating voltage. The semiconductor device according to claim 2, wherein the power is output to the power source. A transmission-side semiconductor circuit for sending transmission data to the data path;
A receiving-side semiconductor circuit that receives transmission data propagated through the data path;
A controller, and
The transmitting semiconductor circuit is
A first data processing circuit for outputting data to be transmitted;
A first latch for latching output data of the first data processing circuit;
A second latch connected in parallel with the first latch with respect to an input of output data of the first data processing circuit;
A first clock controller for supplying a first reference clock and a second clock having a phase advanced from that of the first reference clock;
A first comparator that compares the latch data of the first latch and the latch data of the second latch and generates a first error signal according to the comparison result;
The first latch is
The input data is latched in synchronization with the second clock, the latch data is output to the data path and the first comparator,
The second latch is
The input data is latched in synchronization with the first reference clock, the latch data is output to the first comparator,
The transmitting semiconductor circuit is
A third latch for latching the transmission data propagated through the data path;
A fourth latch connected in parallel with the third latch with respect to the input of the transmission data;
A second data processing circuit for performing processing on the third latch data;
A second clock controller for supplying a second reference clock;
A second comparator that compares the third latch data with the fourth latch data and generates a second error signal according to the comparison result;
The third latch is
The input data is latched in synchronization with the second reference clock, the latch data is output to the second data processing circuit,
The fourth latch is
The input data is latched in synchronization with the second reference clock, the latch data is output to the second comparator,
The controller
A semiconductor device that controls an operation state of at least one of the first data processing circuit or the first latch and the second latch in accordance with at least the first error signal. A first power supply for supplying an operating voltage whose value can be changed according to a first control signal to at least the first latch and the second latch;
The controller
When the operating voltage lower than the normal operating voltage supplied from the first power source is set by the first control signal, the first error signal causes the output data of the first latch and the second latch to be If the output data is different, the first control signal is output to the first power supply so that the operating voltage is at least higher than the set low operating voltage. Item 6. A semiconductor device according to Item 5. The first clock controller includes:
Supplying the first reference clock to the first data processing circuit;
The first data processing circuit includes:
Data processing and output are performed in synchronization with the first reference clock,
The controller
If the first error signal indicates that the output data of the first latch is different from the output data of the second latch, the first clock signal is temporarily transmitted to the first clock controller. The supply to the first data processing circuit is stopped, and the first control signal is output to the first clock controller and the first power supply so that the operating voltage becomes the normal operating voltage. The semiconductor device according to claim 6. The first clock controller includes:
Supplying the first reference clock to the first data processing circuit;
The first data processing circuit includes:
Data processing and output are performed in synchronization with the first reference clock,
The second clock controller is
Supplying the second reference clock to the second data processing circuit;
The second data processing circuit includes:
Data processing is performed in synchronization with the second reference clock,
The controller
If the first error signal indicates that the output data of the first latch and the output data of the second latch are different,
The first clock controller temporarily stops supplying the first reference clock to the first data processing circuit;
The second clock controller temporarily stops supplying the second reference clock to the second data processing circuit;
The first control signal is output to the first clock controller and the first power supply so that the operating voltage is higher than at least the set low operating voltage, and the second control signal is The semiconductor device according to claim 6, wherein the semiconductor device outputs to the second clock controller. The controller
When the first error signal indicates that the output data of the first latch is different from the output data of the second latch, the operating voltage is set to the normal operating voltage. The semiconductor device according to claim 7, wherein the first control signal is output to the first power source. A second power supply for supplying an operating voltage whose value can be changed according to a second control signal to at least the third latch and the fourth latch;
The controller
When the operating voltage lower than the normal operating voltage supplied from the second power source is set by the second control signal, the second error signal causes the output data of the third latch and the fourth latch to If the output data is different, the second control signal is output to the second power supply so that the operating voltage is at least higher than the set low operating voltage. Item 10. The semiconductor device according to any one of Items 6 to 9. The controller
When the second error signal indicates that the output data of the third latch is different from the output data of the fourth latch, the operating voltage is set to the normal operating voltage. The semiconductor device according to claim 10, wherein the second control signal is output to the second power source.

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