JPH02236709A - Timing signal generating device and method and device for detecting its error - Google Patents

Abstract

PURPOSE:To prevent an erroneous processing caused by noise and etc., by predicting the state of the next step based on the current state of a timing signal, and judging that the malfunction exists when noncoincidence between a predictor and the actual timing signal corresponding to a step predicted by the predictor is obtained. CONSTITUTION:The timing signal changing at every step is outputted from a timing signal generating means 3 at every input of a clock signal 11. Meanwhile, a prediction circuit 6 predicts the state of the next step from the current state of the timing signal, and outputs a signal for that. Those two output signals are compared with each other by a comparison means 9, and the malfunction of the timing signal generating means is detected when the noncoincidence is obtained between both signals. Thereby, it is possible to suppress the malfunction of a system to a minimum without continuing the output of an unrequired timing signal when the malfunction occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing signal generation device, an error detection method and device thereof.

[Conventional technology] In the transmission of data, timing signals, etc., errors may occur during transmission due to noise, etc. Conventionally, as a method for detecting such errors, for example, Iwanami Lecture, Information Science-4 "Theory of Information and Codes" (Iwanami Shoten,
1983, 1), p. 123 et seq., an error detection method was used.

FIG. 4 shows a timing signal generator using a conventional error detection method.

In FIG. 4, 60 is a timing signal generation circuit that outputs a timing signal in response to a clock signal, 61 is a parity generation circuit, and 62 is a parity check circuit. 6
3 is a timing signal, 64 is a parity signal of the timing signal, 65 is a parity check result signal, and 66 is a transmission line.

The timing signal 63 generated by the timing signal generation circuit 60 is output to the transmission line 66 together with the parity signal 64 generated by the parity generation circuit 61.The timing signal and parity signal transmitted via the transmission line 66 are , a parity check circuit 62 checks whether an error has occurred during the transmission path. If one of the timing signals changes due to noise or the like, the parity check circuit 62 detects the above error and outputs a result signal 65 indicating malfunction. This result signal 65 is transmitted to a host system (not shown),
Prevents system malfunctions.

[Problems to be Solved by the Invention] However, the above-mentioned conventional technology can detect errors only when errors occur in the middle of the transmission path, and does not take into account errors in the timing generation circuit 60. In other words, there were the following problems. The timing signal generation circuit 60 sequentially outputs predetermined timing signals in response to a clock signal. However, if an unspecified timing signal is output due to noise or the like, the parity generation circuit 61 generates a correct parity signal 64 in response to this unspecified and erroneous timing signal. Therefore, the parity check circuit 6 located at the rear
2, no parity error occurs and the timing signal is determined to be correct. That is, the timing signal generation circuit 6
There was a problem that a malfunction of 0 cannot be detected.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide an error detection method and apparatus for detecting malfunctions of timing signal generating means. Another object of the present invention is to provide a timing signal generator capable of detecting errors.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a timing signal generating means that operates based on a clock signal and outputs a timing signal, and a timing signal generation means that outputs a timing signal based on the current state of the timing signal. A prediction circuit that predicts and outputs a prediction circuit compares the predicted value outputted by the prediction circuit with a timing signal corresponding to the step predicted by the predicted value outputted from the timing signal generation means, and determines whether there is a mismatch. To provide a timing signal generation device comprising: comparison means for determining that the timing signal generation device is malfunctioning when the timing signal generation device malfunctions. By using the fact that the waveform pattern of the timing signal to be output repeats at a certain period, the next step state is predicted based on the current state of a certain timing signal.
and. An error in which a malfunction in the signal generator is detected by comparing the timing signal actually output in the next step with the predicted value and determining that the timing signal generator is malfunctioning if they do not match. A detection method is provided.

Furthermore, the present invention provides a timing signal generating device that operates according to a clock signal and includes a timing signal generating means for outputting a timing signal, in which the waveform pattern of the timing signal outputted by the timing signal generating means repeats at a constant cycle. A prediction circuit is used to predict the state of the next step based on the current state of a timing signal, and the timing signal actually output in the next step is compared with the predicted value, and if there is a mismatch, the An error detection device for a timing signal generator is provided, which includes a comparison means for determining that the timing signal generation means is malfunctioning. The timing signal generating means includes, for example, a combinational circuit and a flip-flop circuit. A timing signal is output using a loop circuit consisting of a combinational circuit and a flip-flop circuit. The prediction circuit preferably includes, for example, a combinational circuit and a holding circuit, inputs the output of the timing signal generating means to the combinational circuit, inputs the output of the combinational circuit to the holding circuit, and inputs the output of the timing signal generating means to the holding circuit. The configuration may be such that the predicted value of the state of the step is output from the holding circuit.

The prediction circuit has a configuration in which, as a combinational circuit, a combinational circuit constituting the timing signal generation means is used in common, the output signal thereof is held in a holding circuit, and the state of the next step of the timing signal generation means is outputted from the holding circuit. It is also possible to do this.

The prediction circuit may be configured to predict a plurality of types of states of the next step of the timing signal generating means and selectively output predicted values from among these. In the error detection method of the present invention, if the timing signal actually output in the next step does not match the predicted value, it is determined that the timing signal generating device is malfunctioning, and the determination result of the malfunction is determined. It is preferable to output this to other devices receiving timing signals from the timing generator. Further, the timing signal generation device of the present invention or the error detection device used therein preferably includes a control circuit for controlling the supply of a clock signal to the timing signal generation means. The control circuit is configured to stop supplying the clock in response to the judgment result when it is judged that the timing signal generating device is malfunctioning.

Further, in the error detection method of the present invention, when it is determined that the timing signal generating device is malfunctioning,
Preferably, the operation of the timing signal generator is stopped.

The timing signal generation device of the present invention includes an information storage control device that controls data writing and reading operations using a timing signal supplied from the timing signal generation device;
For example, it can be preferably installed in a control device for a magnetic tape storage device, a control device for a magnetic disk storage device, a control device for an optical disk storage device, etc. Similarly, the present invention can be preferably installed in an information processing device whose operation is controlled by a timing signal supplied from a timing signal generator.

(Left below) [Operation] Every time a clock signal is input, the timing signal generation means outputs a timing signal that changes by one step. On the other hand, the prediction circuit predicts the next step state from the current state of the timing signal and outputs the signal.

The above two output signals are compared by a comparing means. When the timing signal generation means operates correctly and correctly outputs the timing signal for the next step based on the clock signal, the above two signals match and the comparison means outputs a signal without error. However, if an incorrect timing signal is output due to noise or the like, the two signals will not match, and the comparing means will output a signal indicating the mismatch, thereby detecting a malfunction of the timing signal generating means.

The clock signal of the timing signal generating means can be blocked. As a result, in the event of a malfunction, unnecessary timing signals will not continue to be output, and system malfunctions can be kept to a minimum.

Furthermore, by stopping the timing signal generation operation when an error occurs, the host system can know when the error occurs.

As described above, according to the present invention, a reliable timing signal generation device and its error detection method can be realized. [Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a timing signal generation device and an error detection method thereof according to the present invention.

In FIG. 1, 1 is a combinational circuit consisting of an AND circuit, an OR circuit, etc., and 2 is a flip-flop circuit, and these two constitute the timing signal generating means 3. 4 is a combinational circuit, 5 is a holding circuit, and these two constitute a prediction circuit 6. In addition, 7 is a comparison circuit consisting of a FOR circuit, etc., and 8
1 is a holding circuit, and 10 is an AND circuit, which constitute the comparison means 9.

Furthermore, 11 is a clock signal for the timing signal generating means 3, 12 is a clock signal for the holding circuit 5 which is a component of the prediction circuit 6, and 13 is a clock signal for the holding circuit 8 of the comparing means 9. 14 is a timing signal.

Further, FIG. 2 is a more specific circuit diagram of the timing signal generating means 3 and the prediction circuit 6. In Figure 2,
The combinational circuit 1 includes AND circuits 19 to 22 and an OR circuit 2.
3 and 24. Furthermore, the flip-flop circuit 2 includes JK flip-flop circuits 25 to 27.
Consisting of

The AND circuit 19 receives the -ζ output of the JK flip-flop circuit 25, the possible output of the JK flip-flop circuit 26, and the Q output of the JK flip-flop circuit 27, and performs an AND operation on them. The AND circuit 20 receives the Q output of the JK flip-flop circuit 25. The Q output of the JK flip-flop circuit 26 and the 100 output of the JK flip-flop circuit 27 are input, and their logical product is taken. The AND circuit 21 also outputs the Q output of the JK flip-flop circuit 25. The ゜ζ output of the JK flip-flop circuit 26 and the Q output of the JK flip-flop circuit 27 are input, and their logical product is calculated. AN
The D circuit 22 receives the output from the JK flip-flop circuit 25, the Q output from the JK flip-flop circuit 26, and the JK flip-flop circuit 25.
The Q output of the K flip-flop circuit 27 is input, and their AND is taken. The OR circuit 23 takes the logical sum of the outputs of the ANDs 19 and 20. Also, the OR circuit llI24 is the AND circuit 2
The outputs of 1 and 22 are logically summed.

The JK flip-flop circuit 25 inputs the output of the AND circuit 19 to the J terminal, and the output of the AND circuit 20 to the K terminal.
The output of the D circuit 21 is input to the J terminal, and the output of the AND circuit #t22 is input to the K terminal. The JK flip-flop circuit 27 connects the output of the OR circuit 23 to the J terminal. The output of the OR circuit 24 is input to the K terminal. Also. The Q outputs of the JK flip-flop circuits 25, 26 and 27 are output as timing signals 14a, 14b and 14c, respectively, and each Q and Q output is sent to the combinational circuit 4, respectively. The combinational circuit 4 includes the JK flip-flop circuit 25.
For each Q and hundred output of 26 and 27. An AND circuit 28 which calculates the AND of -ζ-, Q of 26 and Q of 27 of the JK flip-flop circuit 2s, an AND circuit 29 of the JK flip-flop circuit 25, and a Q of the JK flip-flop circuit 2S, It has an AND circuit 30 that performs a logical product of Q and 27.

Further, the combinational circuit 4 includes the AND circuits 28 and 29.
An OR circuit g31 which takes the logical sum of the outputs of the AND circuit 29
and an OR circuit 32 which takes the logical sum of the outputs of the
○R circuit 3 which takes the logical sum of the outputs of D circuits 30 and 28
0. The holding circuit 5 includes D flip-flop circuits 34, 35 and 36, and the outputs of the OR circuits 31, 32 and 33 are input to the corresponding D terminals. The operation of this embodiment will be explained below using FIGS. 1 to 3. During period T1, outputs 14a, 14b, and 14c of JK flip-flop circuits 25 to 27 are all at low level. As a result, the output of the AND circuit 19 becomes high level. The J terminals of JK flip-flops 25 and 27 become high level. Further, the output of the AND circuit 28 of the combinational circuit 4 also becomes high level, and the D terminals of the D flip-flop circuits 34 and 36 become high level. Therefore, when the clock signal 11 is inputted next time, the outputs 14a and 1 of the JK flip-flop circuits 25 and 27
4c is a high level. Furthermore, when the clock signal 12 is input, the outputs 17a and 17c of the D flip-flop circuits 34 and 36 become high level. The output 14 of the flip-flop circuit 2 and the output 17 of the holding circuit 5 are compared in the comparison circuit 7, and since both outputs 14 and 17 match as described above, the output 18 of the comparison circuit 7 is high. level.

The output 18 of the comparison circuit 7 is held by the clock signal 13 inputted through the AND circuit 10 and the holding circuit 8, and outputs a result signal 15 indicating a match to a higher-level system (not shown).

As described above, each time the clock signal 11 is input, the timing signal generator changes the timing from T1→T2→T3→T4→T1.
It continues to change. Next, a case where the timing signal generator malfunctions will be described.

During the period Tl', the JK flip-flop circuits 25 to 27
The outputs 14a, 14b, and 14c of .all are at low level. Therefore, as described above, the J terminals of the JK flip-flop circuits 25 and 27 are at a high level, and the D terminals of the D flip-flop circuits 34 and 36 are at a high level. Suppose that in this state, the clock signal 11 is input, and at T2', the JK flip-flop circuit 27 malfunctions and the output 14c does not become a high level but becomes a low level. On the other hand, the D flip-flop circuits 34 and 36 operate correctly due to the clock signal 12, and the outputs 17a and 17c become high level.

Both output signals 14 and 17 are compared by a comparison circuit 7. At T2', 14c and 17c do not match, so
The output 18 of the comparison circuit 7 becomes low level. The output 18 of this comparison circuit 7 is output to the holding circuit 8 by the clock signal 13.
stored and retained. The holding circuit 8 outputs a low-level result signal 15 indicating a mismatch to a host system (not shown). Further, since the result signal 15 is input to the AND circuit 10, the subsequent clock signal 13 is not input to the holding circuit 8, and the output 15 of the holding circuit 8 is held at a low level.

As described above, the output 14 of the timing signal generation means 3 is predicted by the prediction circuit 6, and the output 17 of the prediction circuit 6 and the output 14 of the timing signal generation means 3 are compared by the comparison means 9. Generating means 3
Malfunctions can be detected. FIG. 5 is a block diagram showing another embodiment of the timing signal generator and error detection method according to the present invention. The present embodiment is configured to include timing signal generation means 3, prediction circuit 6, and comparison means 9, similar to the embodiment shown in FIG.

The timing signal generating means 3 includes a combinational circuit 1 and a flip-flop circuit 2.

Further, the comparison means 9 includes the comparison circuit 7, the holding means 8 and the A
It is configured with an ND circuit 10. Both means 3 and 4 are constructed in the same manner as shown in FIG. 1 and operate in the same manner. The prediction circuit 6 is the same as the embodiment described above in that it includes a combinational circuit and a holding circuit. However, the pre-opening circuit 6 of this embodiment utilizes the combination circuit 1 of the timing signal generating means 3 as a combination circuit. That is, by holding the output of the combinational circuit 1 in the holding circuit 5, the output of the timing signal generating means 3 is predicted. Further, in the embodiment shown in FIG. 5, the flip-flop circuit 2 and the holding circuit 5 have the same configuration.

Note that the details of each component are almost the same as those shown in the corresponding FIG. 2.

As a result, the prediction circuit 6 operates in the same manner as the timing signal generating means, so that it is possible to predict the timing signal. Therefore, by comparing both signals using the comparing means 9, malfunction of the timing signal generating means 3 can be detected.

The embodiment shown in FIG.
This is yet another embodiment of a timing signal generation device and an error detection method thereof, which are configured using only memory.

In FIG. 6, 37 is a ROM, and the ROM 37 and the flip-flop circuit 2 constitute the timing signal generating means 3. 38 is a ROM, and the ROM 38 and the holding circuit 5 constitute a prediction circuit 6. The ROMs 37 and 38 contain, for example, timing signals 14a and 14 shown in FIG.
For each of b and 14c, the waveform pattern for each cycle of T1 to T4 is stored in correspondence with 91'' and "0". The waveform pattern data of each cycle is based on the timing signal of the previous cycle. The waveform pattern is stored as an address. In this embodiment, a timing signal is input to the address input terminal of the ROM 37, the output signal of the ROM 37 is input to the flip-flop circuit 2, and the timing signal for the next step is input by inputting the clock signal 11. Outputs 14.

On the other hand, the timing signal 14 is input to the address input terminal of the ROM 38, and the state of the timing signal for the next step is obtained from the ROM 38. The output signal of the ROM 38 is held in the holding circuit 5, and the prediction signal of the timing signal from the holding circuit 5 is compared with the timing signal 14 by the comparing means 9, thereby detecting malfunction of the timing signal generating means 3. be able to.

Note that in this embodiment and other later embodiments, the ROM
Preferably, PROM, EPROM, etc. can be used. Also. RAM may also be used. FIG. 7 shows still another embodiment of the timing signal generator and its error detection method.

In this embodiment, the ROM 37 and the flip-flop circuit 2
1, a prediction circuit 6 having a holding circuit 5 and a combinational circuit 4, and a comparison means 9.

The main difference between this embodiment and the embodiment shown in FIG. 1 is that a ROM 37 is used in place of the combinational circuit 1, and a prediction circuit 6 is used in which the order of the holding circuit 5 and the combinational circuit 4 is switched. .

The timing signal 14 of the current step is held by the holding circuit 5, and then the combinational circuit 4 predicts and outputs the timing signal of the next step. Timing signal 1 changed to the next step by this prediction signal and clock signal 11
A malfunction of the timing signal generating means 3 can be detected by comparing it with the timing signal generating means 4 using the comparing means 9.

FIG. 8 shows another embodiment of the timing signal generator and its error detection method. This embodiment has a timing signal generation means 3 and comparison means 9 configured similarly to those used in each of the embodiments described above, and a prediction circuit 6 having a configuration unique to this embodiment. be done.

The prediction circuit 6 includes two combinational circuits 40 and 41 and two holding circuits 42 and 4 connected correspondingly.
3, and a switching circuit 44 that switches and outputs the outputs of the holding circuits 42 and 43.

This embodiment operates as follows.

That is, the timing signal 14 output from the timing signal generating means 3 is transmitted to the two combinational circuits 40 and 41.
is input. In response to this, combinational circuits 42 and 4
3 outputs a prediction signal for the next step according to each combinational circuit design.

These predicted signals are held in corresponding holding circuits 42 and 43, respectively, and two types of predicted signals are obtained.

These two types of prediction signals are input to a switching circuit 44, and a switching signal 4 from a host system or another circuit (not shown) is input to the switching circuit 44.
5, one of the above two types is selected. A malfunction of the timing signal generating means 3 can be detected by comparing the selected predetermined signal and the timing signal 14 with the comparing means.

That is, according to this embodiment, in the first mode, the prediction signal obtained by the combinational circuit 40 and the holding circuit 42 is used, and in the second mode, the prediction signal obtained by the combinational circuit 41 and the holding circuit 43 is used. By comparing the timing signals 14, respectively, it is possible to detect a malfunction of the timing signal generating means 3 whose operation changes depending on the mode.

FIG. 9 shows another embodiment of the timing signal generator and its error detection method.

The embodiment shown in FIG. 9 is based on the embodiment shown in FIG. 1, and a control circuit 46 and a reset signal 47 are newly added thereto.

Similar to the embodiments described above, in this embodiment, when the timing signal generating means 3 malfunctions, the comparison means 9 continues to output a low-level result signal 15 indicating the malfunction. When this low level signal is output, the control circuit 46 operates so as not to input the clock signal 11 to the timing signal generating means 3. Therefore, after a malfunction occurs, the timing signal generating means 3 does not operate and stops in its current state.

According to this embodiment, the incorrect timing signal 14 does not continue to be output, and the range of malfunction of the system using the timing signal 14 can be kept to a minimum. Further, upon receiving a low-level result signal 15 informing that the host system has detected the above-mentioned error, and after completing countermeasures, a reset signal 47 is input to the holding circuit 8 of the comparing means 9 to return the reading output to a high level. , it is possible to operate the timing signal generating means 3 again.

The timing signal generation device of each embodiment described above can be used, for example, as a timing signal generation device of an information processing device. Specifically, the present invention is suitable as a device for generating timing that serves as a reference for the operation of a control device in a magnetic tape storage device (hereinafter abbreviated as MT control device), a magnetic or optical disk storage device, or the like. In addition to these, the present invention can also be applied to sequence control in which sequence operations are executed using timing signals. for example,
It can be used as a clock generator or a timing signal generator in a control device inside a computer, or in various control devices using a computer. FIG. 10 shows an embodiment in which the timing signal generating device of the present invention is applied to an MT control device.

In FIG. 10, 48 is a central processing unit (abbreviated as CPU) that controls the entire MT control device, 49 is a clock signal generation circuit, and 50 is a timing signal generation device of the present invention. 51 and 52 are bidirectional data buffers, 53 are data buffers that temporarily store data, and 54 are MT decommissioning devices 5.
This is an MT control circuit that controls 5.

The data stored in the MT is read by the MT operating device 55 and the MT control circuit 54 and written to the buffer memory 53 via the bidirectional buffer 51. Thereafter, the data is read out from the buffer memory 53 and sent to the host computer (not shown) via the bidirectional buffer 52.
Sent to. The series of movements described above are controlled by the CPU 48, but writing to and reading from the buffer memory 53, control of the direction of the bidirectional buffers 51 and 52, etc. are controlled by the timing signal generator 5o.

Furthermore, when the timing signal generator 50 malfunctions during writing or reading operations to the buffer memory 53,
This fact is transmitted to the CPU 48 by the result signal 15, and the M
Malfunctions of the entire T control device can be prevented.

FIG. 10 shows an example in which the timing signal generating device 50 is applied to an MT control device, but as mentioned above, it can also be applied to various control devices such as a disk control device, printer control device, and memory circuits such as a personal computer and a word processor. The timing signal generator of the present invention can be used in any location where a timing signal is required, such as a timing signal generator.

[Effects of the Invention] According to the present invention, when the timing signal generating means malfunctions due to noise etc., this error can be detected.
Incorrect processing can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a timing signal generating means and a prediction circuit used in the configuration of the embodiment,
3 is a timing chart showing waveforms of various parts of the embodiment shown in FIG. 1, FIG. 4 is a block diagram showing a timing signal generator according to the prior art, FIGS. 5, 6, 7,
8 and 9 are block diagrams showing other embodiments of the present invention, and FIG. 10 is a block diagram showing an embodiment in which the timing signal generating device of the present invention is applied to an MT control device. 3... Timing signal generation means, 4... Combination circuit, 5... Holding circuit, 6... Prediction circuit, 9... Comparison means, 14c +7c 10, 19, 20, 21, 22, 28 ,29.30
...AND circuit, 23, 24, 31, 32.3
3...OR circuit, 25,26,27...JK flip-flop circuit, 34,35,36...D flip-flop circuit.・3 timing signal generation means

Claims (1)

[Claims] 1. A timing signal generating means that operates based on a clock signal and outputs a timing signal, a prediction circuit that predicts and outputs the state of the next step based on the current state of the timing signal, and the prediction circuit that predicts and outputs the state of the next step based on the current state of the timing signal. Comparing the predicted value outputted by the circuit with a timing signal outputted from the timing signal generating means and corresponding to the step predicted by the predicted value,
1. A timing signal generation device comprising: comparison means for determining that the timing signal generation means is malfunctioning in the case of a mismatch. 2. An error detection method for detecting malfunctions in a timing signal generator that operates based on a clock signal and outputs a timing signal, the method using the method in which the waveform pattern of the timing signal output from the timing signal generator repeats at a constant period. The state of the next step is predicted based on the current state of a certain timing signal, and the timing signal actually output in the next step is compared with the predicted value, and if they do not match, the timing signal is changed. A method for detecting an error in a timing signal generator, the method comprising determining that the generator is malfunctioning. 3. An error detection device for detecting a malfunction in a timing signal generation device that operates according to a clock signal and includes a timing signal generation means for outputting a timing signal, wherein the waveform pattern of the timing signal outputted by the timing signal generation means is A prediction circuit that predicts the state of the next step based on the current state of a timing signal using repetition at a constant cycle, and a prediction circuit that compares the timing signal actually output in the next step with the predicted value. , and comparing means for determining that the timing signal generating means is malfunctioning in the case of a mismatch. 4. An error detection method for detecting a malfunction in a timing signal generating device that operates based on a clock signal and outputs a timing signal, the method comprising determining the state of the next step based on the current state of the timing signal output by the timing signal generating device. and compares the timing signal actually output in the next step with the predicted value, and if they do not match, it is determined that the timing signal generating device is malfunctioning, and the malfunction is determined. A method for detecting errors in a timing signal generator, the method comprising outputting a result to another device receiving timing signals from the timing generator. 5. A control circuit is provided for controlling the supply of a clock signal to the timing signal generation means, and when it is determined that the timing signal generation device is malfunctioning, the control circuit receives the determination result, and 4. The timing signal generation device according to claim 1, or the error detection device for a timing signal generation device according to claim 3, characterized in that the timing signal generation device is configured to stop supply of a clock. 6. The error detection method for a timing signal generating device according to claim 2 or 4, characterized in that when it is determined that the timing signal generating device is malfunctioning, the operation of the timing signal generating device is stopped. 7. The timing signal generation device according to claim 1 or 5, wherein the prediction circuit predicts a plurality of types of states of the next step of the timing signal generation means and outputs a predicted value selectively from among these. , claim 3 or 5
An error detection device for a timing signal generator as described above. 8. When predicting the state of the next step, a plurality of types of predictions are made and a predicted value selected from these is compared with a timing signal actually output in the next step. , 4 or 6. An error detection method for a timing signal generator according to . 9. An error detection method for detecting a malfunction in a timing signal generation device that operates based on a clock signal and outputs a timing signal, the method comprising The timing signal output due to the inactivity of the signal is compared with the state of the next step predicted based on the current state of a certain timing signal, and if the two do not match, it is determined that the timing signal generator is malfunctioning. 1. An error detection method for a timing signal generator, characterized by determining that. 10. An information storage control device comprising the timing signal generating device according to claim 1 or 5, and controlling data writing and reading operations by timing signals supplied from the timing signal generating device. 11. An information processing device comprising the timing signal generating device according to claim 1 or 5, and controlling operations by a timing signal supplied from the timing signal generating device.