JP2004199268A - Method for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance designing efficiency and reduce cost by reviewing a logic composing method and process procedures by applying an existing library. <P>SOLUTION: This method for designing semiconductor integrated circuit simultaneously uses a flip-flop without a scanning function for replacing a flip-flop with scanning function at scanning and a flip-flop without scanning function for not replacing a flip-flop without a scanning function at scanning, circuit composition in accordance with mutual connection condition of the flip-flops and composition (S24) of a logic circuit is executed in partial scan designing. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for designing a semiconductor integrated circuit that performs logic synthesis based on a source program designed and described in terms of function and designs a logic circuit having a scan test function.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as a semiconductor integrated circuit becomes larger in scale and becomes a synchronous circuit, a circuit design by logic synthesis using a function description and a scan design method are known as methods for automatically generating a test pattern. In circuit design by logic synthesis using a function description, a logic operation is described using a function description language, and a logic circuit is automatically generated by a logic synthesis tool.
[0003]
There is known a general scan design method and an improved scan design method as a test method capable of increasing the design efficiency and reducing the cost of the general scan design method (for example, see Patent Document 1).
A general scan design method will be described with reference to FIG.
First, logic synthesis is performed on a source program whose function is described, using a flip-flop circuit having no scan function (step S1). Next, a replacement operation with a flip-flop circuit having a scan function (hereinafter, referred to as scan insertion) is performed (step S2). Subsequently, test pattern automatic generation (ATPG) is performed on the circuit on which the scan insertion has been performed (step S3). Finally, a floor plan (Step S4) and arrangement / wiring (Step S5) are performed.
[0004]
Next, an improved scan design method will be described with reference to FIG.
First, in step S11, a flip-flop circuit library having a scan function dedicated to logic synthesis as shown in FIG. 4 (however, a scan switching signal and a scan input are fixed) is prepared. In step S12, logic synthesis is performed only by the flip-flop circuit having the scan function.
[0005]
In step S13, a layout tool is used to perform placement and wiring, clock tree synthesis is performed, and a floor plan is examined. Based on the result, in step S14, the scan chains are connected to complete the logic circuit. In step S15, a test pattern is automatically created by the ATPG tool.
In step S16, whether or not to perform full scan design is selected, and in the case of partial scan design instead of full scan design, the process proceeds to step S17. In step S17, a part of the shift register of the sequential connection that does not need to use the flip-flop circuit with the scan function in the normal operation mode is replaced with the flip-flop circuit without the scan function in the circuit of the full scan design. . Then, the test pattern designed by the full scan circuit is applied to the circuit designed by the partial scan.
[0006]
[Patent Document 1]
JP 2000-20560 A
[0007]
[Problems to be solved by the invention]
However, in the processing method shown in FIG. 13, even when it is desired to convert the shift register configuration into a partial scan, it is necessary to perform a full scan design once, which increases the design work cost.
Further, as a circuit diagram of the library, a “flip-flop circuit having a scan function exclusively for logic synthesis” as shown in FIG. 4 is separately required. This means that an intermediate gate-level circuit that is not used in an actual integrated circuit is prepared for exclusive use, and a normal flip-flop circuit, a flip-flop circuit having a scan function, and a dedicated circuit having a fixed scan function are provided. Is required at the minimum, and the work at the time of library creation and the library management become inconvenient.
[0008]
Further, the circuit information of the scan function unit must be provided as circuit information before the scan chain connection. For this reason, depending on the simulator, information of the scan function unit may be fetched, and in this case, there is a concern that the calculation speed may be affected or the storage capacity of the storage device may be increased.
In addition, since wiring information that is not intended by the designer at first is added, it is difficult to understand when directly looking at the circuit diagram, and the design efficiency is deteriorated.
[0009]
On the other hand, according to the scan design method shown in FIG. 12, since synthesis is performed by a flip-flop circuit without a scan function, a large timing error occurs when the flip-flop circuit with a scan function is replaced.
On the other hand, in the processing method shown in FIG. 13, in the case of the partial scan from the full scan design circuit, on the other hand, “the circuit part having the shift register configuration in the normal operation mode is extracted and this circuit part There is a high possibility that a difference occurs in the data propagation time between before and after the replacement by the operation of “replacement with a flip-flop circuit that has not been performed”.
[0010]
Therefore, in any case, the optimization work is required again, and the development cost is increased.
In the processing method shown in FIG. 13, the floor plan is created before the selection of the partial scan design or the full scan design, and is performed only for the full scan circuit. For this reason, a portion occupied by the area of the flip-flop circuit is different from the final state, and a floor plan that is optimal in terms of area and timing cannot be obtained. In a process with a small cell delay, such as a recent submicron process, there is a possibility that a large problem such as a skew error occurring after a clock tree is created may occur.
[0011]
In particular, in the case of "applying a test pattern designed by a full scan circuit to a circuit designed by a partial scan", the ATPG pattern generated by the full scan circuit rarely becomes usable. For this reason, there is a need to intentionally perform chain generation in advance so as to do so.
[0012]
When specifying the target of partial scan design with the tool that replaces the flip-flop circuit, since the original circuit does not have information for distinguishing the target, it is necessary to list all the targets with circuit-specific instance names etc. Requires a large storage capacity, and the possibility of occurrence of omission or mistake at the time of designation increases.
[0013]
Further, in the conventional method, when a library is created, in order to prevent a timing difference or the like from appearing after replacement, a large difference is not caused in the delay and the driving ability of the flip-flop circuit without the scan function. Therefore, even when the transistor size can be reduced, a library having a similar size is often created. Such a restriction on the method may be a restriction that hinders optimization of the original area and power consumption cost.
In view of the above, an object of the present invention is to provide a method of designing a semiconductor integrated circuit capable of improving design efficiency and reducing costs by reviewing a logic synthesis method and a processing procedure using an existing library. To provide.
[0014]
[Means for Solving the Problems]
In order to solve the above problems and achieve the object of the present invention, the inventions according to claims 1 to 5 are configured as follows.
That is, the invention according to claim 1 is a method for designing a semiconductor integrated circuit for designing a logic circuit using a logic synthesis tool for a source program for which a function description is designed, wherein a plurality of flip-flops are used in a library used at the time of synthesis. One of these is a flip-flop in which the flip-flop has a fixed terminal for either data input or output during synthesis, or both data input and output terminals are connected only to the data input / output terminal of another flip-flop. Using a library containing a plurality of flip-flops prepared so as to belong to a first group that is one and a second group that is a flip-flop connected to another logic gate or an external port. Circuit synthesis so as to satisfy at least the above connection conditions. The one in which the features.
[0015]
According to a second aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect, in the circuit synthesis, the flip-flop is configured to have one of a data input terminal and a data input terminal or a data input or output terminal at the time of synthesis. A group in which both output terminals are flip-flops connected only to the data input / output terminal of another flip-flop is defined as a flip-flop without scan function, and flip-flops connected to other logic gates or external ports are replaced with flip-flops with scan function. It is characterized in that a circuit synthesis is performed as a flip-flop in which the timing, area, and input / output drive information corresponding to the later are set.
[0016]
According to a third aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the second aspect, the flip-flop without the scan function and the flip-flop in which timing information is set after replacement with the flip-flop with the scan function are set. When creating a floor plan based on the result of the circuit synthesis composed of the above, the cell layout information corresponding to the circuit assumed to be replaced with the flip-flop is also obtained by using the layout data corresponding to the flip-flop with the scan function after the replacement. It is characterized in that a floor plan is designed using a layout tool.
[0017]
According to a fourth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect, when the flip-flop is replaced with a flip-flop with a scan function for a scan test to form a scan chain, at the time of the circuit synthesis. Flip-flops whose data input or output are set to different groups or whose data input / output terminals are connected only to the data input / output terminals of another flip-flop are excluded from replacement. The flip-flop connected to a logic gate or an external port is replaced with a replacement target.
[0018]
According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit design method for performing logic synthesis based on a source program for which a function description is designed and designing a logic circuit having a scan test function, the first method having a scan function. And a second flip-flop that is replaced with a flip-flop with a scan function during scanning and does not have a scan function, and has a scan function without being replaced with a flip-flop with a scan function during scan processing A third step of preparing a cell library including a third flip-flop that does not have a logic circuit, and in the case of partial scan design, a logic based on the source program using both the second and third flip-flops A second step of creating a logic circuit by performing synthesis; A third step of performing a floor plan process based on the selected logic circuit, and replacing the second flip-flop with the first flip-flop based on the result of the floor plan process, connecting a scan chain, and A fourth step of scanning the circuit; and a fifth step of designing a test pattern for the logic circuit to which the scan chain is connected. In the second step, the partial scan is designed. When the normal data input terminal of any flip-flop is connected to the normal data output terminal of another flip-flop, the normal data output terminal of any flip-flop is connected to the normal data input terminal of another flip-flop. If the normal data input / output terminal of any flip-flop is different from other When the flip-flop is connected to the normal data input / output terminal, the optional flip-flop selects the third flip-flop. When the connection of the optional flip-flop is other than the above, the optional flip-flop is not selected. The second flip-flop is selected.
[0019]
According to the present invention having such a configuration, when designing a partial scan test circuit in a component of a shift register, flip-flops of different groups (names) are arranged according to connection conditions, thereby achieving full scan design. Scan design can be performed directly without taking the above steps. For this reason, it is not necessary to have a full scan data circuit as intermediate data, and the work at the time of library creation and library management costs are reduced.
[0020]
In addition, the absence of intermediate data can reduce the load and investment cost on simulators and storage devices that handle the data, and the composite circuit diagram is a circuit intended by the designer without extra additional wiring. Therefore, the design data can be easily verified, which leads to shortening of the development process.
Further, in the present invention, the timing damage due to replacement during generation of the partial scan circuit is suppressed by setting the parameters of the flip-flop with the scan function in advance for the flip-flop designated as the scan chain target cell. Repetition of the development process such as adjustment can be reduced.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a method for designing a semiconductor integrated circuit of the present invention will be described with reference to the drawings.
FIG. 1 is a flowchart showing the procedure of the method for designing a semiconductor integrated circuit according to this embodiment.
[0022]
FIG. 2 shows a symbol of the flip-flop without scan function 1 used in the method of designing a semiconductor integrated circuit according to this embodiment, and FIG. 3 shows a symbol of the flip-flop with scan function 5 used therefor.
The flip-flop 1 with a scan function has a data input terminal 2, a data output terminal 3, and a clock input terminal 4. In the synthesis library, a name or a number that can be managed as an ASIC component cell is given as a cell name, and this is configured. It is used as a library (hereinafter, referred to as a cell library) together with the circuit diagram of the gate structure.
[0023]
In addition, for the cell, apart from the gate level circuit diagram, a library (hereinafter, technology library) that describes the technology such as layout area, input / output timing characteristics, and input / output driver capability characteristics corresponding to this cell is used. I do.
As shown in FIG. 3, the flip-flop 5 with a scan function selects the data input terminal 6, the data output terminal 7, the clock input terminal 8, the scan input terminal 9, and the data input terminal 6 or the scan input terminal 9. It has a scan switching control signal terminal 10.
[0024]
Next, the procedure of the design method will be described with reference to FIG.
First, in step S21, a plurality of flip-flops are prepared as a cell library. That is, in addition to the flip-flop without the scan function, a flip-flop in which input / output timing characteristics and the like corresponding to replacement with the flip-flop with the scan function are prepared.
[0025]
For example, a flip-flop named “FFA” as a cell name and a flip-flop named “FFB” as a cell name are prepared. In this example, at the time of scanning in step S26 to be described later, a target to be replaced with a flip-flop with a scan function is collectively designated by a flip-flop name. Therefore, the flip-flop designated for replacement is a flip-flop in which input / output timing characteristics, layout area, and input / output drive capability characteristics corresponding to the flip-flop with the scan function beforehand are set in the technology library.
[0026]
In the example of FIG. 6, the values of the technology library for the flip-flops 31 and 32 having the cell name “FFB” are as usual. In the flip-flop having the cell name "FFA", the output 20 of the flip-flop 17 with the scan function is connected to its own scan input terminal as shown in FIG. 5, and the switching signal 21 is fixed so that the scan path is not switched. The characteristics are extracted and replaced with the technology library parameters of the layout area, input / output timing characteristics, and input / output driver capability characteristics.
[0027]
Instead of replacing only the technology library, the circuit itself may use a flip-flop with a scan test function as shown in FIG.
Here, considering the minimum configuration of the library, the cell library prepares the following for flip-flops.
That is, as the cell library, only a flip-flop without a scan test function (see FIG. 2) that differs only in the cell name and a flip-flop with a scan function (see FIG. 3) that is replaced when scanning is performed.
[0028]
The technology library to be set for this includes a parameter whose characteristics are extracted in a state of a normal flip-flop without a scan function (see FIG. 2) and a parameter whose characteristics are extracted in a state equivalent to a flip-flop with a scan function after replacement. Three parameters are prepared: a layout area, input / output timing characteristics, and input / output driver capability characteristics) and parameters obtained by extracting characteristics in the state of a flip-flop with a scan function (see FIG. 3).
[0029]
In step S22, either full scan design or partial scan design is selected. When the full scan design is selected due to the ATPG tool or the like, the process proceeds to step S23, and when the partial scan design is selected, the process proceeds to step S24.
In step S23, only the flip-flop that replaces the flip-flop with the scan function at the time of scanning, which will be described later, is used, and the logic circuit is formed by performing logical synthesis based on the source program for which the function description is designed. create.
[0030]
In this case, it is sufficient to simply remove or disable the normal flip-flops that are not replaced from the synthesis library, and only flip-flops that have the input / output timing characteristics of the flip-flops with a scan function corresponding to the replacement are set. Is logically synthesized.
In step S24, in order to implement the partial scan design, logic synthesis is performed based on the source program for which the function description is designed, and a logic circuit is created.
[0031]
That is, a flip-flop without a scan function that replaces a flip-flop with a scan function during scanning, and a scan test function that does not replace a flip-flop with a scan function during scanning, based on a source program designed and described in terms of function. Using the flip-flops without, logic synthesis is performed according to the definition of the connection conditions of the flip-flops to create a logic circuit.
[0032]
FIG. 6 shows an example of the connection state of the flip-flops of the circuit thus logically synthesized. In this example, at the time of logic synthesis, different flip-flops are adapted depending on whether the data input terminal of any flip-flop constituting the shift register is connected only to the data input / output terminal of another flip-flop. .
That is, in FIG. 6, the data input terminal of the flip-flop 31 is connected to the combinational circuit 30 other than the flip-flop, and the cell name is “FFA”. In addition, since each data input terminal of the flip-flops 32 and 33 is connected to a data input / output terminal of another flip-flop, “FFB” having a cell name different from “FFA” is assigned at the time of logic synthesis.
[0033]
Here, as will be described later, when replacing flip-flops with a scan function as a test design, removing the sequentially connected flip-flops from the replacement targets so as not to increase the layout area increases design efficiency and costs. It is very important for reduction. In this example, as shown in FIG. 7, a flip-flop having a cell name of “FFA” is referred to as a flip-flop having a scan function, and a flip-flop having a cell name of “FFB” is referred to as a flip-flop without a normal scan function. Simply specify them collectively by cell name or group name.
[0034]
At the time of step S24, the cell designated for replacement is a flip-flop in which the timing, layout area, and input / output drive characteristics corresponding to after replacement by the flip-flop with the scan function are set in the technology library in advance. For this reason, logic synthesis is performed in an actual circuit delay state in which flip-flops with a scan function and flip-flops without a scan function coexist.
[0035]
In step S25, a floor plan is examined by a layout tool based on the circuit information generated by the logic synthesis as described above.
Here, by optimizing the layout area, optimizing the wiring, and designing the clock tree by setting what is needed for the floor plan based on the cell layout information assuming replacement of the flip-flop with scan function It is implemented assuming a proper arrangement.
[0036]
In step S26, the scan target of the flip-flop is designated by a cell name (or a group name which is a set of target cells), and is replaced with a flip-flop with a scan function together with floor plan information to connect a scan chain.
By such processing, the circuit diagram of FIG. 6 is replaced with a circuit diagram as shown in FIG. That is, the cell having the cell name "FFA" shown in FIG. 6 is replaced with the flip-flop 35 having the scan function having the cell name "FFAS" as shown in FIG. Is done.
[0037]
In step S27, a test pattern is generated by the automatic test pattern generation tool (ATPG) for the final circuit for which the scan test has become possible.
Here, in the case of the ATPG that can handle only the full scan, since only the library for the full scan is used in step S23, a different flow (procedure) and adjustment are not particularly required.
[0038]
In the last step S28, the layout arrangement and wiring are completed, the layout design is verified, and the semiconductor integrated circuit is completed.
As described above, according to this embodiment, when a partial scan test circuit is designed in a component of a shift register, a flip-flop having a different cell name is arranged according to connection conditions, thereby achieving a full scan design. Scan chains can be designed directly without taking steps. For this reason, it is not necessary to have a full scan data circuit as intermediate data, and the work at the time of library creation and the library management cost are reduced.
[0039]
In addition, the absence of intermediate data can reduce the load and investment cost on simulators and storage devices that handle the data, and the composite circuit diagram is a circuit intended by the designer without extra additional wiring. Therefore, the design data can be easily verified, which leads to shortening of the development process.
Also, both the flip-flop without scan function and the flip-flop with scan function in the final circuit use the one that assumes the circuit that is the final form as a technology file from the synthesis stage, so that it can be replaced when generating the conventional partial scan circuit. Since timing damage is suppressed, repetition of development processes such as timing adjustment can be reduced.
[0040]
Also, in this embodiment, unlike the case where the floor plan is created only by the full scan circuit, the floor plan is created in advance using the layout information of the cell to be replaced with the scan function, so that the flip-flop with the scan function can be used. This is performed in a state where flip-flops without a scan function are mixed. Therefore, it is possible to create an optimized floor plan layout in which the accuracy and timing of the clock tree are accurate and the area is small.
[0041]
In particular, in this embodiment, the pattern created by the ATPG is created based on the final test circuit. Is not advantageous.
Further, according to this embodiment, when the target is specified by the replacement tool, the specification can be easily performed by the cell name (group name). For this reason, the omission of designation or mistake of the target circuit hardly occurs, which is effective for improving the quality circuit and shortening the development period. Also, there is almost no load on the storage device as compared with the case where all the target circuits (such as instant names) are stored.
[0042]
Further, according to this embodiment, since a flip-flop having a shift register configuration can be scheduled in advance at the stage of logic synthesis, it is possible to prepare and adapt a dedicated flip-flop having a small size and low current consumption. It is possible to construct a library in consideration of the layout area and power consumption cost, which can contribute to optimization during logic synthesis and cost reduction.
[0043]
Next, two other application examples of this embodiment will be described with reference to FIGS.
FIG. 8 shows that a flip-flop that is not to be replaced at the time of logic synthesis has a circuit obtained by logic synthesis when its data output terminal is defined as being connected to the data input terminal of another flip-flop. The results are shown.
[0044]
In this example, since the data output terminals of the flip-flops 40 and 41 are connected to other flip-flops, the cell name is "FFB", and the flip-flop 42 has a data output terminal whose final output 44 such as its scan output is external. Is logically synthesized such that the cell name becomes “FFA” different from “FFB”.
Although the data input terminal of the flip-flop 40 is connected to the combinational circuit 43, since the connection condition is checked based on the data output terminal of the flip-flop according to the above definition, the cells of the same group as the flip-flop 41 It has become. When this is scanned, the flip-flop 42 whose cell name is “FFA” shown in FIG. 8 is replaced with a flip-flop 45 with a scan function whose cell name is “FFAS” as shown in FIG. The scan chain 46 and the scan switching signal 47 are wired to enable a scan test.
[0045]
FIG. 10 shows that a flip-flop that is not to be replaced at the time of logic synthesis is obtained by logic synthesis when it is defined that both data input / output terminals are connected to data input / output terminals of another flip-flop. FIG.
In this example, since the data input terminal of the flip-flop 61 is connected to another logic circuit 60, the cell name is “FFA”, and the data output terminal of the flip-flop 63 is connected to another logic circuit 64, so that the cell name is “FFA”. Since both the data input / output terminals of the “FFA” and the flip-flop 62 are connected to another flip-flop, the logic synthesis is performed so that the cell name becomes “FFB”.
[0046]
When this is scanned, the flip-flops 61 and 63 having the cell name “FFA” shown in FIG. 10 are connected to the flip-flops 66 and 67 having the scan function having the cell name “FFAS” as shown in FIG. In place, scan test becomes possible.
This is a definition in a case where it is convenient for all the flip-flops connected to the combinational circuit to be flip-flops with a scan function depending on the ATPG tool.
[0047]
【The invention's effect】
As described above, according to the present invention, when a partial scan test circuit is designed in a constituent part of a shift register, different flip-flops of a technology file are arranged according to connection conditions, thereby achieving a step of full scan design. Scan design can be performed directly without stepping on. For this reason, it is not necessary to have a full scan data circuit as intermediate data, and the work at the time of library creation and the library management cost are reduced.
[0048]
In addition, the absence of intermediate data can reduce the load and investment cost on simulators and storage devices that handle the data, and the composite circuit diagram is a circuit intended by the designer without extra additional wiring. Therefore, the design data can be easily verified, and the development process can be shortened.
Furthermore, in the present invention, both the flip-flop without scan function and the flip-flop with scan function in the final circuit use a circuit which assumes a circuit which is a final form as a technology file from a synthesis stage, thereby achieving a conventional partial scan circuit. Since timing damage due to replacement during generation is suppressed, repetition of development processes such as timing adjustment can be reduced.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating a procedure of a design method according to an embodiment of a semiconductor integrated circuit of the present invention.
FIG. 2 is a diagram showing symbols of flip-flops without a scan function used in this design method.
FIG. 3 is a diagram showing symbols of flip-flops with a scan function used in this design method.
FIG. 4 is a connection diagram of a flip-flop used by a conventional general scan design method.
FIG. 5 is a circuit diagram when a flip-flop with a scan function is functionally used as a flip-flop without a scan function.
FIG. 6 is a diagram showing a connection state of a flip-flop of a circuit logically synthesized by this design method.
FIG. 7 is a diagram showing a state where the flip-flops of the circuit of FIG. 6 are replaced and scan chains are connected.
FIG. 8 is a diagram illustrating a connection state of a flip-flop of a circuit that is logically synthesized at the time when the definition of the connection condition of the flip-flop is changed.
FIG. 9 is a diagram showing a state where the flip-flops of the circuit of FIG. 8 are replaced and scan chains are connected.
FIG. 10 is a diagram showing the connection states of the flip-flops of the logic-synthesized circuit when the definition of the connection conditions of the flip-flops is further changed.
11 is a diagram showing a state where the flip-flops of the circuit of FIG. 10 are replaced and scan chains are connected.
FIG. 12 is a flowchart showing a procedure of a conventional general scan design method.
FIG. 13 is a flowchart showing a procedure of a scan design method improved as a test method capable of improving design efficiency and reducing costs of a conventional general scan design method.
[Explanation of symbols]
1, 31, 32, 33 Flip-flop without scan function
5,35 flip-flop with scan function
2, 6 Normal data input terminal
3, 7 Normal data output terminal
4, 8 clock terminals
9 Scan data input terminal
10 Scan mode switching terminal
30 Combination circuit

Claims (5)

A method for designing a semiconductor integrated circuit, wherein a logic circuit is designed using a logic synthesis tool for a source program designed for function description,
Prepare multiple flip-flops in the library used during synthesis,
One of these is that the flip-flop is a flip-flop in which either the data input or the output terminal is determined at the time of synthesis, or both the data input and output terminals are connected only to the data input / output terminal of another flip-flop. One group and the other belonging to a second group of flip-flops that also connect to other logic gates or external ports,
A method for designing a semiconductor integrated circuit, comprising: performing circuit synthesis so as to satisfy at least the connection condition by using the prepared library including a plurality of flip-flops. In the circuit synthesis,
Flip-flops without scanning function are defined as a group of flip-flops in which either data input or output is determined at the time of synthesis, or flip-flops in which both data input / output terminals are connected only to data input / output terminals of another flip-flop. And
2. The circuit according to claim 1, wherein the flip-flop connected to the other logic gate or the external port is replaced with a flip-flop with a scan function, and the circuit is converted into a flip-flop in which the timing, area, and input / output drive information are set. The method for designing a semiconductor integrated circuit according to the above. When creating a floor plan based on the result of circuit synthesis composed of the flip-flop without scan function and a flip-flop in which timing information is set assuming that the flip-flop with scan function has been replaced, 3. The semiconductor integrated circuit according to claim 2, wherein information on a cell layout corresponding to the circuit assumed to be replaced is also subjected to floor plan design by a layout tool using the layout data corresponding to the flip-flop with the scan function. Design method. When replacing flip-flops with flip-flops with scan function for scan test and forming scan chains,
At the time of the circuit synthesis, a predetermined terminal of either data input or output set in a different group, or a flip-flop in which both data input and output terminals are connected only to the data input / output terminal of another flip-flop 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein the replacement is performed with a flip-flop connected to another logic gate or an external port as a replacement target. Functional description A logic synthesis is performed based on a designed source program, and in a semiconductor integrated circuit design method of designing a logic circuit having a scan test function,
A first flip-flop having a scan function, a second flip-flop that has been replaced with a flip-flop with a scan function at the time of scanning and has no scan function, and has been replaced with a flip-flop with a scan function at the time of scanning. First step of preparing a cell library including a third flip-flop not having a scan function;
A second step of performing logic synthesis based on the source program using both the second and third flip-flops to create a logic circuit in the case of partial scan design;
A third step of performing floor plan processing based on the logic circuit created by the logic synthesis;
A fourth step of replacing the second flip-flop with the first flip-flop based on a result of the floor plan processing and connecting a scan chain to scan the logic circuit;
A fifth step of designing a test pattern for the logic circuit to which the scan chain is connected,
In the partial scan design in the second step,
When the normal data input terminal of any flip-flop is connected to the normal data output terminal of another flip-flop, the normal data output terminal of any flip-flop is connected to the normal data input terminal of another flip-flop Or if the normal data input / output terminal of any flip-flop is connected to the normal data input / output terminal of another different flip-flop, the arbitrary flip-flop selects the third flip-flop;
The method of designing a semiconductor integrated circuit, wherein when the connection of an arbitrary flip-flop is other than the above, the arbitrary flip-flop selects the second flip-flop.

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