JP4223319B2 - Semiconductor integrated circuit and test generation program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a test generation program for easily testing a semiconductor integrated circuit having a built-in embedded core.
[0002]
[Prior art]
In recent years, due to improvements in multilayer wiring technology and miniaturization technology in semiconductor manufacturing, a single system can be realized by mounting functional cores such as a microprocessor, DSP, analog circuit, and memory on one chip of a semiconductor integrated circuit. Yes. On the other hand, since the scale of a single-chip mounting gate has increased, a method for testing a semiconductor integrated circuit after manufacture has become a problem.
[0003]
Usually, when testing a semiconductor integrated circuit, a custom logic unit designed using a logic circuit such as an AND circuit, an OR circuit, a flip-flop, a microprocessor, a DSP (Digital Signal Processor), an analog circuit A test method different from that for a functional core such as a memory is used.
[0004]
The test of the custom logic part uses a scan path test method in order to obtain a high failure detection rate. The logic circuit of the custom logic unit is generally composed of a sequential circuit such as a flip-flop and a combinational circuit such as an AND circuit and an OA circuit. In the scan path test method, the logic circuit of the custom logic section is divided into two circuits, a sequential circuit and a combinational circuit.
[0005]
Specifically, all or part of the custom logic unit is replaced with a scan flip-flop with a selector, or a selector is inserted in front of the flip-flop. These flip-flops are connected in a chain to form a shift register (scan chain). During the test, the test pattern of the combinational circuit is serially input to this shift register, and the test pattern is set in the flip-flop by the shift operation. Then, the normal operation is performed for one clock, the combinational circuit is operated, and the operation result of the combinational circuit is latched in the flip-flop. Again, the output result of the combinational circuit operated by the test pattern set by the shift operation is output to the external terminal. This output is compared with an expected value prepared in advance. By repeating these operations, you can simply add an input terminal that specifies the test operation or normal operation, a test pattern input terminal that inputs the test pattern serially, and an output terminal that outputs the test result. Test can be done.
[0006]
In a scan path test circuit, the construction of a scan path circuit and generation of a test vector can be automatically performed by an EDA (Electronic Design Automation) tool. As a result, the circuit designer can concentrate on circuit design for realizing normal system operation, and can greatly reduce the effort for designing a test circuit and a test pattern.
[0007]
A procedure for converting a general synchronous design logic circuit having no scan path circuit into a scan path circuit will be described. First, a selector is inserted before each flip-flop of the custom logic unit. Connects to the select terminal of each selector and an external terminal for inputting a test mode switching signal. The input of the selector selected when the test mode switching signal is a signal indicating the test mode is connected to an input terminal for inputting a test pattern and a terminal of another flip-flop. The signal input to the flip-flop before the selector is inserted is connected to the input of the selector that is selected when the test mode switching signal is a signal indicating the normal mode. Then, the output of the flip-flop as the final stage is connected to the external terminal. As a result, a scan chain can be configured.
[0008]
In the scan path circuit, a scan flip-flop, which is a functional cell in which a selector and a flip-flop are integrated, is generally used. A conversion procedure in this case will be described. First, each flip-flop of the custom logic unit is replaced with a scan flip-flop. Subsequently, a test mode switching signal is connected to a selection terminal of all scan flips. The selector selected when the test mode switching signal is a signal indicating the test mode includes an input terminal for inputting a test pattern and a terminal of another scan flip-flop, and the test mode switching signal indicates the normal mode. The signal input to the flip-flop before the replacement with the scan flip-flop is connected to the input of the selector selected in the case of a signal. Then, the output of the scan flip-flop as the final stage is connected to the external terminal. In this way, the conversion to the scan path circuit is completed by connecting the paths by the output of the scan flip-flops so as to have a chain structure.
[0009]
Next, a conventional technique for efficiently testing an embedded core having one or a plurality of functional cores will be described. A conventional semiconductor integrated circuit includes a test mode matrix composed of a plurality of multiplexers, an embedded core, a custom logic unit, and an I / O circuit having an interface between the external terminal of the semiconductor integrated circuit and the custom logic unit. I have. The test mode matrix is composed of a plurality of multiplexers, and interconnects the embedded core, the custom logic unit, and the I / O circuit. By connecting the I / O circuit to an external tester, standard test vectors are used for embedded core testing and normal circuit operation. The test mode matrix performs connection between the embedded core and the custom logic unit based on a specific mode selected by a control signal transmitted from an external terminal via an I / O circuit (for example, , See Patent Document 1).
[0010]
Another semiconductor integrated circuit has two modes for testing a plurality of functional cores. The first mode is associated with a respective core test control block (TCB) for each core to control each of these cores to the test mode, and each core has a core shift register for holding test control data. The functional cores are linked in series in the chain, and each functional core shifts test control data along the chain. The second mode provides test control data to the associated core. A system TCB is provided in the chain, and the output terminal of the system TCB is connected to each functional core. When the system TCB receives a specific test control data set, a system test hold signal is supplied to the functional core, and the functional core Is switched to either the first mode or the second mode (see, for example, Patent Document 2).
[0011]
[Patent Document 1]
JP 09-0454705 A
[Patent Document 2]
Japanese Patent Application Laid-Open No. 11-525783
[0012]
[Problems to be solved by the invention]
In the former prior art, a test mode matrix connects a buried core and a custom logic unit based on a control signal input via an I / O circuit to perform a test, thereby completing a complete tester for a semiconductor integrated circuit. Maintainability.
[0013]
In addition, the latter prior art architecture does not require a complex state machine of functional cores according to the boundary scan test standard for supplying test control data to each functional core, and various functional cores and systems. The number of interconnections between the two can be reduced.
[0014]
However, in both conventional technologies, the custom logic unit and the embedded core in the semiconductor integrated circuit must be tested separately. Therefore, there has been a problem that the custom logic unit and the embedded core must each have a dedicated test terminal and a test circuit. That is, there are problems that the number of dedicated test terminals increases for testing the semiconductor integrated circuit, and that the test time increases due to the increase in the length of the test vector.
[0015]
In addition, a test circuit for directly accessing the input / output terminals of the functional core from the outside of the semiconductor integrated circuit is provided. I / O terminals are required. As a result, when the number of input / output terminals of the semiconductor integrated circuit is small and a plurality of cores are incorporated, there is a problem that the test circuit and its control method are complicated and the circuit scale is increased.
[0016]
The present invention has been made in view of the above, and in a semiconductor integrated circuit having a custom logic portion and an embedded core, a semiconductor integrated circuit and a test generation for efficiently testing the embedded core by separating the custom logic portion and the embedded core portion The purpose is to obtain a program.
[0017]
[Means for Solving the Problems]
To achieve the above object, a semiconductor integrated circuit according to the present invention includes a custom logic having an embedded core having one or a plurality of functional cores, and a scan path circuit in which a combinational circuit and a plurality of scan flip-flops are chain-connected. In a semiconductor integrated circuit comprising: an input register connected to each input terminal of the embedded core, and connected to each output terminal of the embedded core, between the custom logic unit and the embedded core Output registers, and during the embedded core test operation, each of the input registers and each of the output registers is connected in a chain to form a scan path, and the embedded cores that are serially input Before setting the test pattern to each input register by shift operation When the gate signal for outputting the embedded core test pattern to the embedded core is asserted, the embedded core is operated with the embedded core test pattern set in each input register, and the output is output to each output register. And a test shift register that latches and outputs the output of the latched embedded core to an external terminal and a first stage scan flip-flop of the scan path circuit by a shift operation when the gate signal is negated. .
[0018]
According to the present invention, the semiconductor integrated circuit is connected between the custom logic unit and the embedded core, each of the input registers connected to the input terminal of the embedded core and the output terminal of the embedded core when testing the embedded core. The test pattern of the embedded core that is serially input by being chain-connected to each output register to be set is set in each input register by a shift operation. When the gate signal for outputting the set test pattern of the embedded core to the embedded core is asserted, the embedded core is operated with the test pattern of the embedded core set in each input register, and the output is used for each output. When latched in a register and the gate signal is negated, the output of the latched embedded core is output to an external terminal by a shift operation.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a semiconductor integrated circuit and a test generation program according to the present invention will be explained below in detail with reference to the accompanying drawings.
[0020]
Embodiment 1 FIG.
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit 1 according to the first embodiment of the present invention. The semiconductor integrated circuit 1 according to the first embodiment of the present invention includes an embedded core 11, a custom logic unit 12, and a test shift register 13.
[0021]
The embedded core 11 includes functional cores such as a microprocessor, a DSP, an analog circuit, and a memory.
[0022]
As shown in FIG. 2, the custom logic unit 12 includes a combinational circuit 121 such as an AND circuit and an OR circuit, and a scan path circuit 122 in which flip-flops are chain-connected.
[0023]
The scan path circuit 122 includes a plurality of (in this case, three) flip-flops 1221 to 1223 and multiplexers 1224 to 1226 connected to the input terminals D of the flip-flops 1221 to 1223.
[0024]
The multiplexer 1224 outputs the scan-out CSO that is the output of the test shift register 13 when the scan enable signal SE is asserted (in this case “1”), and when the scan enable signal SE is negated (in this case “0”). The output of the combinational circuit 121 is selected and output to the flip-flop 1221. The flip-flop 1221 latches the output of the multiplexer 1224 at the rising edge of the clock CLK and outputs it to the combinational circuit 121 and the multiplexer 1225. The multiplexer 1225 selects the output of the flip-flop 1221 when the scan enable signal SE is “1”, and selects the output of the combinational circuit 121 when the scan enable signal SE is “0”, and outputs the selected output to the flip-flop 1222. The flip-flop 1222 latches the output of the multiplexer 1225 at the rising edge of the clock CLK and outputs it to the combinational circuit 121 and the multiplexer 1226. The multiplexer 1226 selects the output of the flip-flop 1222 when the scan enable signal SE is “1” and the output of the combinational circuit 121 when the scan enable signal SE is “0”, and outputs the selected output to the flip-flop 1223. The flip-flop 1223 latches the output of the multiplexer 1226 at the rising edge of the clock CLK. Then, the scan-out SO that is the output of the scan path circuit 122 is output to the combinational circuit 121 and the external terminal of the semiconductor integrated circuit 1.
[0025]
The test shift register 13 controls the input / output signals of the embedded core 11 based on the scan enable signal SE, the test enable signal TE, and the gate signal Gate input from the external terminals of the semiconductor integrated circuit 1, and the semiconductor integrated circuit 1. The serial input signal SI input from the external terminal is input to the embedded core 11 and the output of the embedded core 11 operated by the serial input signal SI is latched. Then, the latched output of the embedded core 11 is output serially. The serial output scan-out CSO is output to the external terminal of the semiconductor integrated circuit 1 and the scan path circuit 122.
[0026]
FIG. 3 is a block diagram showing the configuration of the test shift register 13. The test shift register 13 includes input registers 131 to 134 connected to the input terminals of the embedded core 11 and output registers 135 and 136 connected to the output terminals of the embedded core 11. The input registers 131 to 134 have the same function. The output registers 135 and 136 have the same function.
[0027]
The input registers 131 to 134 control signals input to the embedded core 11 based on the scan enable signal SE, the test enable signal TE, and the gate signal Gate. The output registers 135 and 136 control the output of the embedded core 11 based on the scan enable signal SE and the test enable signal TE. The input registers 131 to 134 and the output registers 135 and 136 are chain-connected in the order of the input registers 131 and 132, the output registers 135 and 136, and the input registers 133 and 134 based on the scan enable signal SE. To constitute a shift register circuit. The input registers 131 to 134 and the output registers 135 and 136 may have a well-known boundary scan cell configuration as defined in the IEEE (Institute of Electrical and Electronics Engineers) standard 1149.1.
[0028]
FIG. 4 is a circuit diagram showing an example of the input register 131. The input register 131 includes a flip-flop 1311, a gate circuit 1312, and multiplexers 1313 and 1314.
[0029]
The multiplexer 1313 selects the serial input signal SI when the scan enable signal SE is “1”, and selects the signal input from the custom logic unit 12 when the scan enable signal SE is “0”, and outputs the selected signal to the flip-flop 1311. The flip-flop 1311 latches the output of the multiplexer 1313 at the rising edge of the clock CLK, and outputs it to the gate circuit 1312 and the input register or output register in the subsequent stage. The gate circuit 1312 passes through the output of the flip-flop 1311 when the gate signal Gate is “1”, latches the output of the flip-flop 1311 when the gate signal Gate is “0”, and outputs the latch 1314 to the multiplexer 1314. The multiplexer 1314 outputs the output of the gate circuit 1312 when the test enable signal TE is asserted (in this case “1”), and outputs the output of the custom logic unit 12 when the test enable signal TE is negated (in this case “0”). Select and output to the embedded core 11.
[0030]
FIG. 5 is a circuit diagram showing an example of the output register 135. The output register 135 includes a flip-flop 1315 and multiplexers 1316 and 1317.
[0031]
The multiplexer 1316 selects the serial input signal SI when the scan enable signal SE is “1”, and selects the signal input from the embedded core 11 when the scan enable signal SE is “0”, and outputs the selected signal to the flip-flop 1315. The flip-flop 1315 latches the output of the multiplexer 1316 at the rising edge of the clock CLK, and outputs it to the multiplexer 1317 and the input register or output register in the subsequent stage. The multiplexer 1317 selects the output of the flip-flop 1315 when the test enable signal TE is “1”, selects the output of the embedded core 11 when the test enable signal TE is “0”, and outputs it to the custom logic unit 12.
[0032]
Next, the operation of the semiconductor integrated circuit 1 will be described. First, the normal operation of the semiconductor integrated circuit 1 will be described. During normal operation of the semiconductor integrated circuit 1, the test enable signal TE is set to “0”. Therefore, the multiplexer 1314 of the input registers 131 to 134 selects the output of the custom logic unit 12 and outputs it to the embedded core 11. The multiplexer 1317 of the output registers 135 and 136 selects the output of the embedded core 11 and outputs it to the custom logic unit 12. As a result, the custom logic unit 12 and the embedded core 11 are connected, and the semiconductor integrated circuit 1 operates normally.
[0033]
Next, the test operation of the embedded core 11 will be described with reference to the time chart of FIG. At time t1, the test enable signal TE is changed from “0” to “1”. As a result, the semiconductor integrated circuit 1 performs a test operation, the multiplexer 1314 of the input registers 131 to 134 inside the test shift register 13 outputs the output of the gate circuit 1312, and the multiplexer 1317 of the output registers 135 and 136 includes the flip-flop 1315. Select the output.
[0034]
At time t2, the scan enable signal SE is changed from “0” to “1”, and data is input to the serial input signal SI. The multiplexer 1313 of the input registers 131 to 134 selects the serial input signal SI and outputs it to the flip-flop 1311. The multiplexer 1316 of the output registers 135 and 136 selects the serial input signal SI and outputs it to the flip-flop 1315. Accordingly, the flip-flop 1311 of the input register 131, the flip-flop 1311 of the input register 132, the flip-flop 1315 of the output register 135, the flip-flop 1315 of the output register 136, the flip-flop 1311 of the input register 133, and the input The flip-flops 1311 of the register 134 are connected in this order and operate as a shift register. That is, the serial input signal SI that is the test pattern of the embedded core 11 input from the external terminal is taken in and shifted in order of D0, D1, D2, D3, D4, and D5 in synchronization with the rising edge of the clock CLK. Is set in the flip-flop 1311 of the registers 131-134.
[0035]
At time t3, data D0 is input to the flip-flop 1311 of the input register 134 in the final stage of the shift register configuration. At this timing, the scan enable signal SE is changed from “1” to “0”. As a result, the input registers 131 to 134 and the output registers 135 and 136 stop the shift operation. Further, the gate signal Gate is changed from “0” to “1”. As a result, the gate circuit 1312 of the input registers 131 to 134 passes the output of the flip-flop 1311 through, and the multiplexer 1314 selects the output of the gate circuit 1312 and outputs the input pattern to the embedded core 11. The embedded core 11 starts operation with the input pattern. On the other hand, the multiplexer 1316 of the output registers 135 and 136 selects the output of the embedded core 11, and the flip-flop 1315 latches the output of the multiplexer 1316 at the rising edge of the clock CLK. That is, the output pattern of the embedded core 11 is sampled at the rising edge of the clock CLK.
[0036]
At time t4, the gate signal Gate is changed from “1” to “0”. The gate circuit 1312 of the input registers 131 to 134 latches the output of the flip-flop 1311 and fixes the input of the embedded core 11.
[0037]
At time t5, the output pattern of the embedded core 11 with the input-pattern input at time t3 is determined. From time t3 to time t5 is an operation delay of the embedded core 11, and differs depending on the embedded core 11.
[0038]
At time t6 after the operation of the embedded core 11 is confirmed, the flip-flop 1315 of the output registers 135 and 136 latches the output pattern of the embedded core 11. At the same time, the scan enable signal SE is changed from “0” to “1”. As a result, the input registers 131 to 134 and the output registers 135 and 136 perform a shift operation, and the flip-flop 1315 of the output register 136 serving as the final stage of the shift register is embedded in the external terminal of the semiconductor integrated circuit 1. Scanout CSO, which is an output pattern, is output in the order of DO0, DO1, DO2, DO3, DO4, and DO5. The scan-out CSO is compared with the expected operation value prepared in advance.
[0039]
On the other hand, D6, D7, D8, D9, D10, and D11 which are the next input patterns of the embedded core 11 are sequentially input to the serial input signal SI in synchronization with the rising edge of the clock CLK, and the flip-flops of the input registers 131 to 134 are input. Set to 1311. By repeating such an operation and inputting the serial input signal SI in synchronization with the rising edge of the clock CLK, the operation test of the embedded core 11 can be performed in conjunction.
[0040]
Next, a test operation of the custom logic unit 12 in the semiconductor integrated circuit 1 will be described. When the custom logic unit 12 is tested, the scan enable signal SE input from the outside of the semiconductor integrated circuit 1 is set to “1”. As a result, the multiplexer 1224 selects the scan-out CSO that is the output of the test shift register 13. The multiplexers 1225 and 1226 select the outputs of the flip-flops 1221 and 1222. That is, the flip-flops 1221 to 1223 of the scan path circuit 122 are connected in a chain and constitute a shift register.
[0041]
A serial input signal SI is input in synchronization with the clock CLK, and a test pattern is input to the flip-flops 1221 to 1223 via the test shift register 13. When the test pattern is set in the final stage flip-flop 1223 of the scan path circuit 122, the scan enable signal SE is set to "0". As a result, the multiplexers 1224 to 1226 select the output of the combinational circuit 121. Accordingly, the flip-flops 1221 to 1223 latch the output of the combinational circuit 121 that has operated according to the test pattern.
[0042]
Next, the scan enable signal SE is set to “1”. As a result, the flip-flops 1221 to 1223 of the scan path circuit 122 are chain-connected to form a shift register. In synchronization with the clock CLK, the flip-flops 1221 to 1223 sequentially shift the latched output of the combinational circuit 121 and output it to the external terminal of the semiconductor integrated circuit 1 as a scan-out SO. The scan-out SO is compared with the expected value. Such an operation is repeated to test the custom logic unit 12.
[0043]
In order to test the custom logic unit 12, it is necessary to control and observe an interface signal with the embedded core 11. Therefore, in the semiconductor integrated circuit 1 according to the first embodiment, the shift register composed of the input registers 131 to 134 and the output registers 135 and 136 of the test shift register 13 of the embedded core 11 is connected to the test enable signal TE and The output of the flip-flop 1311 (final flip-flop of the test shift register 13) in the input register 134 of the test shift register 13 can be controlled by the scan enable signal SE, and the flip-flop 1221 of the scan path circuit 122 Since the test shift register 13 and the scan path circuit 122 are chain-connected to the first flip-flop 1221 of the shift register composed of ˜1223, the entire semiconductor integrated circuit 1 is based on the scan enable signal SE. It is possible to control the shift operation, thereby enabling a full scan path test of the custom logic unit 12. In addition, by outputting the output of the flip-flop 1311 at the final stage of the test shift register 13 to the external terminal, the end point of the test shift register 13 can be observed.
[0044]
As described above, in the first embodiment, the test shift register 13 that configures the scan path circuit for the embedded core 11 test with the input register and the output register is provided between the embedded core 11 and the custom logic unit 12. The output of the flip-flop in the input register at the final stage of the test shift register 13 or the flip-flop in the output register is output to the external terminal of the semiconductor integrated circuit 1. Thereby, the test pattern of the embedded core 11 can be shortened.
[0045]
Further, the first stage flip-flop of the scan path circuit 122 in the custom logic unit 12 and the last stage flip-flop of the test shift register 13 are connected, and the test shift register 13 and the scan path circuit 122 are connected by the scan enable signal SE. As a result, the test efficiency of the custom logic unit 12 can be increased.
[0046]
Furthermore, since it is configured by a scan flip-flop for chaining input registers to form a shift register and a gate circuit for outputting a test pattern to the embedded core 11, it is embedded without being affected by the shift operation. An input signal to the core 11 can be controlled.
[0047]
Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIG. In the semiconductor integrated circuit 2 according to the second embodiment, a test control module (hereinafter referred to as TCM) 21 and a selector are selected in order to reduce the control signal input from the external terminal of the semiconductor integrated circuit in the first embodiment. 22 is added. Components having the same functions as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.
[0048]
The TCM 21 is a sequence circuit composed of a test mode select TMS, a clock CLK, and a serial input signal SI, and generates control signals for the test shift register 13, the scan path circuit 122, and the selector 22. The test mode select TMS is fetched at the rising edge of the clock CLK, the sequence is changed according to the level (“0” or “1”) of the test mode select TMS at that time, and a control signal is output. Specifically, the TCM 21 includes a test enable signal TE that controls the test shift register 13 based on a test mode select TMS, a serial input signal SI, and a clock CLK input from an external terminal of the semiconductor integrated circuit 2, and a gate signal. A gate and core scan enable signal CSE, a scan enable signal SE for controlling the scan path circuit 122, and a selection signal SEL for controlling the selector 22 are generated. The TMC 21 can be realized with a configuration equivalent to a test access port controller (TAP controller) defined in the IEEE standard 1149.1.
[0049]
The selector 22 selects either the output of the test shift register 13 or the output of the scan path circuit based on the selection signal SEL, and outputs the scan-out SO to the external terminal of the semiconductor integrated circuit 2. In this case, the output of the test shift register 13 is selected when the selection signal SEL is “0”, and the output of the scan path circuit 122 is selected when the selection signal SEL is “1”.
[0050]
Next, the test operation of the semiconductor integrated circuit 2 will be described. First, during the test operation of the embedded core 11, the TCM 21 sets the test enable signal TE to “1” based on the test mode select TMS and the clock CLK. As a result, the semiconductor integrated circuit 2 performs a test operation.
[0051]
Next, based on the test mode select TMS and the clock CLK, the TCM 21 sets the core scan enable signal CSE to “1”, the gate signal Gate to “0”, the scan enable signal SE to “0”, and the selection signal SEL. Is set to “0”. The input registers 131 to 134 and the output registers 135 and 136 of the test shift register 13 are serial input signals SI (test patterns of the embedded core 11) input from the external terminals of the semiconductor integrated circuit 2 in synchronization with the clock CLK. To shift. Since the scan enable signal SE is “0”, the multiplexers 1224 to 1226 of the scan path circuit 122 select the output of the combinational circuit 121. Therefore, the scan path circuit 122 does not operate.
[0052]
When the test pattern for all the input terminals of the embedded core 11 is set in the flip-flops 1311 of the input registers 131 to 134 by the shift operation of the test shift register 13, the TMC 21 generates the gate signal Gate based on the test mode select TMS. Set to “1”. As a result, the test pattern is input to the embedded core 11. Based on the test mode select TMS, the TCM 21 sets the gate signal Gate to “0” to fix the test pattern input to the embedded core 11, and sets the core scan enable signal CSE to “0” to the output register 135. , 136 causes the flip-flop 1315 to latch the output of the embedded core 11. Based on the test mode select TMS input in consideration of the operation delay of the embedded core 11, the TMC 21 sets the core scan enable signal CSE to "1", the input registers 131 to 134 of the test shift register 13, and the output register 135 and 136 perform a shift operation, and the serial input signal SI is set in the flip-flop 1311 of the input registers 131 to 134, and the output of the embedded core 11 of the flip-flop 1315 of the output registers 135 and 136 is customized with the selector 22. The data is output to the scan path circuit 122 of the logic unit 12. By repeating such an operation, the serial input signal SI input from the external terminal of the semiconductor integrated circuit 2 is input to the embedded core 11 to test the embedded core 11.
[0053]
On the other hand, since the selection signal SEL is “0”, the selector 22 that outputs the scan-out SO to the external terminal of the semiconductor integrated circuit 2 selects the output of the test shift register 13. Therefore, by the shift operation of the test shift register 13, the output of the embedded core 11 latched in the flip-flop 1315 of the output registers 135 and 136 is output to the external terminal of the semiconductor integrated circuit 2. The embedded core 11 can be tested by comparing the scan-out SO with an expected value prepared in advance.
[0054]
Next, the test operation of the custom logic unit 12 will be described. Based on the test mode select TMS and the clock CLK, the TCM 21 sets the test enable signal TE, the core scan enable signal CSE, the scan enable signal SE, and the selection signal SEL to “1”. As a result, the test shift register 13 and the flip-flops 1221 to 1223 of the scan path circuit 122 are chain-connected to form a shift register. The serial input signal SI is set in the flip-flops 1221 to 1223 of the scan path circuit 122 through the test shift register 13 by the shift operation.
[0055]
The TCM 21 sets the scan enable signal SE to “0” based on the test mode select TMS. As a result, the multiplexers 1224 to 1225 select the output for the combinational circuit 121. Accordingly, the flip-flops 1221 to 1223 latch the output of the combinational circuit 121 that has operated according to the test pattern.
[0056]
Next, the TCM 21 sets the scan enable signal SE to “1” based on the test mode select TMS. As a result, the flip-flops 1221 to 1223 of the scan path circuit 122 are chain-connected to form a shift register. In synchronization with the clock CLK, the flip-flops 1221 to 1223 sequentially shift the output of the latched combinational circuit 121 and output the scan-out SO to the external terminal of the semiconductor integrated circuit 1 via the selector 22. The scan-out SO is compared with the expected value. Such an operation is repeated to test the custom logic unit 12.
[0057]
As described above, in the second embodiment, the number of external terminals necessary for the test is reduced using the TCM. Therefore, even when the number of external terminals of the semiconductor integrated circuit is limited, the embedded core and the custom logic can be easily obtained. You can test the department.
[0058]
Embodiment 3 FIG.
A third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, a method for inserting a test shift register from a semiconductor integrated circuit realizing a desired function will be described.
[0059]
First, the insertion of the input register will be described. The semiconductor integrated circuit 3 shown in FIG. 8A includes an embedded core 31 and a custom logic unit 32. The signal 33 output from the custom logic unit 32 is connected to the input terminal of the embedded core 31. The custom logic unit 32 includes an internal logic 321 and a combinational circuit 322, and the signal 33 is driven from the combinational circuit 322. That is, the signal 33 is driven by an AND circuit or an OR circuit. Therefore, as shown in FIG. 8B, an input having the same function as that of the input register 131 shown in FIG. 4 is provided between the embedded core 31 and the custom logic unit 32 in order to form a test shift register. Register 34 is inserted. As a result, during the normal operation of the semiconductor integrated circuit 3a, the test enable signal TE becomes “0”, and the output from the combinational circuit 322 is directly input to the embedded core 31 via the multiplexer 1314. During the test operation of the semiconductor integrated circuit 3a, the test enable signal TE becomes “1”, and the output of the gate circuit 1312 is input to the embedded core 31 via the multiplexer 1314. When the scan enable signal SE becomes “1”, the flip-flop 1311 is chain-connected to the preceding and succeeding flip-flops to form a shift register. Then, data is set in the flip-flop 1311 in synchronization with the rising edge of the clock CLK via the serial input signal SI, and the gate signal Gate is set to “1”, whereby the data set in the flip-flop 1311 is transferred to the gate circuit 1312. Propagate to.
[0060]
When the signal 35 output from the flip-flop 323 in the custom logic unit 32 is connected to the input terminal of the embedded core 31 as in the semiconductor integrated circuit 3 shown in FIG. ), A flip-flop 323 is used for the input register 34a. That is, the flip-flop 323 in the custom logic unit 32 is used instead of the flip-flop 1311 of the input register shown in FIG. In this case, as shown in FIG. 9A, the signal 35 input to the embedded core 31 during normal operation is output from the flip-flop 323. Therefore, the output of the flip-flop 323 is connected to the input terminal selected when the test enable signal TE of the multiplexer 1314 of the input register 34a using the flip-flop 323 is "0". As a result, during normal operation of the semiconductor integrated circuit 3a, the test enable signal TE becomes “0”, and the output of the combinational circuit 322 is latched in the flip-flop 323 via the multiplexer 1313. Then, the output of the flip-flop 323 is input to the embedded core 31 via the multiplexer 1314. During the test operation of the semiconductor integrated circuit 3a, the test enable signal TE becomes “1”, and the signal set in the gate circuit 1312 is input to the embedded core 31 via the multiplexer 1314. When the scan enable signal SE becomes “1”, the flip-flop 323 is chain-connected to the preceding and subsequent flip-flops to form a shift register. Then, data is set in the flip-flop 323 in synchronization with the rising edge of the clock CLK via the serial input signal SI, and the gate signal Gate is set to “1”, whereby the data set in the flip-flop 323 is transferred to the gate circuit 1312. Propagate to.
[0061]
Next, insertion of an output register will be described. As shown in FIG. 10A, the signal 38 that is the output of the embedded core 31 of the semiconductor integrated circuit 3 is transmitted to the internal logic 321 via the combinational circuit 322 of the custom logic unit 32. In this case, as shown in FIG. 10B, an output having the same function as that of the output register 135 shown in FIG. 5 in order to form a test shift register between the embedded core 31 and the combinational circuit 322. Register 36 is inserted. As a result, during the normal operation of the semiconductor integrated circuit 3a, the test enable signal TE becomes “0”, and the output of the embedded core 31 is input to the combinational circuit 322 via the multiplexer 1317. Further, during the test operation of the semiconductor integrated circuit 3a, the test enable signal TE becomes “1”. During the period when the scan enable signal SE is “0”, the flip-flop 1315 latches the output of the embedded core 31 via the multiplexer 1316. When the scan enable signal SE becomes “1”, it is chain-connected to the preceding and succeeding flip-flops to form a shift register. Then, the output of the embedded core 31 latched via the scan-out SO in synchronization with the rising edge of the clock CLK is output to the external terminal of the semiconductor integrated circuit 3a.
[0062]
Further, when the signal 37 output from the embedded core 31 is connected to the input terminal of the flip-flop 324 in the custom logic section 32 as in the semiconductor integrated circuit 3 shown in FIG. ), A flip-flop 324 is used for the output register 36a. That is, the flip-flop 324 in the custom logic unit 32 is used instead of the flip-flop 1315 of the output register shown in FIG. In this case, as shown in FIG. 11A, the signal 37 output from the embedded core 31 during normal operation is input to the flip-flop 324, and the output of the flip-flop 234 is output to the internal logic 321. Therefore, the output of the flip-flop 324 is output to the internal logic whether the semiconductor integrated circuit 3a is in a normal operation or a test operation. This eliminates the need to connect the multiplexer 1317 and the test enable signal TE shown in FIG. Thus, when the semiconductor integrated circuit 3a is in a normal operation, the scan enable signal SE is set to “0”, whereby the output of the embedded core 31 is latched by the flip-flop 324 via the multiplexer 1316 and transmitted to the internal logic 321. . During the test operation of the semiconductor integrated circuit 3a, the flip-flop 324 latches the output of the embedded core 31 via the multiplexer 1316 while the scan enable signal SE is “0”. When the scan enable signal SE becomes “1”, it is chain-connected to the preceding and succeeding flip-flops to form a shift register. Then, the output of the embedded core 31 latched via the scan-out SO in synchronization with the rising edge of the clock CLK is output to the external terminal of the semiconductor integrated circuit 3a.
[0063]
As described above, in the third embodiment, when the input register constituting the test shift register is inserted, if the input signal to the embedded core is the output of the flip-flop, the flip-flop is connected to the input register. Used as a flip-flop. On the other hand, when inserting the output register constituting the test shift register, if the output signal of the embedded core is input to the flip-flop, the flip-flop is used as the flip-flop of the output register. Thereby, the flip-flops and multiplexers of the test shift register can be reduced. That is, the circuit scale for testing the semiconductor integrated circuit can be reduced.
[0064]
Embodiment 4 FIG.
A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 12 is a conceptual diagram showing the test generation program and its input / output in the present invention.
[0065]
The circuit connection information 40 defines cell information that defines an embedded core and a functional cell for the target semiconductor integrated circuit to realize a desired function, and connection information that indicates a connection between the embedded core and the functional cell. Is done.
[0066]
The floor plan information 41 includes position information indicating where the embedded core is arranged in the layout of the target semiconductor integrated circuit, position information of the input / output terminals of the embedded core, position information of the functional cells of the custom logic unit, and Position information of external terminals of the semiconductor integrated circuit is defined.
[0067]
The library information 42 defines technology information such as embedded core and functional cell logic information, delay information, and terminal attributes.
[0068]
The embedded core function test pattern 43 defines an embedded core test pattern created from a result of manual design or circuit simulation. The embedded core function test pattern 43 is a parallel pattern for applying an input signal to all signals and comparing an expected value of an output signal within a predetermined period.
[0069]
Next, the operation of the test circuit insertion program will be described. In the embedded core test cell insertion process (step S1), an embedded core test circuit is inserted based on the circuit connection information 40, the floor plan information 41, and the library information 42, and the embedded core test cell layout designation information 44 and the embedded core test cell are embedded. The scan path connection order information 45 of the core test cell and the circuit connection information 46 after insertion of the embedded core test cell are generated.
[0070]
The operation of the embedded core test cell insertion process will be described in detail with reference to the flowchart of FIG. The circuit connection information 40 and the library information 42 are read (step S100), and an embedded core terminal in which no embedded core test cell is inserted is selected (step S101).
[0071]
The terminal direction of the terminal of the embedded core selected based on the library information 42 is confirmed (step S102). When the selected embedded core terminal is an input terminal, an embedded core test cell for input is selected (step S103). As shown in FIG. 14, the embedded core test cell 6 a for input is a so-called soft macro capable of developing a lower layer composed of a flip-flop 61, a gate circuit 62, and a multiplexer 63.
[0072]
In the case of the semiconductor integrated circuit 7 of FIG. 16, the terminals C, E, and F of the embedded core 71 are input terminals. Therefore, when the terminals C, E, and F of the embedded core 71 are selected as terminals where the embedded core test cell is not inserted, the input embedded core test cell is selected.
[0073]
If the selected embedded core terminal is an output terminal, an embedded core test cell for output is selected (step S104). As shown in FIG. 15, the embedded core test cell 6b for output is a so-called soft macro capable of developing a lower layer composed of a flip-flop 65 and a multiplexer 66.
[0074]
In the case of the semiconductor integrated circuit 7 of FIG. 16, the terminals A, B, and D of the embedded core 71 are output terminals. Therefore, when the terminals A, B, and D of the embedded core 71 are selected as the terminals where the embedded core test cell is not inserted, the output embedded core test cell is selected.
[0075]
Based on the circuit connection information 40 and the library information 42, it is determined whether or not the terminal of the embedded core is connected to the combinational circuit (step S105). As a result of the determination, if the terminal of the selected embedded core is connected to the combinational circuit, it is determined to insert the selected embedded core test cell (step S106), and the embedded core test in which the circuit connection information 40 is selected is determined. Change to the circuit connection information in which the cell is inserted.
[0076]
In the case of the semiconductor integrated circuit 7 of FIG. 16, the input terminals C and E of the embedded core 71 are connected to the combinational circuit 75 and wirings 720 and 721, respectively. Therefore, an embedded core test cell for input is inserted into the wirings 720 and 721. Further, the output terminal B of the embedded core 71 is connected to the combinational circuit 75 by a wiring 711. Therefore, an embedded core test cell for output is inserted. That is, as shown in FIG. 17, the embedded core test cell 743 for output is connected to the output terminal B of the embedded core 71 and the wiring 711 of the combinational circuit 75, and the input terminal C of the embedded core 71 and the wiring 720 of the combinational circuit 75 are connected. The embedded core test cell 731 for input is inserted, and the embedded core test cell 732 for input is inserted into the input terminal E of the embedded core 71 and the wiring 721 of the combinational circuit 75, respectively.
[0077]
As a result of the determination, if the terminal of the embedded core is not connected to the combinational circuit, that is, if it is connected to a flip-flop, the embedded core test cell is replaced with the flip-flop of the embedded core test cell. Insert (step S107). Specifically, as described in the third embodiment, in the case of the input terminal of the embedded core, the flip-flop 61 of the embedded core test cell 6a for input is connected to the flip-flop connected to the input terminal of the embedded core. In the case of the output terminal of the embedded core, the flip-flop connected to the output of the embedded core is used as the flip-flop 65 of the embedded core test cell 6b for output. And the circuit connection information 40 is changed corresponding to those connections.
[0078]
The input terminal F of the embedded core 71 of the semiconductor integrated circuit 7 in FIG. 16 is connected to the flip-flop 74 and the wiring 722. Therefore, the flip-flop 74 is replaced with the flip-flop 61 of the embedded core test cell 6a for input shown in FIG. The output terminals A and D of the embedded core 71 are connected to the flip-flops 72 and 73 by wirings 710 and 712, respectively. Therefore, the flip-flop 72 and the flip-flop 73 are replaced with the flip-flop 65 of the embedded core test cell 6b for output shown in FIG. That is, as shown in FIG. 17, an output embedded core test cell 741 replacing the flip-flop 72 is connected to the output terminal A of the embedded core 71 and the wiring 710 of the flip-flop 72, and the output terminal D of the embedded core 71. The wiring 712 of the flip-flop 73 has an embedded core test cell 742 for output replacing the flip-flop 73, and the input terminal F of the embedded core 71 and the wiring 722 of the flip-flop 74 have inputs for replacing the flip-flop 74. Embedded core test cells 733 are respectively inserted.
[0079]
Based on the changed circuit connection information 40, the operation of inserting the embedded core test cell is repeated until the embedded core test cell is inserted into all the terminals of the embedded core (steps S101 to S108).
[0080]
When the embedded core test cells for all the embedded core terminals are inserted, the scan path connection order of the flip-flops in the embedded core test cell is extracted (step S109). Specifically, based on the floor plan information 41 of the embedded core, the scan flip-flops in the embedded core test cell are chain-connected with the shortest path, and the start end thereof is connected to an external terminal for inputting a scan pattern of the semiconductor integrated circuit. , A constraint condition for connecting the termination to the scan path circuit in the internal logic circuit is generated and output to the scan path connection order information 45 of the embedded core test cell.
[0081]
FIG. 18 is an image diagram of the floor plan showing the embedded core 71 of the floor plan information 41 of the semiconductor integrated circuit 7 shown in FIG. 16 and the terminal position of the serial input signal SI. The floor plan information 41 indicates that the external terminal of the serial input signal SI of the semiconductor integrated circuit 7 is located closest to the input terminal C of the embedded core 71. Accordingly, when the difficulty of wiring around the embedded core 71 is uniform, the flip-flop in the embedded core test cell connected to the input terminal C of the embedded core 71 is connected to the terminal for inputting the serial input signal SI. The optimal connection is the start of the campus circuit. For the terminals A, B, D, E, and F of the other embedded core 71, the shortest wiring is realized by connecting the terminal C in the clockwise direction or the counterclockwise direction. For example, when connecting in the counterclockwise direction, in the semiconductor integrated circuit 7 shown in FIG. 17, the embedded core test cells 731, 743, 741, 733, 732, and 742 are in this order. The scan path connection order information 45 of the embedded core test cell in which this order is converted into a format that can be used in the scan path connection process is output. If there are other priority conditions such as a non-wiring area, the order is determined taking this into consideration.
[0082]
When the scan path connection order information 45 is output, layout designation information of the flip-flop in the embedded core test cell is extracted (step S110). Specifically, in order to realize the shortest wiring length of the scan path connection order information 45 of the embedded core test cell, it is necessary to optimize the arrangement of the scan flip-flops. That is, when the difficulty of cell placement around the buried core is uniform, it is desirable to place the flip-flop in the buried core test cell in the vicinity of the corresponding buried core terminal. Therefore, based on the layout information of the custom logic part in the floor plan information 41, the embedded core test cell flip-flop is extracted from the embedded core test cell by extracting the constraint condition at the optimum position with respect to the related embedded core terminal. The data is output to the cell layout designation information 44.
[0083]
In the case of the semiconductor integrated circuit 7 of FIG. 17, the constraint condition is that the respective flip-flops in the embedded core test cells 741, 743, 731, 742, 732, and 733 are arranged in the vicinity of the terminals A to F of the embedded core. Is output to the layout specification information 44 of the embedded core test cell. Note that if there are other priority constraints such as placement prohibited areas, the placement conditions are determined in consideration of this.
[0084]
When the layout designation information 44 is output, the empty terminals of the embedded core test cells are connected (step S111). Specifically, the test enable signal TE, the gate signal Gate, the clock CLK of each embedded core test cell inserted into the semiconductor integrated circuit, the output of the embedded core test cell in the final stage, and the scan-out CSO of the semiconductor integrated circuit Connecting.
[0085]
In the case of the semiconductor integrated circuit 7 of FIG. 17, the external terminal for inputting the clock CLK of the semiconductor integrated circuit 7 and the clock terminals CLK of the embedded core test cells 731 to 733 and 741 to 743 are connected by the wiring 751. An external terminal to which the test enable signal TE of the embedded core test cells 731 to 733 and 741 to 743 is input is connected by a wiring 752. An external terminal for inputting the gate signal Gate of the semiconductor integrated circuit 7 and a terminal for inputting the gate signal Gate of the embedded core test cells 731 to 732 are connected by a wiring 753. Further, the terminal DO of the embedded core test cell 742 that is the final stage when the scan path connection order information 45 is determined is connected to the external terminal that outputs the scan-out CSO of the semiconductor integrated circuit 7 by the wiring 754.
[0086]
When the connection is completed, circuit connection information 46 after insertion of the embedded core test cell, which is connection information of the semiconductor integrated circuit after insertion of the embedded core test circuit, is output (step S112).
[0087]
When the embedded core test cell insertion process is completed, a scan path connection process (step S2) is performed. In the scan path connection processing, first, circuit connection information 46 after insertion of the embedded core test cell is read, and all flip-flops in the circuit are scan flip-flops with multiplexers or logically equivalent circuits as shown in FIG. Convert to Specifically, the flip-flop 61 of the embedded core test cell 6a inserted by the embedded core test cell insertion process is converted into the scan flip-flop 8, and a circuit logically equivalent to the input register 131 shown in FIG. Become. Further, the flip-flop 65 of the embedded core test cell 6b inserted by the embedded core test cell insertion process is converted into the scan flip-flop 8, and a circuit logically equivalent to the output register 135 shown in FIG. Further, all the flip-flops in the custom logic unit are also converted into scan flip-flops 8.
[0088]
After all the flip-flops are converted into scan flip-flops 8, these scan flip-flops 8 are chain-connected based on the connection order defined in the scan path connection order information 45. That is, the scan enable signal SE is supplied to the terminal SFSE of the scan flip-flop 8, the serial input signal SI is supplied to the terminal SFSI of the scan flip-flop 8 as the first stage, and the previous scan flip-flop is supplied to the terminal SFSI of the other scan flip-flop 8. The output of the group 8 is connected to the terminal SFD of the scan flip-flop 8 for signals during normal operation (input / output signals of the embedded core 71 and input / output signals of the combinational circuit 75). When the scan path connection is completed, circuit connection information 47 after the scan path connection is output.
[0089]
FIG. 20 is a conceptual diagram showing the semiconductor integrated circuit 7 that has executed the scan path connection process on the circuit connection information 46 of the semiconductor integrated circuit 7 shown in FIG. The embedded core test cells 731a to 733a and 741a to 743a are embedded core test cells after the flip-flops inside the embedded core test cells 731 to 733 and 741 to 743 in FIG. The wirings 760 to 766 are wirings for scan path connection, and embedded core test is performed using the wirings 760 to 766 from the serial input signal SI input from the external terminal of the semiconductor integrated circuit 7 based on the scan path connection order information 45. The cells 731a to 733a and 741 to 743a are chain-connected. Further, the embedded core test cell 742 a at the final stage is connected to the scan path circuit of the logic circuit 76 by the wiring 766. The scan flip-flop 8 at the final stage of the scan path of the logic circuit 76 outputs the scan-out SO to the external terminal of the semiconductor integrated circuit 7 through the wiring 767. Reflecting these wirings, circuit connection information 47 after scan path connection is output.
[0090]
When the scan path connection process ends, the embedded core test pattern conversion process (step S3) is executed based on the circuit connection information 47 after the scan path connection and the embedded core function test pattern 43. The detailed operation of the embedded core test pattern conversion process will be described with reference to the flowchart of FIG.
[0091]
First, the circuit connection information 47, the library information 42, and the embedded core function test pattern 43 after the scan path connection are read (step S300), and the circuit that is the target of the embedded core test is specified (step S301). Specifically, in the case of the semiconductor integrated circuit 7 shown in FIG. 20, the target is the embedded core 71, and the target is the logic circuit 76 and the combinational circuit 75. Therefore, the embedded core 71 is specified as a test target.
[0092]
When the circuit to be embedded core test is specified, a test rule check is performed based on the embedded core terminal information defined in the library information 42 and the embedded core function test pattern 43 (step S302). Specifically, for example, whether the input / output signals of the test pattern defined in the embedded core function test pattern 43 correspond to the terminals of the embedded core 71 defined in the library information 42, or the embedded core function test The prohibition condition of the signal input to the embedded core 71 defined in the pattern 43 is checked, for example, an indefinite value is input.
[0093]
When the test rule check is completed, the test pattern is converted (step S303). Test pattern conversion will be described with reference to the semiconductor integrated circuit 7 shown in FIG. 20 and the time chart of FIG. The embedded core function test pattern 43 includes C0, C1, C2, and C3 at the input terminal C of the embedded core 71, E0, E1, E2, and E3 at the input terminal E, and F0 and F1 at the input terminal F at every cycle T11. , F2 and F3 are defined. The expected values of the output terminal A are A0, A1, A2, and A3, the expected values of the output terminal B are B0, B1, B2, and B3, and the expected values of the output terminal D are D0, D1, D2, and D3. Such a parallel-type embedded core function test pattern is converted into a pattern that can be input from the external terminal of the semiconductor integrated circuit 7 as the serial input signal SI. That is, the embedded core test cells 731a to 733a and 741a to 743a of the semiconductor integrated circuit 7 shown in FIG.
[0094]
The embedded core test pattern inputs C1, E1, and F1 in the parallel format having the period T11 of the embedded core function test input pattern are converted into the shift period T12 of the pattern after conversion, and the embedded core test pattern expected values A1, B1, and D1 are the shift period. Assign to each T13. That is, the expected value of the embedded core test pattern in parallel format is assigned to the input of the embedded test pattern in parallel format after one shift period.
[0095]
The order of assignment is from the flip-flop of the embedded core test cell at the head of the chain-connected embedded core test cells, that is, from the flip-flop connected to the external terminal of the semiconductor integrated circuit 7 that outputs the scan-out CSO. Become. In the case of the semiconductor integrated circuit 7 shown in FIG. 20, serialization is performed in the order of the terminals D, E, F, A, B, and C of the embedded core 71. Therefore, the serial input signal SI includes an embedded core test cell 742a connected to the terminal D, an embedded core test cell 732a connected to the terminal E, an embedded core test cell 733a connected to the terminal F, and a terminal A. The data to be set in the order of the scan flip-flops 8 of the embedded core test cell 741a connected to the terminal B, the embedded core test cell 743a connected to the terminal B, and the embedded core test cell 731a connected to the terminal C are input. To do. At this time, the input pattern to the scan flip-flop 8 in the embedded core test cells 742a, 741a, 743a connected to the output terminals D, A, B of the embedded core 71 may be either “0” or “1”. . The expected value of the timing at which the data of the scan flip-flop 8 of the embedded core test cells 732a, 733a, 731a connected to the input terminals E, F, C of the embedded core 71 is shifted and output as the scan-out CSO is “0”. "1" or "1" may be used, and the expected value at this time is a don't care ("x").
[0096]
For the control signals, the test enable signal TE is fixed to “1”, the scan enable signal SE is set to “1”, and the gate signal Gate is set to “0”. After the test pattern to be input to the terminal C of the embedded core 71 is set in the embedded core test cell 731a connected to the external terminal of the semiconductor integrated circuit 7 to which the serial input signal SI is input, the scan enable signal SE is set. The gate signal Gate is set to “1” to “0”. That is, the scan enable signal SE is set to “0” and the gate signal Gate is set to “1” every shift period T14 in which data is set in the flip-flop of the embedded core test cell. Then, the gate signal Gate is set to “0” in synchronization with the falling edge of the clock CLK. The scan enable signal SE is set to “1” in synchronization with the rising edge of the clock CLK after the operation delay time of the embedded core 71 is taken. In the case of the time chart of FIG. 22, since the operation delay time of the embedded core 71 is within the period of the clock CLK, the scan enable signal SE becomes “1” in the period of the clock CLK1. When the operation delay of the embedded core 71 is less than n (0 <n, n is a natural number) times the period of the clock CLK, the capture period T15 in which the scan enable signal SE is “0” is the period of n clock CLK. Cost. Since the operation delay time of the embedded core 71 is defined in the library information 42, the capture period T15 is determined based on this operation delay time.
[0097]
In this way, the embedded core function test pattern 48 using the scan path obtained by converting the embedded core function test pattern 43 into a test pattern corresponding to the circuit connection information 47 after the scan path connection is output (step S304). The core test pattern conversion process ends.
[0098]
Finally, test pattern automatic generation processing is performed (step S4). In the test pattern automatic generation process, the library information 42 and the circuit connection information 47 after the scan path connection are read. Then, for example, a randomly generated signal or a signal generated by a test pattern automatic generation method of an existing scan test is input to the scan path circuit, and the combinational circuit 75 is operated to execute a static simulation. Then, the failure detection rate of the combinational circuit of the circuit connection information 47 after the scan path connection is calculated, and a test pattern with high coverage is generated. Then, the generated test pattern is output as a scan path test pattern 49.
[0099]
As described above, in the fourth embodiment, in the embedded core test cell insertion process, test cells are inserted into the input terminal and the output terminal of the embedded core based on the circuit connection information 40, the floor plan information 41, and the library information. Then, the circuit connection information 46 changed to the cell information and connection information after the test cell insertion is generated, and the flip-flop defined in the circuit connection information 46 changed to the connection after the test cell insertion in the scan path connection process The circuit connection information 47 changed to the cell information and the connection information after the generation of the scan path circuit is generated by replacing the scan flip-flop with the chain connection. Thereby, it is possible to design without being aware of a circuit necessary for the test at the time of designing, and the design time can be shortened.
[0100]
Also, in the embedded core test pattern conversion process, the embedded core function test pattern 43 is added with a control signal necessary for the embedded core test corresponding to the circuit connection information 47 after the scan path connection, and the embedded core function test pattern 43 And a test pattern of a custom logic part is generated in the test pattern automatic generation process. Thereby, the time for generating the test pattern is shortened, and the design efficiency can be increased.
[0101]
In the fourth embodiment, the embedded core test cell insertion process, the scan path connection process, the embedded core test pattern conversion process, and the test pattern automatic generation process operate as individual processes, and an external storage medium such as a file is used between the processes. In the above description, the data is exchanged via the network. That is, each processing has been described as a configuration that can operate as an individual program. However, the processing may be realized as a single program and shared as data constructed in the memory instead of the external storage medium.
[0102]
Embodiment 5 FIG.
The first to fourth embodiments have been described based on a so-called mode select method using a scan flip-flop that uses a single clock CLK to switch between a test operation and a normal operation using a scan enable signal SE. However, the semiconductor integrated circuit and the test generation program according to the present invention can also be applied to a clock select system in which a test and a normal operation are controlled by individual clocks. By replacing the scan enable signal SE in the first to fourth embodiments with a scan clock and similarly performing a scan path design, the same function can be realized, and the same effect as in the first to fourth embodiments can be obtained. Can do.
[0103]
【The invention's effect】
As described above, according to the semiconductor integrated circuit of the present invention, between the custom logic unit and the embedded core, when testing the embedded core, each input register connected to the input terminal of the embedded core, and the embedded The test pattern of the embedded core that is serially input by being chain-connected to each output register connected to the output terminal of the core is set in each input register by a shift operation. When the gate signal for outputting the set test pattern of the embedded core to the embedded core is asserted, the embedded core is operated with the test pattern of the embedded core set in each input register, and the output is used for each output. When latched in a register and the gate signal is negated, the output of the latched embedded core is output to an external terminal by a shift operation. As a result, the test pattern of the embedded core can be shortened and the semiconductor integrated circuit can be efficiently tested.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a custom logic unit shown in FIG.
FIG. 3 is a block diagram showing a configuration of a test shift register shown in FIG. 1;
4 is a circuit diagram showing an example of an input register shown in FIG. 3. FIG.
FIG. 5 is a circuit diagram showing an example of the output register shown in FIG. 3;
6 is a time chart for explaining a test operation of the embedded core of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG.
FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 8 is a diagram for explaining a method for inserting an input register of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 9 is a diagram for explaining a method for inserting an input register of a semiconductor integrated circuit according to a third embodiment of the present invention.
10 is a diagram for explaining a method for inserting an output register of a semiconductor integrated circuit according to a third embodiment of the present invention; FIG.
11 is a diagram for explaining a method for inserting an output register of a semiconductor integrated circuit according to a third embodiment of the present invention; FIG.
FIG. 12 is a conceptual diagram showing a test generation program and its input / output in the present invention.
FIG. 13 is a flowchart for explaining an operation of an embedded core test cell insertion process;
FIG. 14 is a circuit diagram showing a configuration of an embedded core test cell for input inserted in an embedded core test cell insertion process.
FIG. 15 is a circuit diagram showing a configuration of an embedded core test cell for output inserted in an embedded core test cell insertion process;
FIG. 16 is a block diagram showing a configuration of a semiconductor integrated circuit before an embedded core test cell is inserted.
FIG. 17 is a block diagram showing a configuration of a semiconductor integrated circuit after an embedded core test cell is inserted.
18 is an image of the floor plan showing the embedded core of the floor plan information of the semiconductor integrated circuit shown in FIG. 16 and the terminal position of the serial input signal.
FIG. 19 is a circuit diagram showing an example of a scan flip-flop used in a scan path connection process.
FIG. 20 is a block diagram showing a configuration of a semiconductor integrated circuit after a scan path connection process;
FIG. 21 is a flowchart for explaining an operation of embedded core function test pattern conversion processing;
FIG. 22 is a time chart for explaining the operation of embedded core function test pattern conversion processing;
[Explanation of symbols]
1, 2, 3, 3a, 7 semiconductor integrated circuit, 6a, 731, 732, 733 embedded core test cell for input, 6b, 741, 742, 743 embedded core test cell for output, 8 scan flip-flop, 11, 31, 71 Embedded core, 12 Custom logic section, 13 Test shift register, 21 TCM, 22 Selector, 33, 35, 37, 710, 711, 712, 720, 721, 722, 751, 752, 753, 760, 761 , 762,763,764,765,766 wiring, 40 circuit connection information, 41 floor plan information, 42 library information, 43 embedded core function test pattern, 44 layout designation information, 45 scan campus connection order information, 46 embedded core test cell Circuit connection information after insertion, 47 scan patterns Circuit connection information after connection, embedded core function test pattern using 48 scan paths, 49 scan path test pattern, 75, 121, 322 combination circuit, 122 scan path circuit, 32, 131, 132, 133, 134 input register 36, 135, 136 output register, 321 internal logic, 61, 62, 65, 72, 73, 74, 1221, 1222, 1223, 1311, 1315 flip-flop, 63, 66, 1224, 1225, 1226, 1313 1314, 1316 Multiplexer, 1312 Gate circuit.

Claims (7)

In a semiconductor integrated circuit comprising: an embedded core having one or more functional cores; and a custom logic unit having a combination circuit and a scan path circuit in which a plurality of scan flip-flops are chain-connected,
Between the custom logic unit and the embedded core, an input register connected to each input terminal of the embedded core, and an output register connected to each output terminal of the embedded core, At the time of the embedded core test operation, the input registers and the output registers are connected in a chain to form a scan path, and the test pattern of the embedded core that is input serially is shifted by the shift operation. When the gate signal for outputting the set embedded core test pattern to the embedded core is asserted, the embedded core is operated with the embedded core test pattern set in each input register, When the output is latched in each output register and the gate signal is negated , The test shift register for outputting the output of the latched embedded cores by shift operation and the first-stage scan flip-flops of said external terminals scan path circuit,
A semiconductor integrated circuit comprising: The input register is
A scan flip-flop configured to form a shift register in a chain connection with an input register or output register in the preceding stage and the subsequent stage;
A gate circuit for controlling the output of a test pattern in the embedded core;
With
The output register is
A scan flip-flop configured to form a shift register in a chain connection with an input register or output register in the preceding stage and the subsequent stage;
A multiplexer that selects one of the output of the embedded core and the output of the scan flip-flop and outputs it to the custom logic unit;
The semiconductor integrated circuit according to claim 1, comprising: A test for generating a control signal for controlling the test shift register and the scan path circuit based on a test mode select signal input from an external terminal, a clock signal, and a test pattern of the embedded core input serially Control module,
The semiconductor integrated circuit according to claim 1, further comprising: Cell connection information defining cell information defining the embedded core and the functional cell, connection information indicating connection between the embedded core and the functional cell, and the embedded core and functional cell defined in the circuit connection information Input terminal of the embedded core based on floor plan information in which terminal information and position information of the embedded core are defined, and library information in which logic information, delay information, and terminal attributes of the embedded core and functional cells are defined And an embedded core test cell insertion processing step for inserting a test cell into the output terminal and generating circuit connection information changed to cell information and connection information after the test cell insertion,
The circuit connection changed to the cell information and connection information after generating the scan path circuit by replacing the flip-flop defined in the circuit connection information changed to the connection after the test cell insertion with the scan flip-flop A scan path connection processing step for generating information;
Based on the embedded core function test pattern in which the test pattern for testing the embedded core and the expected value are defined in parallel format, and the library information, the cell information and the connection information after the scan path circuit is generated An embedded core test pattern conversion processing step for converting the embedded core function test pattern by adding a control signal necessary for the embedded core test corresponding to the external terminal of the changed circuit connection information;
Test pattern automatic generation processing step for generating a test pattern of a custom logic unit other than the embedded core of the circuit connection information changed to the cell information and connection information after generating the scan path circuit;
A test generation program comprising: The embedded core test cell insertion step includes:
5. The test generation program according to claim 4, wherein when a flip-flop is connected to an input / output terminal of the embedded core, the connected flip-flop is shared with the flip-flop in the test cell. . The embedded core test cell insertion step includes:
Based on the terminal position of the embedded core, generating layout designation information and scan path connection order information which are constraints that arrange the wirings connecting the test cells to be the shortest,
The scan path connection processing step includes:
6. The test generation program according to claim 4, wherein the scan flip-flop is connected based on the layout designation information and the scan path connection order information. The layout designation information is
It further includes a constraint condition that the wiring connecting the first stage flip-flop of the scan path circuit configured in the custom logic unit and the last stage flip-flop of the scan path circuit configured by the test cell is arranged to be the shortest. The test generation program according to claim 6.

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