JP2009253023A - Design method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method of a semiconductor integrated circuit provided with a scan test function not only satisfying a required specification when an AC spec of an arithmetic processing circuit is specified, but also capable of preventing degradation of a failure detection rate. <P>SOLUTION: This design method of a semiconductor integrated circuit including a scan test circuit structured such that a scan chain is composed by connecting, in series to one another, a plurality of flip-flops arranged corresponding to each of a plurality of logic circuit blocks constituting the arithmetic processing circuit, and test output date output from the respective logic circuit blocks in response to test input data supplied from an input terminal of the scan chain are extracted from an output terminal of the scan chain. The design method includes steps of: setting the flip-flop of an input-side first stage connected to a logic input terminal of the arithmetic processing circuit in the first stage of the scan chain; setting a flip-flop of the last output stage connected to a logic output terminal of the arithmetic circuit in the last stage of the scan chain; and automatically generating other circuit configurations of the scan test circuit by using an automatic test patter generation tool. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for designing a semiconductor integrated circuit having a scan test circuit used for failure detection.

  In the LSI test, there is a problem that the circuit scale of DUT (Device Under test) is large. It is virtually impossible to test all input combinations. LSI circuit design techniques have been developed in pursuit of automation (automatic placement and routing, logic synthesis, etc.). Therefore, methods for automatically generating test circuits have been studied. Currently, methods such as scan tests are put into practical use.

  The current digital LSI is designed on the premise of a synchronous circuit system, and a combinational circuit is inserted between D flip-flops (hereinafter referred to as D-FF) sharing a clock signal, and these are synchronized with the clock signal. Is working. In the scan test, a type of shift register (scan chain) is configured by connecting in series scan flip-flops (hereinafter referred to as scan FFs) each having a selector (multiplexer) added to the input of each D-FF.

  FIG. 1 shows a configuration of a scan FF and a scan test circuit using the scan FF. The scan FF 20 is configured by connecting a selector 20b to a data input terminal D of a normal D-FF 20a. A logic input signal from the preceding logic circuit block is input to the input terminal IN of the selector 20b via a logic input signal line (INPUT). A scan-in signal (test data signal) for performing a scan test is input to the scan-in terminal SI of the selector 20b via a scan-in signal line (SCAN_IN). Further, a scan enable signal that controls whether a scan-in signal or a logic input signal is supplied to the D-FF 20a is input to the selector 20b via a scan enable signal line (SCAN_EN).

  A clock signal is supplied to the clock input terminal of the D-FF 20a via a clock signal line (CLK). The D-FF 20a outputs an output signal corresponding to the state of the input signal supplied from the selector 20b to the output terminal Q in synchronization with the clock signal. That is, either the scan-out signal corresponding to the scan-in signal or the logic output signal corresponding to the logic input signal is selectively output to the output terminal of the D-FF 20a. The output terminal of the D-FF 20a is connected to the subsequent logic circuit block 30 and the scan-in terminal SI of the subsequent scan FF.

  The scan test by the scan test circuit as shown in FIG. First, when a high level scan enable signal is supplied from the outside via the scan enable terminal (SCAN_EN) and the scan mode is selected, the selector 20b selects the scan-in terminal SI. That is, in this case, since the output signal from the logic circuit block 30 is blocked by the selector 20b, a scan path in which the scan FFs 20 are substantially connected in series with each other is configured. In this state, by supplying a scan-in signal (test input data signal) from the outside via the scan-in signal line (SCAN_IN), an initial value is set in each scan FF 20 (this is referred to as a scan-in operation). The initial value held in the scan FF 20 is given as an input signal of the logic circuit block 30 connected so that the output signal of the scan FF 20 is input. The logic circuit block 30 outputs a processing result corresponding to the given initial value. That is, any state during the operation of the logic circuit block 30 can be reproduced by an external input by the scan-in operation.

  Next, by setting the scan enable signal to a low level, the connection of the scan FF 20 is returned to the normal state, and the processing result output from the logic circuit block 30 is taken into each scan FF 20 (this is referred to as a logic test operation).

Next, by setting the scan enable signal to high level again, the scan path is formed again, and the processing results (test output data) by the respective logic circuit blocks 30 with respect to the initial values are sequentially collected (this is referred to as scan-out operation). Called). The following Patent Documents 1 and 2 each disclose a technique having such a scan FF.
Japanese Patent No. 3548922 JP 2000-20560 A

  In general, when an AC spec (timing spec) of an integrated circuit is defined, it is connected to a logic input terminal of an arithmetic processing circuit configured by combining each logic circuit block so as to satisfy the AC spec. The first flip-flop on the input side and the final output flip-flop connected to the logic output terminal of the arithmetic processing circuit are not scanned. That is, these flip-flops do not constitute a scan chain. FIG. 2 shows a configuration of an integrated circuit having a conventional scan test function when the AC specification of such an integrated circuit is defined in FIG.

  The D-FF 11 is a first stage D flip-flop on the input side of the arithmetic processing circuit. The D-FF 12 is a D flip-flop at the final output stage of the arithmetic processing circuit. Since these D-FFs affect the operation timing of the arithmetic processing circuit, signal delay becomes a problem when the AC specifications of the arithmetic processing circuit are defined. For this reason, these D-FFs cannot be configured as scan FFs in order to avoid signal delay, and are configured as normal D-FFs. The reason will be described later.

  The scan FFs 21, 22, and 23 are scan FFs having the same configuration as the scan FF 20 illustrated in FIG. These scan FFs 21 to 23 switch the circuit connection state to the scan mode or the normal mode based on the scan enable signal supplied via the scan enable signal line (SCAN_EN), and via the scan-in signal line (SCAN_IN). An initial value is set by the supplied scan-in signal (test input data), and a scan test is executed for the corresponding logic circuit block.

  The logic circuit blocks 31 to 35 are circuit blocks constituting an arithmetic processing circuit, and are inserted between the flip-flops sharing the clock signal. The logic circuit blocks 31 to 35 perform arithmetic processing on the input signal supplied from the preceding flip-flop, and supply the result to the input terminal D of the succeeding flip-flop.

  Next, the reason why the first flip-flop 11 at the input side of the arithmetic processing circuit and the flip-flop 12 at the final output stage of the arithmetic processing circuit cannot be scanned when the AC specifications of the integrated circuit are defined is described with reference to FIGS. explain. FIG. 3A shows the circuit configuration of the portion after the pattern layout when the first flip-flop 11 on the input side of the arithmetic processing circuit is scanned. Making the flip-flop 11 scan means that the flip-flop 11 is configured by a scan FF and is taken into the scan chain. However, if the first flip-flop 11 on the input side is configured with a scan FF, wiring is automatically connected between the scan-in terminal SI of the other scan FF 20 and the input terminal D of the flip-flop 11 when creating a pattern layout by the automatic placement and routing system. As a result, the repeater 50 is automatically inserted on the logic input signal line (INPUT) to which the logic input signal is to be input. That is, when the wiring in the chip designed by the automatic placement and routing system used in the LSI chip pattern layout becomes a long path, a repeater circuit is automatically inserted in the long path to avoid signal deterioration and delay. I am going to do that. Here, the repeater circuit is a waveform shaping circuit that is automatically inserted in the middle of wiring in order to avoid signal delay or deterioration due to wiring resistance or parasitic capacitance generated in a long path formed by the automatic placement and routing system. The automatic placement and routing system calculates the length of the wiring connecting the circuit elements, calculates the resistance value of the wiring, calculates the parasitic capacitance value of the wiring, and calculates the calculated resistance value and capacitance value. The amount of delay is calculated from When the delay amount exceeds the allowable value, a repeater circuit is automatically inserted at a point where the delay value is minimized.

  However, a delay occurs when the logic input signal supplied to the flip-flop 11 through the logic input signal line (INPUT) passes through the automatically inserted repeater 50, and the required AC specifications are satisfied. It may not be possible. Therefore, when the AC specifications of the arithmetic processing circuit are defined, as shown in FIG. 3B, the first flip-flop on the input side of the arithmetic processing circuit is constituted by a D-FF having no scan function. Thus, automatic wiring formation and automatic repeater insertion are avoided by the automatic placement and routing system. As a result, the required AC specifications can be satisfied.

  Similarly, FIG. 4A shows the circuit configuration when the flip-flop 12 at the final output stage of the arithmetic processing circuit is scanned. By configuring the flip-flop 12 with a scan FF, the flip-flop 12 is taken into the scan chain. However, when the flip-flop 12 is configured by a scan FF, a wiring is formed between the output terminal Q of the flip-flop 12 and the scan-in terminal SI of another scan FF 20 during pattern layout by the automatic placement and routing system, and as a result. The repeater 51 is automatically inserted on the logic output signal line (OUTPUT). Then, the output signal output from the flip-flop 12 at the final output stage may be delayed by passing through the automatically inserted repeater 51, and may not meet the required AC specifications. Therefore, when the AC specifications of the arithmetic processing circuit are defined, as shown in FIG. 3B, the flip-flop at the final output stage of the arithmetic processing circuit is configured with a D-FF having no scan function. Thus, automatic wiring formation and automatic repeater insertion are avoided by the automatic placement and routing system.

  Thus, when the AC specifications of the arithmetic processing circuit are defined, it is necessary to avoid the insertion of repeaters on the logic input signal line (INPUT) and the logic output signal line (OUTPUT) by the automatic placement and routing system. For this reason, the input-side first stage and final output stage flip-flops of the arithmetic processing circuit cannot be scanned. However, when these flip-flops are excluded from the scan chain, although the AC specifications are satisfied, the corresponding arithmetic processing circuit components (that is, logic circuit blocks 31 and 35 in FIG. 2) are excluded from the scan test target. As a result, the failure detection rate of the circuit portion is significantly reduced.

  The present invention has been made in view of the above points, and in the case where the AC specifications of the arithmetic processing circuit are defined, not only can the required specifications be satisfied, but also a reduction in the failure detection rate can be prevented. An object of the present invention is to provide a method for designing a semiconductor integrated circuit having a scan test function.

  According to the semiconductor integrated circuit design method of the present invention, a plurality of flip-flops provided corresponding to each of a plurality of logic circuit blocks constituting an arithmetic processing circuit are connected in series to form a scan chain, and the scan chain A method of designing a semiconductor integrated circuit including a scan test circuit that extracts test output data output from each of the logic circuit blocks from an output terminal of the scan chain in accordance with test input data supplied from an input terminal of A step of setting an input-side first stage flip-flop connected to the logic input terminal of the arithmetic processing circuit to an initial stage of the scan chain, and a final output stage flip-flop connected to the logic output terminal of the arithmetic processing circuit. A step of setting the final stage of the scan chain and an automatic test pattern It is characterized in that it comprises a step of automatically generating a another circuit configuration of the scan test circuit by generation tool.

BEST MODE FOR CARRYING OUT THE INVENTION

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings shown below, components that are substantially the same as or equivalent to the components shown in FIGS. 1 to 4 are given the same reference numerals. FIG. 5 shows a configuration of a semiconductor integrated circuit 100 having a scan test circuit according to the present invention. It is assumed that the semiconductor integrated circuit 100 has an AC specification (timing specification) defined, and a delay time of the logic output signal with respect to the logic input signal is required to be a predetermined value or less.

  The first flip-flop 11 on the input side of the arithmetic processing circuit connected to the logic input signal line (INPUT) to which the logic input signal is to be input is provided in the first stage of the scan chain. The flip-flop 11 is composed of a scan FF, but its input terminal D and scan-in terminal SI are short-circuited and used, and thus is substantially equivalent to a normal D-FF. A connection point between the input terminal D and the scan-in terminal SI is connected to a logic input signal line (INPUT) and a scan-in signal line (SCAN_IN1) to which a scan-in signal (test input data) is to be supplied. The output terminal Q of the scan FF 11 is connected to the subsequent logic circuit block 31 and also connected to the scan-in terminal SI of the scan FF 21.

  The output terminal Q of the scan FF 21 is connected to the input terminal of the logic circuit block 32 in the subsequent stage and to one input of the selector 40. The output signal of the logic circuit block 32 is supplied to the other input of the selector 40. The output terminal of the selector 40 is connected to a scan-out signal line (SCAN_OUT1) that is the end of the scan chain. A common clock signal is supplied to the scan FFs 11 and 21 via the clock signal line (CLK), and a common scan enable signal is supplied via the scan enable signal line (SCAN_EN).

  When a scan test is performed in such a circuit configuration, a high level scan enable signal is supplied to the scan FFs 11 and 21 via the scan enable signal line (SCAN_EN), and the scan mode is selected. Then, the scan FFs 11 and 21 select the scan-in terminal SI, and the first scan line from the scan-in signal line (SCAN_IN1) to the scan-out signal line (SCAN_OUT1) via the scan FF11, the scan FF21, and the selector 40. Configure the campus. That is, in this state, the scan FFs 11 and 21 function as shift registers.

  In this state, when the scan-in signal (test input data) is sequentially input from the scan-in signal line (SCAN_IN1) in synchronization with the clock signal, the input data is held in the scan FFs 11 and 21 constituting the shift register. .

  The data held in the scan FFs 11 and 21 are given as input signals to the logic circuit blocks 31 and 32, respectively. The logic circuit blocks 31 and 32 output a processing result corresponding to the given data. At this time, the output side of the logic circuit block 32 is selected by the selector 40, and the processing result by the logic circuit block 32 is output from the scan-out signal line (SCAN_OUT1) via the selector 40.

  Next, when a low level scan enable signal is supplied to the scan FFs 11 and 21 via the scan enable signal line (SCAN_EN), the scan FFs 11 and 21 select the input terminal D and switch the connection state to the normal mode. When a clock signal is given to the scan FFs 11 and 21 in this state, the processing result by the logic circuit block 31 is held in the scan FF 21. At this time, the output side of the scan FF 21 is selected by the selector 40, and the processing result (test output data) by the logic circuit block 31 held in the scan FF 21 is output from the scan-out signal line (SCAN_OUT1) via the selector 40. With the above operation, the scan test for the logic circuit blocks 31 and 32 is completed.

  On the other hand, the flip-flop 12 in the final output stage of the arithmetic processing circuit connected to the logic output signal line (OUTPUT) is provided in the final stage of the scan chain. The flip-flop 12 is composed of a scan FF having a scan function. The output terminal Q of the scan FF 12 is connected to the logic output signal line (OUTPUT) and to the scan-out signal line (SCAN_OUT2) that is the end of the second scan chain.

  The scan-in terminal SI of the scan FF 22 is connected to the scan-in signal line (SCAN_IN2). The output terminal Q of the scan FF 22 is connected to the subsequent logic circuit block 34 and to the scan-in terminal SI of the scan FF 23. The output terminal Q of the scan FF 23 is connected to the input terminal of the logic circuit block 35 in the subsequent stage and to the scan-in terminal SI of the scan FF 12 in the final output stage. A common clock signal is supplied to each of the scan FFs 22, 23 and 12 via a clock signal line (CLK), and a common scan enable signal is supplied via a scan enable signal line (SCAN_EN).

  When a scan test is performed in such a circuit configuration, a high level scan enable signal is supplied to the scan FFs 22, 23, and 12 via the scan enable signal line (SCAN_EN), and the scan mode is selected. Then, these scan FFs select the scan-in terminal SI, and the second scan from the scan-in signal line (SCAN_IN2) to the scan-out signal line (SCAN_OUT2) via the scan FF22, scan FF23, and scan FF12. Construct a chain. That is, in this state, the scan FFs 22, 23, and 12 function as shift registers.

  In this state, when the scan-in signal (test input data) is sequentially input from the scan-in signal line (SCAN_IN2) in synchronization with the clock signal, the input data is held in the scan FFs 22 and 23 constituting the shift register.

  The data held in these scan FFs is given as input signals to the logic circuit blocks 34 and 35, respectively. The logic circuit blocks 34 and 35 output a processing result corresponding to the given data.

  Next, when a low level scan enable signal is supplied to the scan FFs 22, 23 and 12 via the scan enable signal line (SCAN_EN), these scan FFs select the input terminal D and switch the connection state to the normal mode. When a clock signal is given to these scan FFs in this state, the processing results by the logic circuit blocks 34 and 35 are held in the scan FFs 23 and 12, respectively.

  Next, when a high level scan enable signal is supplied to the scan FFs 22, 23 and 12 via the scan enable signal line (SCAN_EN), a scan path is configured. In this state, when a clock signal is given to these scan FFs, the processing results (test output data) by the logic circuit blocks 34 and 35 are sequentially output from the scan-out signal line (SCAN_OUT2). With the above operation, the scan test for the logic circuit blocks 34 and 35 is completed.

  Next, a method for designing the semiconductor integrated circuit 100 having the scan test circuit configured as described above will be described with reference to the flowchart shown in FIG.

  First, RTL design is performed (step S1). RTL is a type of technique for describing synchronous digital circuits in integrated circuit design. In RTL, all operations in a logic circuit are described in synchronization with a clock cycle.

  Next, logic synthesis is performed (step S2). In this step, a gate circuit is automatically generated from the RTL description using a logic synthesis tool. In logic synthesis, a logic gate circuit is automatically generated by optimizing a logic gate circuit according to design constraints such as an area, a clock period, and power consumption given by a designer from an HDL description. Note that the logic synthesis tool is a part of EDA (Electronic Design Automation), which is a device that performs mounting design of a logic circuit from a description about the operation of an abstract circuit by a built-in program.

  Next, timing analysis is performed (step S3). The logic gate has a unique delay value, and the delay value of the gate circuit can be obtained by calculating the delay of the logic gate and the delay due to the wiring. In this step, a static timing analysis tool is used to verify whether the logic-synthesized gate circuit satisfies the design constraints. If the design constraint conditions are not satisfied, the RTL design is repeated.

  Next, design for testability is performed (step S4). Here, first, the first scan FF 11 on the input side of the arithmetic processing circuit is manually set to the first stage of the scan chain (step S4-1). In other words, the external connection terminal of the scan-in signal line (SCAN_IN) serving as the input terminal of the scan chain is connected to the input terminal D and the scan-in terminal SI of the scan FF 11.

  Subsequently, the scan FF 12 of the final output stage of the arithmetic processing circuit is manually set to the final stage of the scan chain (step S4-2). That is, the output terminal Q of the scan FF 12 is connected to the external connection terminal of the scan-out signal line (SCAN_OUT) serving as the output terminal of the scan chain. Thus, in the design method of the present invention, the arrangement on the scan chain is manually fixed for the flip-flops at the input side first stage and the final output stage of the arithmetic processing circuit. Thereafter, test patterns are automatically created using the automatic test pattern generation tool (ATPG) for the other components of the scan chain (step S4-3). As a result, a scan test circuit constituting one or more scan chains having the scan FF 11 as the first stage of the scan chain and the scan FF 12 as the final stage of the scan chain is automatically generated. The automatic test pattern generation tool is a device that is a part of EDA and automatically generates an IC test pattern from logic circuit information using a built-in program.

  Next, layout design is performed (step S5). Here, first, a floor plan for determining where to place which circuit block of the integrated circuit is arranged on the chip is performed, then cells are arranged on the chip, and wiring between the cells is performed. In such a layout design, an automatic layout tool that performs automatic placement and routing according to a net list of a gate circuit including floor plan information and a test pattern is used. At this time, the first-stage scan FF 11 on the input side of the arithmetic processing circuit is automatically arranged near the external connection terminal of the scan-in signal line (SCAN_IN) because it is set as the first-stage flip-flop of the scan chain. Therefore, the scan-in signal line (SCAN_IN) leading to the scan FF 11 by the automatic layout tool does not have a long path, and therefore no delay compensation is required, so that a repeater is automatically inserted on the extension line of the logic input signal line (INPUT). Can be avoided. Similarly, the scan FF 12 at the final output stage of the arithmetic processing circuit is automatically arranged near the external connection terminal of the scan-out signal line (SCAN_OUT) because it is set as a flip-flop at the final scan chain stage. Therefore, the scan-out signal line (SCAN_OUT) connected to the output terminal Q of the scan FF 12 by the automatic layout tool does not have a long path, and therefore no delay compensation is required, so that a repeater is provided on the extension line of the logic output signal line (OUTPUT). Can be automatically inserted. Note that the automatic layout tool is a part of EDA and is a semiconductor that automatically places macrocells based on macrocell connection information (that is, logic circuit design results) by built-in program and performs automatic wiring between them. A device that automatically generates a chip layout. Through the above steps, the design of the semiconductor integrated circuit 100 having the scan test function of the present invention is completed.

  As is apparent from the above description, according to the design method of the present invention, in the test pattern design stage, the flip-flops at the input stage first stage and the final output stage of the arithmetic processing circuit are manually set as the first stage and last stage of the scan chain. After fixing the placement on the scan chain by setting, the test pattern is generated by the automatic test pattern generation tool. Therefore, the first flip-flop on the input side at the layout design stage using the automatic placement and routing tool Is necessarily arranged near the external connection terminal of the scan-in signal line (SCAN_IN), and the flip-flop 12 at the final output stage is necessarily arranged near the external connection terminal of the scan-out signal line (SCAN_OUT). . As a result, the wiring of the scan-in signal line (SCAN_IN) connected to the scan FF 11 and the wiring of the scan-out signal line (SCAN_OUT) connected to the scan FF 12 do not become a long path, and these wirings are formed short. Therefore, since no delay compensation is required, it is possible to avoid the repeater being automatically inserted on the logic input signal line (INPUT) and the logic output signal line (OUTPUT). This facilitates achievement of the AC specifications of the arithmetic processing circuit. Further, since these flip-flops are constituted by scan FFs and taken into the scan chain, the constituent parts of the arithmetic processing circuit (that is, the logic circuit in FIG. 2) that has not been subjected to the scan test in the conventional circuit system. Since the blocks 31 and 35) are also subjected to the scan test, an improvement in the failure detection rate can be expected as compared with the conventional circuit. That is, by designing the semiconductor integrated circuit by the above method, it is possible not only to satisfy the AC specifications of the arithmetic processing circuit but also to solve the problem of a significant decrease in the failure detection rate in the conventional circuit system.

It is a figure which shows the structure of a scan flip-flop and a scan test circuit. It is a figure which shows the structure of the conventional integrated circuit which has the conventional scan test circuit in case the AC specification of an arithmetic processing circuit is prescribed | regulated. (A) is a figure which shows the circuit structure after the pattern layout at the time of comprising the flip-flop of the input side first stage by the flip-flop which has a scan function. (B) is a diagram showing a circuit configuration after pattern layout when the first flip-flop on the input side is configured by a D flip-flop. (A) is a figure which shows the circuit structure after the pattern layout at the time of comprising the flip-flop of a final output stage by the flip-flop which has a scan function. (B) is a diagram showing a circuit configuration after pattern layout when the flip-flop at the final output stage is configured by a D flip-flop. It is a figure which shows the structure of the semiconductor integrated circuit which has the scan test circuit based on this invention. 3 is a flowchart showing a method for designing a semiconductor integrated circuit having a scan test circuit according to the present invention.

Explanation of symbols

11 First-stage scan FF on the input side
12 Scan FF at the final output stage
21-23 Scan FF
31-35 Logic circuit block

Claims (4)

A plurality of flip-flops provided corresponding to each of the plurality of logic circuit blocks constituting the arithmetic processing circuit are connected in series to form a scan chain, and the test input data supplied from the input terminal of the scan chain In response, a test method for a semiconductor integrated circuit including a scan test circuit that extracts test output data output from each of the logic circuit blocks from an output terminal of the scan chain,
Setting an input-side first stage flip-flop connected to a logic input terminal of the arithmetic processing circuit to the first stage of the scan chain;
Setting the final output stage flip-flop connected to the logic output terminal of the arithmetic processing circuit to the final stage of the scan chain;
And automatically generating another circuit configuration of the scan test circuit by an automatic test pattern generation tool.   2. The method for designing a semiconductor integrated circuit according to claim 1, further comprising a step of automatically generating a pattern layout of a semiconductor chip corresponding to the scan test circuit and the arithmetic processing circuit by an automatic layout tool.   2. The semiconductor integrated circuit according to claim 1, wherein the first flip-flop on the input side is connected to an input terminal of the scan chain, and the flip-flop of the final output stage is connected to an output terminal of the scan chain. Circuit design method.   4. The input-side first-stage flip-flop and the final-output-stage flip-flop are configured by flip-flops having a scan function that configures the scan chain according to a control signal. A design method of a semiconductor integrated circuit according to one.

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