JPH10262246A - System decoder and dynamic image decoder using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a frame memory capacity by using synchronization pulses or pulses generated by detecting matching as display image data read start pulses. SOLUTION: A control circuit 37A counts a time Δ after receiving matching pulses EQ until receiving read start pulses ESYNC by clock pulses CLK, activates loading signals to a counter 40 at the timing of the read start pulses ESTNC when the Δ or T-Δ is an unneglectable value more than a set value and loads a presentation time stamp(PTS) to the counter. The control circuit 37A reads the PTS and read start address ADR of an image to be displayed next from a PTS/ADR table register 36. A picture PIC1 is read from a frame memory 14 at the time of PTS=PTS1 at t=t1 and the read of the picture PIC2 is started from the frame memory 14 at the time of becoming PTS=PTS2 at t=t2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a system decoder and a moving picture decoding apparatus using the same.

[0002]

2. Description of the Related Art FIG. 5 shows a schematic configuration of an MPEG AV decoder. The packet multiplexed stream DAT is supplied to the system decoder 10, where a control signal is separated, a signal to be described later is generated based on the control signal, and the demultiplexer 11 is switched and controlled, so that the encoded image data VDAT0 and The encoded audio data ADAT0 is separated.

The coded image data VDAT0 is written into a memory in a buffer circuit 12, and is stored in a system decoder 10
In response to the read start pulse DSYNC of the frame period from, the reading of the encoded image data VDAT1 is started from the read start address DADR of this memory. The read encoded image data VDAT1 is supplied to the video decoder 13 and decoded, and is written into the frame memory 14 as image data VDAT2. If the decoded image data VDAT2 is for a P picture or a B picture, the reference image data V
DAT3 is read out, predicted image data is generated in the video decoder 13, and the decoded image data VDAT2 is decoded.
Is used to generate In response to the frame period read start pulse ESYNC from the system decoder 10, the video decoder 13 starts reading the display image data VDAT4 from the read start address ADR of the frame memory 14.

The display image data VDAT4 is format-converted by a video output circuit 15, converted into an analog signal, and a vertical synchronization pulse VS from a system decoder 10.
The YNC is combined to generate a video signal VID. The audio data ADAT0 is sequentially supplied to the buffer circuit 22, the audio decoder 23, the frame memory 24, and the audio output circuit 25, and the signals ADAT1, ADAT
2, AVDAT4, AUD, DADRA, FSYNC,
ADRA and GSYNC are signals VD on the video side, respectively.
AT1, VDAT2, VDAT4, VID, DADR,
It supports DSYNC, ADR, and ESYNC.

As shown in FIG. 6B, for example, a packet multiplex stream DAT is composed of n packets 1 to n of variable length.
, A packet header is arranged at the beginning of the packet to form one pack. For example, packet 1 is video, packet 2 is audio, and packet n is video. One pack contains video and audio data for substantially the same amount of time. The pack header includes a system clock reference SCR, and each packet includes a stream ID, a decoding time stamp D
TS and presentation time stamp PTS are included.

FIG. 6A shows a system decoder 1 shown in FIG.
0 shows a main part configuration. The difference between the system clock reference SCR and the system time clock STC output from the counter 32 is calculated by the subtraction circuit 31, and the difference is converted into an analog signal by the D / A converter 33. The signal is supplied to the oscillator 35. Clock pulse CLK from voltage controlled oscillator 35
Is counted by the counter 32. The counter 32 is loaded with the first system clock reference SCR,
At this time, the output of the subtraction circuit 31 becomes 0, and the frequency of the clock pulse CLK becomes a standard value. Subtraction circuit 31, D /
The A converter 33, the low-pass filter 34, the voltage-controlled oscillator 35, and the counter 32 form a PLL, whereby a continuous system time clock STC is generated from a discontinuous system clock reference SCR for each pack.

[0007] Presentation time stamp PTS
Is the display image data VDAT from the frame memory 14.
4 is supplied to the PTS / ADR table register 36. The PTS is stored in the frame memory 14
And the control circuit 37 sets the PTS to the read start address ADR.
Then, the PTS / ADR table register 36 is written in correspondence with the PTS / ADR table register 36, and then the PTS corresponding to the display image data VDAT4 to be read from the frame memory 14 is read. This PTS is compared with the system time clock STC by the comparator 38, and the read start pulse ESYNC is output from the comparator 38 when the system time clock STC matches the PTS. This read start pulse ESYN
In synchronization with C, the control circuit 37 sends the next PTS to PTS / A
It is read from the DR table register 36.

Further, a system time clock STC is supplied to a decoding circuit (not shown) by a decoding time stamp DTS.
, The read start pulse DS
YNC is output. Decoded image data VDAT2 is B
In the case of a picture, the video decoder 13 writes the decoded image data VDAT2 in the frame memory 14 with reference to the two pictures stored in the frame memory 14, and reads out the display image data VDAT4 of the B picture from the frame memory 14. Therefore, conventionally, the frame memory 14 having a capacity of at least three frames
Was used. However, since the B picture is read out as the display image data VDAT4 while being written to the frame memory 14 as the decoded image data VDAT2, the buffer capacity for the B picture in the frame memory 14 is smaller than one frame in principle. May be
By reducing this capacity, it becomes possible to reduce the manufacturing cost of the video decoding device.

[0009]

However, when the capacity of the frame memory 14 is reduced, the buffer capacity is reduced, so that the read start time of the display image data VDAT4 is set to PTS.
Faster, the PTS cannot be used, and the display image data V
The timing between the reading of DAT4 and the vertical synchronization pulse VSYNC is shifted. As a result, the capacity of the frame memory 14 cannot be reduced.

An object of the present invention is to provide a system decoder capable of reducing the capacity of the frame memory 14 and a video decoding device using the same, in view of the above problems.

[0011]

According to the first aspect of the present invention, there is provided a system decoder comprising: a circuit for generating a clock pulse; a counter for counting the clock pulse and outputting the counted value as a system time clock; A synchronizing pulse generation circuit for generating a synchronizing pulse having a frame period based on a clock pulse, a storage unit for temporarily storing a supplied presentation time stamp, and a presentation time stamp from which the system time clock is read from the storage unit And a control circuit for reading the presentation time stamp corresponding to the image reproduction order from the storage means and loading the presentation time stamp into the counter in response to the synchronization pulse. Has,
The synchronization pulse or a pulse generated by detecting the coincidence is used as a display image data reading start pulse. According to this system decoder, even if the capacity of the frame memory is reduced as compared with the conventional system and the read start time of the display image data from the frame memory is shifted from the conventional presentation time stamp, an appropriate system time is set according to the shift. Since the clock is generated, as a result, the capacity of the frame memory can be reduced, which greatly contributes to the reduction in the manufacturing cost of the video decoding device.

According to a second aspect of the present invention, in the system decoder according to the first aspect, the control circuit includes a time Δ from the detection of the coincidence to the generation of the synchronization pulse, or a time Δ (frame period T) −Δ When よ り 大 き い is greater than the set value,
The presentation time stamp is loaded into the counter. According to this system decoder, there is an effect that the shift time is automatically adjusted even if the shift time Δ or (T−Δ) becomes too large to be ignored for some reason.

According to a third aspect of the present invention, there is provided the system decoder according to the first or second aspect, further comprising a selector for selecting one of a system clock reference and a presentation time stamp read from the storage means and supplying the selected time stamp to the counter. The control circuit causes the selector to select the system clock reference and then the presentation timestamp, and loads the output of the selector into the counter in response to the synchronization pulse.

According to a fourth aspect of the present invention, in the third aspect, the control circuit causes the selector to select the system clock reference supplied first and then select the presentation time stamp. According to this system decoder, there is an effect that the adjustment of the shift time is performed immediately after the start of decoding.

According to a fifth aspect of the present invention, in the system decoder according to any one of the first to fourth aspects, the circuit for generating the clock pulse is such that a value of a counter for counting the clock pulse coincides with a value of the system clock reference. A PLL circuit that performs feedback control of the frequency of the clock pulse so as to perform the above operation.

According to a sixth aspect of the present invention, in the system decoder according to any one of the first to fourth aspects, the circuit for generating the clock pulse is a free-running clock generation circuit. According to this system decoder, the configuration of the system decoder is simplified as compared with the case of claim 5, and the structure of claim 5
The effect that the period of the clock pulse can be made more accurate than in the case of the feedback control described above.

According to a seventh aspect of the present invention, there is provided a moving picture decoding apparatus, comprising: a buffer circuit for temporarily storing supplied image data encoded by the MPEG system and reading out the encoded image data in synchronization with an encoded image reading start pulse; Decoding the coded image data read from the frame memory and the buffer circuit and writing the decoded image data to the frame memory; reading the image data from the frame memory for reference; A video decoder for synchronously reading out the image data from the frame memory for display, and a system decoder according to any one of claims 1 to 6.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a main configuration of a system decoder 10A according to a first embodiment of the present invention, corresponding to FIG.

The clock pulse CLK and the system time clock STC are, as in FIG.
1, generated by the D / A converter 33, the low-pass filter 34, the voltage-controlled oscillator 35, and the PLL of the counter 32. The clock pulse CLK is supplied to a clock input terminal of an N-ary counter 391 and counted, and the counted value is supplied to decoders 392 and 393. The decoders 392 and 393 detect that the count value coincides with a predetermined value, and detect the synchronization pulse USSYNC and the vertical synchronization pulse V, respectively.
Generate a SYNC pulse. The period of the sync pulses USSYNC and VSYNC is equal to the field period and VSYNC
NC is equal to USSYNC delayed by δ shown in FIG. The synchronization pulse USSYNC is frequency-divided by で in a 分 frequency division / leading edge detection circuit 394, the rising edge of the pulse is detected and the pulse is shortened, and a read start pulse ESYNC as shown in FIG. Is supplied to the video decoder 13.

The clock pulse CLK is also supplied to the clock input terminal of the counter 40 and counted.
It is supplied to the comparator 38 as a system time clock STCA. Comparator 38 compares this STCA with PTS / AD
A comparison is made with the PTS from the R table register 36, and when they match, a match pulse EQ is output. STCA,
Used in processing video data. Since the decoding time stamp DTS is not always present, the read start pulse DSYNC is
It is generated with a predetermined phase difference from YNC.

The selector 41 is supplied with PTS and SCR, one of which is selected and supplied to the data input terminal of the counter 40. The control circuit 37A is supplied with the clock pulse CLK, the SCR, the read start pulse ESYNC, and the coincidence pulse EQ. Based on these, the control circuit 37A makes the counter 32, the PTS / ADR table register 3
6, the counter 40 and the selector 41 are controlled as follows.

The selector 41 is first switched to the SCR side. When detecting the first SCR, the control circuit 37A activates a load signal supplied to the counters 32 and 40 to load the SCRs on the counters 32 and 40. As a result, the output of the subtraction circuit 31 becomes 0, and the frequency of the clock pulse CLK becomes a standard value. Further, at t <t0 (t is real time) in FIG.
It becomes STCT.

Immediately after the loading, the control circuit 37A
The selector 41 is caused to select the PTS. Control circuit 37
A, after receiving the coincidence pulse EQ, the read start pulse ES
The time Δ shown in FIG. 2 until receiving the YNC is counted by the clock pulse CLK, and when Δ or T−Δ is equal to or greater than a set value that cannot be ignored, the load signal to the counter 40 is activated at the timing of the read start pulse ESYNC. ,
The PTS is loaded into the counter 40. Here, T is a frame period. In FIG. 2, when t = t0, the picture PI
The PTS of C0 = PTS0 is loaded into the counter 40,
The value of STCA shifts from the value of STC.

In FIG. 6, the buffer circuit 12 starts reading DAT1 from the read start address DADR of the memory in the buffer circuit 12 in response to the read start pulse DSYNC. The video decoder 13 starts reading the display image data VDAT4 from the read start address ADR of the frame memory 14 in response to the read start pulse ESYNC.

Next, the control circuit 37A sends a PTS / ADR table register 36 with the PT of the next image to be displayed.
S and the read start address ADR are read from the PTS / ADR table register 36. In FIG. 2, t = t1
Becomes PTS = PTS1, and the reading of the picture PIC1 from the frame memory 14 is started.
TS = PTS2, and reading of the picture PIC2 from the frame memory 14 is started.

According to the first embodiment, the capacity of the frame memory 14 is reduced from the conventional three frames to a value larger than two frames and smaller than three frames, and the display image data VDAT4 is read from the frame memory 14. Even if the start time is shifted from STC = PTS, the time from the read start pulse ESYNC to the vertical synchronization pulse VSYNC becomes almost equal to the optimum value δ, and as a result, the capacity of the frame memory 14 can be reduced.

The system time clock STCA is set to STC
Therefore, if reading of the encoded image data VDAT1 from the buffer circuit 12 is delayed, the storage capacity of the buffer circuit 12 needs to be increased, but significantly compressed data is written in the buffer circuit 12. Therefore, the amount of increase is small compared to the amount of decrease from the capacity of the frame memory 14 for three frames.

[Second Embodiment] FIG. 3 shows a system decoder 10 according to a second embodiment of the present invention, corresponding to FIG.
2 shows a configuration of a main part of B. In this system decoder 10B, a self-running clock generator 42 is used instead of the PLL circuit including the subtraction circuit 31, the D / A converter 33, the low-pass filter 34, the voltage control oscillator 35, and the counter 32 in FIG. This simplifies the configuration of the system decoder 10B and makes the cycle of the clock pulse CLK more accurate than in the case of feedback control. Since the control circuit 37B does not need to generate a load signal for the counter 32 in FIG. 1, the configuration is simpler than the control circuit 37A. The coincidence pulse EQ output from the comparator 38 is used as a read start pulse ESYNC.

The other points are the same as those in FIG. [Third Embodiment] FIG. 4 shows a main configuration of a system decoder 10C according to a third embodiment of the present invention, corresponding to FIG. The time δ in FIG. 2 is smaller than 1 ms and depends on the configuration of the video output circuit 15 in FIG.
Depending on the processing speed, the time δ can be ignored.
Therefore, in the system decoder 10C, the decoder 393 in FIG. 3 is omitted, and the vertical synchronization pulse VSYNC is also used as the synchronization pulse USSYNC in FIG. Also,
By supplying one bit of the data output of the counter 40, for example, the most significant bit to the N-ary counter 391 as the clock φ, the number of bits of the N-ary counter 391A is made smaller than that of the N-ary counter 391 in FIG. Further, the selector 41 shown in FIG.
Is supplied to the data input terminal. Since the control circuit 37C does not need to control the selector 41, the configuration is simpler than the control circuit 37B of FIG.

The control circuit 37C counts the time Δ shown in FIG. 2 from the reception of the coincidence pulse EQ to the reception of the read start pulse ESYNC by the clock pulse CLK.
When −Δ is equal to or more than the set value, the read start pulse ESYN
At timing C, the load signal to the counter 40 is activated to load the PTS into the counter 40. The control circuit 37C then sends the PTS / ADR table register 3
In step 6, the PTS of the next image to be displayed and the read start address ADR are read from the PTS / ADR table register 36.

The present invention includes various other modifications. For example, the PTS / ADR table register 36
Without storing the read start address ADR in the PTS / AD
In the R table register 36, the address of the register in which the PTS is stored corresponds to the read start address ADR, or the P address is stored in another part, for example, a part of the frame memory 14.
The configuration may be such that the read start address ADR is stored in accordance with the order in which the PTSs are stored in the TS / ADR table register 36.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a system decoder according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an operation of adjusting a system time clock.

FIG. 3 is a block diagram illustrating a main configuration of a system decoder according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a main configuration of a system decoder according to a third embodiment of the present invention.

FIG. 5 is a block diagram illustrating a schematic configuration of a conventional AV decoding device.

FIG. 6A is a block diagram illustrating a configuration of a main part of a conventional decoder, and FIG. 6B is a diagram illustrating a schematic format of a packet multiplexed stream.

[Explanation of symbols]

 10, 10A to 10C System decoder 11 Demultiplexer 12, 22 Buffer circuit 13 Video decoder 14, 24 Frame memory 15 Video output circuit 23 Audio decoder 25 Audio output circuit 31 Subtraction circuit 32, 40 Counter 33 D / A converter 34 Low-pass filter 35 voltage controlled oscillator 36 PTS / ADR table register 37, 37A-37C control circuit 38 comparator 391 N-ary counter 392, 393 decoder 41 selector

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H03M 7/30 H03M 7/30 Z (72) Inventor Yoshihiko Kamo 4-1-1 1-1 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Stock Inside the company (72) Inventor Katsuki Miyawaki 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (7)

[Claims] 1. A circuit that generates a clock pulse, a counter that counts the clock pulse, and outputs the counted value as a system time clock, and a synchronization pulse generator that generates a synchronization pulse of a frame period based on the clock pulse. Circuit, storage means for temporarily storing the supplied presentation time stamp, comparison circuit for detecting that the system time clock matches the presentation time stamp read from the storage means, and response to the synchronization pulse. And a control circuit for reading the presentation time stamp corresponding to the image reproduction order from the storage means and loading the presentation time stamp into the counter, and detecting and generating the synchronization pulse or the coincidence. The pulse to be read is the display image data read start A system decoder characterized in that it is used as a virus. 2. The control circuit according to claim 1, wherein the time Δ from the detection of the coincidence to the generation of the synchronization pulse or the time {(frame period T) −Δ} is greater than a set value, 2. The system decoder according to claim 1, wherein a stamp is loaded into said counter. 3. A selector for selecting one of a system clock reference and a presentation time stamp read from the storage means and supplying the selected time stamp to the counter, wherein the control circuit controls the selector for the system clock reference. 3. The system decoder according to claim 1, further comprising: selecting the presentation time stamp, and loading the output of the selector into the counter in response to the synchronization pulse. 4. The system decoder according to claim 3, wherein the control circuit causes the selector to select the system clock reference supplied first and then select the presentation time stamp. 5. The circuit for generating a clock pulse is a PLL circuit for feedback-controlling the frequency of the clock pulse so that the value of a counter that counts the clock pulse matches the value of the system clock reference. The system decoder according to any one of claims 1 to 4, wherein: 6. The circuit for generating the clock pulse,
The system decoder according to claim 1, wherein the system decoder is a free-running clock generation circuit. 7. A buffer circuit for temporarily storing the supplied image data encoded by the MPEG system and reading out the encoded image data in synchronization with an encoded image reading start pulse, a frame memory, and the buffer circuit. The encoded image data read from is decoded and written into the frame memory, the image data is read out from the frame memory for reference, and the image data is read out from the frame memory in synchronization with the display image data read start pulse. A video decoder comprising: a video decoder for reading image data for display; and the system decoder according to claim 1.