KR19980079615A - Image data processing method and apparatus, moving picture decoder and system decoder using same - Google Patents

Abstract

The switching circuits 21 to 24 are provided so as to select whether or not to transfer the image data DAT2 or DAT5 to the letter box conversion circuit 20 before or after writing the image data to the frame memory 14A. The coded image data of the B picture is divided into m logical banks (m? 2), and the data is temporarily stored in the p physical bank (2 < p < m) secured in the frame memory 14A, and read in display order. When the winding mode is the double speed reproduction mode, the decoder 27A decodes the coded image data DAT0 at twice the normal speed, records the data DAT2 in the frame memory 14, and simultaneously retrieves the data DAT2 from the reference memory frame. The data DAT4 is read out, and the decoder reads out the decoded picture data DAT5 from the frame memory 14 by one picture at a normal speed. The system decoder 110A includes a clock generator 142, a counter for counting clock pulses and supplying the count value as an STCA, a synchronous pulse generators 1391A, 1393, and 1394 for generating VSYNC and ESYNC in accordance with the clock CLK, and display. A table register 136 for temporarily storing PTSs according to the read start address, a comparator 138 for detecting that the STC coincides with the PTS read out from the table register 136, and reading the PTSs in the order of the original picture. By controlling the address ADR from register 136, when Δ and (T−Δ) are greater than the set value (where T is the frame period and Δ is the time from EQ to ESYNC pulse of comparator 138), And a control circuit which loads the counter 140 at the timing of the ESYNC pulse.

Description

Image data processing method and apparatus, moving picture decoder and system decoder using same

The present invention relates to a method and apparatus for processing image data, and a moving picture decoder and a system decoder using the same.

Fig. 15 schematically shows the configuration of a conventional picture decoder which decodes coded picture data DAT0 in accordance with the MPEG method for displaying video data. The encoded image data DAT0 is converted into quantized DCT coefficients by the variable length decoder circuit 10, converted into DCT coefficients by the inverse quantization circuit 11, and converted into image data DAT1 by the inverse DCT circuit 12.

If the DAT1 is an I picture (internally coded picture), it passes the addition circuit 13 as it is, and if the DAT1 is a P picture (forward prediction coded picture) or a B picture (bidirectional predictive coded picture), the DAT1 is a prediction error. The data is added to the predictive image data DAT3 from the memory control / prediction image generation circuit 15 by the addition circuit 13. The predictive image generation circuit is a circuit that performs motion compensation and predictive decoding. The output of the addition circuit 13 is temporarily stored in the frame memory 14 as the decoded image data DAT2. The memory control / prediction picture generation circuit 15 reads the reference decoded picture data DAT4 from the frame memory 14 based on the prediction mode and the motion vector separated by the variable length decoder circuit 10 and predicts the picture data DAT3. Is generated and supplied to the addition circuit 13.

The reference picture is a past I picture or P picture when the picture data DAT1 is a P picture. When the DAT1 is a B picture, the reference picture is a past I picture or a P picture and a future I picture or a P picture. Here, the expressions "past" and "future" indicate the order of the original image before encoding.

The frame memory 14 has a storage capacity of three frames in total, two frames for the reference picture and one frame for the buffer.

Fig. 16 shows the image types of the image data DAT0 supplied sequentially during decoding and the image storage states S1 to S9 in the frame memory 14. In FIG. 16, I, P, and B have shown the image type. The numbers assigned to these picture types indicate the temporal order of the picture data DAT0.

DAT0 indicates images I1, B2, B3, P4, B5, B6,... The variable length decoder circuit 10 is supplied to the variable length decoder circuit 10 in this order, and the image data DAT2 is temporarily stored in the frame memory 14 in the same order. This temporarily stored image is read out as display image data DAT5 in the order of the original image before encoding. The B picture is read as display image data DAT5 without reference, and the I picture or P picture is reproduced after the B picture up to the next I picture or P picture before playback. That is, the display image data DAT5 is represented by the images B2, B3, I1, B5, B6, P4, ... shown in parentheses in FIG. Are read from the frame memory 14 in the order of.

The frame memory 14 has a capacity of three frames as described above, but it is desirable to reduce the capacity as much as possible to reduce the manufacturing cost. Therefore, focusing on the fact that two data memories for an I picture or a P picture are divided into 2N slots, and the B picture is read as the display picture data DAT5 without being referred to, N + 4 for the B picture. An image processing apparatus that performs the following processing using a data memory having two slots and a slot management memory for storing 2N + 6 slot numbers has been proposed (Japanese Patent Laid-Open No. 8-298666).

(1) Initial values of 0 to N + 3 are stored in N + 4 words starting from the head of the slot management memory. Initial values 0 and N + 4 are stored in the write pointer WP and the read pointer RP, respectively.

(2) The slot number is read by addressing the slot management memory from the contents of the write pointer WP, and the slot number is read by addressing the slot management memory at (contents of the write pointer WP) +1.

(3) In the data memory, data is recorded in the slot of the read two slot numbers. In addition, the order of reading the slots of the data memory is predicted to store the two slot numbers at different addresses of the slot management memory, respectively.

(4) Increment only two write pointers.

(5) The slot number is read by addressing the slot management memory from the contents of the read pointer RP, and the slot number is read by addressing the slot management memory at (contents of the read pointer RP) +1.

(6) In the data memory, data is read from the two read slot numbers.

(7) Only two read pointers are incremented, and this process is repeated.

However, since N = 480 / (8 × 2) = 30, for example in the case of an image of 480 lines, the slot management memory should be able to store 2N + 6 = 66 slot numbers. In addition, the configuration of the apparatus is complicated because it is necessary to predict the slot read order of the data memory. Furthermore, since the two data memories for I picture or P picture are divided into 2N slots each, the configuration becomes more complicated.

Lateral: When an image having a length = 16: 9 is output without distortion to a normal CRT having a 4: 3 aspect ratio, as shown in FIG. 17, a letter box for reducing the image 16 to the image 17 It is necessary to perform the conversion on the image 16. The hatched lines 181 to 182 and the lines 183 to 184 represent black display portions on the CRT.

In Fig. 15, when the display mode is the reduced mode, the switching circuit 19 is switched to the letter box conversion circuit 20 side, and the display image data DAT5 read out from the frame memory 14 is the letter box conversion circuit 20. In FIG. ) Is reduced as described above, and passes through the switching circuit 19 to be taken out as the display image data DAT5. When the display mode is the normal mode, the switching circuit 19 switches to the output side of the frame memory 14, and the display image data DAT5 passes through the switching circuit 19 and is taken out as the display image data DAT6. In the circuit not shown in the figure, the display image data DAT6 is converted in format and converted into analog values to be a video signal for display.

In Fig. 17, when the display mode is the normal mode, it is sufficient to read the display image data DAT5 for one image from the frame memory 14 during the period from the line 181 to the line 184. In the case where the display mode is the reduced mode, the display image data DAT5 for one image must be read from the frame memory 14 and letterbox converted in a shorter period from the line 182 to the line 183. As a result, higher speed processing is required than in the normal mode, which increases the manufacturing cost.

FIG. 18A shows the relationship between the image string encoded by the MPEG method and the display image string decoded and rearranged. The six coded pictures constitute one GOP (Group 0f pictures).

Conventionally, in the case of fast forward display, only I pictures or only I pictures and P pictures are transferred from the buffer memory to the decoder, and B pictures are not displayed. In Fig. 18A, if the B image is skipped, I0, P2, P4, I6,... The images are displayed in the order of and the mode becomes the double speed mode.

For example, since the object is constantly moving and B picture coding cannot be performed on a moving picture having a large motion vector, only an I picture and a P picture are used as shown in Fig. 18B. In this case, the moving image display in the double speed mode cannot be performed by the conventional method of skipping the B image. It is possible to display only the I image, but in the case as shown in Fig. 18B, the moving image is displayed in the 6x mode instead of the 2x mode.

Fig. 19 shows a schematic configuration of an AV decoder of MPEG-2 system.

The packet multi-stream BS is supplied to the system decoder 110 so that the control signal is separated. Signals described later are generated in accordance with this control signal, and the multiplexer 111 is switched to separate the encoded image bit stream VBS and the encoded audio bit stream ABS.

The VBS is written to the memory in the buffer circuit 112. In response to the read start pulse DSYNC from the system decoder 110, reading of the coded image data DAT0 is started from the start address BR of this memory.

The DAT0 is supplied to the video decoder 113 and decoded, and recorded in the frame memory 14 as the image data DAT2. In response to the read start pulse ESYNC of the frame period from the system decoder 110, the video decoder 113 starts reading the display image data DAT5 from the read start address ADR of the frame memory 14.

The DAT5 is converted in format by the display output circuit 115 and converted into an analog signal, and the vertical sync pulse VSYNC from the system decoder 110 is synthesized to generate the video signal VS.

The voice bit stream ABS passes through the buffer circuit 122 and the audio decoder 123 and is supplied to the audio output circuit 125. Signal AS corresponds to signal VS.

In the packet multi-stream BS as shown in Fig. 20B, for example, packet headers are arranged at the head of n packets 1 to n of variable length to form one pack. For example, packet 1 is video, packet 2 is audio, and packet n is video. In one pack, the video and audio data are stored for about the same time. The pack header contains the system clock reference SCR. Each packet contains a stream ID, a decoding time stamp DTS, and a presentation time stamp PTS.

FIG. 20A illustrates a main part of the system decoder 110 of FIG. 19.

The subtraction circuit 131 calculates the difference between the SCR and the system time clock STC that is the output of the counter 132. This is converted into an analog signal by the D / A converter 133 and passed through the low pass filter 134 to the voltage controlled oscillator 135. The clock pulse CLK from the voltage controlled oscillator 135 is counted by the counter 132. The first SCR is loaded into the counter 132. At this time, the output of the subtraction circuit 131 becomes 0, and the frequency of the CLK becomes a standard value. A PLL is formed of the subtraction circuit 131, the D / A converter 133, the low pass filter 134, the voltage controlled oscillator 135, and the counter 132, thereby continuing from every pack discontinuous SCR. System time clock STC is generated.

The PTS is the read start time of DAT5 from the frame memory 14 and is supplied to the PTS / ADR table register 136. The PTS corresponds to the read start address ADR of the image data in the frame memory 14. The control circuit 137 writes the PTS in the PTS / ADR table register 136 in association with the read start address ADR, and reads the next PTS corresponding to the next DAT5 to be read next from the frame memory 14. This PTS is compared with the STC in the comparator 138 so that the comparator 138 outputs ESYNC when the STC matches the PTS. In synchronization with this ESYNC, the control circuit 137 reads the next PTS from the PTS / ADR table register 136.

When the comparison circuit (not shown) detects that the STC matches the DTS, the DSYNC is output.

When the DAT2 is a B picture, the video decoder 113 records the DAT2 in the frame memory 14 while referring to the two pictures stored in the frame memory 14, and this B picture as the VDAT4 from the frame memory 14. Since it is necessary to read DAT2, the frame memory 14 having at least three frame capacities has been conventionally used. However, since the B picture is recorded in the frame memory 14 as DAT2 and read out as DAT5, in principle, the buffer capacity for the B picture in the frame memory 14 is at least better than one frame. By reducing this capacity, it is theoretically possible to reduce the manufacturing cost of the moving picture decoder.

However, if the capacity of the frame memory 14 is reduced, the buffer capacity is reduced, so that the read start time of the display image data DAT5 must be earlier than the PTS, so that the PTS cannot be used, and the display image from the frame memory 14 is lost. The timing of reading the data DAT5 and the timing of the vertical synchronizing pulse VSYNC are shifted. As a result, the capacity of the frame memory 14 cannot be reduced.

It is therefore an object of the present invention to provide an image data processing method and apparatus which can reduce the manufacturing cost by eliminating the need to reduce the memory capacity or increase the operating frequency for image reduction processing with a simpler configuration. .

It is still another object of the present invention to provide a moving picture decoder that enables picture reproduction in double-speed winding mode even when no B picture exists.

Another object of the present invention is to provide a system decoder capable of reducing the capacity of the frame memory 14 and a moving picture decoder using the same.

1 is a schematic structural diagram of a moving picture decoder according to a first embodiment of the present invention;

2 is a schematic structural diagram of a moving picture decoder according to a second embodiment of the present invention;

3 is a block diagram showing an example of the configuration of a bank management circuit shown in FIG. 2;

4 is an explanatory diagram of image decoding processing by the apparatus of FIG. 2;

5A to 5G are explanatory diagrams of bank allocations of B pictures.

6 is a time chart showing the operation of the circuit shown in FIG.

7 (a) to 7 (c) are explanatory diagrams for slow reproduction of a B image.

Fig. 8A is a block diagram showing the schematic configuration of a moving picture decoder according to the third embodiment of the present invention.

FIG. 8B is a block diagram showing the bank address control unit in FIG. 8A; FIG.

Fig. 9 is a time chart showing the operation of a moving picture decoder in the constant speed mode.

Fig. 10 is a time chart showing the operation of a moving picture decoder in double speed mode.

11 is a block diagram showing a schematic configuration of a system decoder according to a fourth embodiment of the present invention.

12 is an explanatory diagram of an adjustment operation of a system time clock.

Fig. 13 is a block diagram showing the configuration of main parts of a system decoder according to a fifth embodiment of the present invention.

Fig. 14 is a block diagram showing the configuration of main parts of a system decoder according to a sixth embodiment of the present invention.

Fig. 15 is a block diagram showing a schematic configuration of a conventional picture decoder.

FIG. 16 is an explanatory diagram of image decoding processing by the apparatus shown in FIG. 15; FIG.

17 is an explanatory diagram showing a conventional letter box conversion.

18 (a) and 18 (b) are explanatory diagrams of a problem of the prior art of decoding an encoded image in a fast-forward mode according to the MPEG system.

Fig. 19 is a block diagram showing a schematic configuration of a conventional AV decoder.

20A is a block diagram showing the structure of a conventional decoder main part.

20B is a diagram illustrating a schematic format of a packet multiple stream.

* Explanation of symbols for the main parts of the drawings

10 variable length decoder 11: inverse quantization circuit

12 reverse DCT circuit 13 addition circuit

14,14A: Frame Memory

15,15A: Memory control / prediction image generation circuit

20: letter box conversion circuit 21 to 24: switching circuit

25: buffer memory control circuit 251, 291: address counter

26: buffer memory 27: decoder

28: decoding / display control circuit 281: start address register circuit

29: frame memory control circuit 30: bank management circuit

31: display circuit 32: physical bank number calculator

33: state physical bank detector 34: physical bank allocation register

35: physical bank allocator 36: logical / physical bank number converting unit

37: physical bank opening portion MR1 to MR4: mapping register

L1N: Write logic bank number L2N: Read logic bank number

RQ2: Physical bank allocation request DAT0: Encoded image data

DAT1: image data DAT2, DAT2A: decoded image data

DAT3: predictive image data DAT4: decoded image data for reference

DAT5: Displayed decoded image data CI1, CI2: Control information

PW: Buffer memory write start address

BR: Buffer memory read start address

FW: Frame memory write start address

FR1, FR2: Frame memory reference picture read start address

FR3: Frame memory display image read start address

PRQ: Stop playback request signal SRQ: Slow playback request signal

1 / N: Playback speed DRQ: Decoding start command

In the image data processing apparatus according to the first aspect of the present invention, m = (image data amount for one frame) / (image data amount for one bank), and m and p are integers satisfying 2 ≦ pm. In this case, the memory having the storage area of the p bank for image data storage, and the image data for one frame is read in m banks in order to record image data in the memory or to read decoded image data recorded in the memory. A first control circuit for outputting a logical bank number when the logical bank number is assigned to each bank by dividing by. And an empty space when the physical bank number is assigned to each bank of the p bank storage area. Assigned to a state physical bank number, and the allocated physical bank number is set to be in an empty state each time reading of a bank unit from the memory is completed, and outputted from the first control circuit. And bank management circuitry to convert the physical bank number for Li bank number which is assigned to the logical bank number, and has a memory control circuit for sequentially accessing the image data of a physical bank starting at the address corresponding to the converted physical number.

According to the first aspect of the present invention, by dividing the image data into logical banks and assigning them to physical banks secured in the memory, and recording and reading the image data in units of banks, one conventional frame with a capacity smaller than one frame is obtained. Can play the role of minutes. In addition, since the bank management circuit of the above structure is used, the effect of reducing the capacity of the memory can be achieved with a simple structure, contributing to the reduction of the manufacturing cost of the image data processing apparatus.

Moreover, since the first control circuit only requires outputting the logical bank number, the first control circuit has an effect that the processing and the configuration are simplified.

As a second aspect of the present invention, in the image data processing apparatus according to the first aspect of the present invention, the bank management circuit is configured to correspond to a correspondence between a physical bank number and a logical bank number supplied when an allocation control signal is active. The logical / physical bank number converting unit for performing the allocation by converting the logical bank number into the physical bank number according to the allocation, and any of the logical bank numbers for each of the physical bank numbers. In response to a physical bank allocation request from the first control circuit and an allocation state storage unit indicating whether there is an allocated state or an unassigned empty state, the empty state is detected by referring to the contents of the allocation state storage unit, The physical bank number and the act of changing the detected empty state to the allocated state and converting to the allocated state A ball supplying the control signal allocated to the logical / physical bank number conversion unit converts the state unit has physical bank detection / assignment.

According to a second aspect of the present invention, a logical bank is provided to a physical bank by simply providing an allocation state storage section and a shared physical bank detection / allocation section, which are simple configurations, and outputting a physical bank allocation request and a logical number from a main control circuit. Since it is allocated, the allocation of the logical bank to the physical bank can be easily performed.

As a third aspect of the present invention, there is provided an image data processing apparatus according to a second aspect, wherein the bank management circuit detects that the memory control circuit has completed access to a read address for one bank, and stores the allocation state. The apparatus further includes a physical bank opening for converting the allocation state into the empty state in addition to the physical bank number of the one bank.

According to the third aspect of the present invention, since the opening of the physical bank is performed separately from the first control circuit, the processing in the first control circuit is simplified.

In an image data processing apparatus according to a second aspect as a fourth aspect of the present invention, the empty state physical bank detection / allocating section references the empty state with reference to the contents of the allocation state storage section in response to a physical bank search request. An empty state physical bank detection unit for detecting, converting the detected empty state into the allocation state, supplying the physical bank number converted into the allocation state to the logical / physical bank number conversion unit, and outputting an allocation completion notice; And a physical bank allocator for outputting the physical bank search request and supplying the logical / physical bank number conversion unit with the active allocation control signal when the physical bank allocation request and the allocation completion notification are received.

According to the fourth aspect of the present invention, since a public physical bank number can be obtained in response to a physical bank search request before the physical bank allocation request, a logical bank can be assigned to a physical bank at a high speed in response to the physical bank allocation request. have.

In the image data processing apparatus according to the first aspect of the fifth aspect of the present invention, the memory has a buffer storage region for encoded image data, and the memory control circuit temporarily stores encoded image data in the buffer storage region for delay. And the decoder further reads the encoded image data from the buffer storage region, and the image data processing apparatus further includes a decoder for decoding the encoded image data read out from the buffer storage region and supplying the encoded image data to the memory. The control circuit responds to a slow regeneration request for reproducing at a rate of 1 / N, and with respect to the memory control circuit, each of the top field and the bottom field is repeatedly read N times from the buffer storage area of the memory, Therefore, the decoded image data is stored in the storage area of the p bank. It is performed in the write and read for display.

According to the fifth aspect of the present invention, slow reproduction can be performed at a rate of 1 / N even when the memory structure for the decoded image data is less than one frame in the bank structure.

As a sixth aspect of the present invention, there is provided an image data processing apparatus according to a fifth aspect, wherein the first control circuit performs the same operation as the control operation for the slow reproduction request of speed 1 / ∞ in response to the pause reproduction request. Do it.

As a seventh aspect of the present invention, there is provided an image data processing apparatus according to the first aspect, wherein the image data is MPEG data, and the storage capacity of each physical bank is an integer multiple of one macro block line.

According to the seventh aspect of the present invention, the complexity of image data processing by bank division can be avoided.

As an eighth aspect of the present invention, there is provided an image data processing apparatus according to the first aspect, wherein the image data is MPEG data, and the storage capacity of each physical bank is an odd multiple of one macroblock line. .

According to the eighth aspect of the present invention, in the case of processing image data on a field basis, the complexity of image data processing by bank division can be avoided.

The image data processing method according to the ninth aspect of the present invention is m = (image data amount for one frame) / (image data amount for one bank), and m is a logical bank when image data is m When a logical bank number is assigned to each logical bank, and p is an integer satisfying 2 < pm, the storage area of the p physical bank is secured in the memory for storing image data, and the physical bank is physically assigned to each physical bank. Assigning a bank number, assigning a logical bank number to an empty physical bank number, leaving the allocated physical bank number empty each time the reading of a bank unit is completed, and assigning a logical bank number to each of the allocated logical bank numbers. Converting the logical bank number into a physical bank number to which the logical bank number is assigned, and converting the logical bank number into one physical bank starting from an address corresponding to the converted physical number. And a step of sequential access data.

As a tenth aspect of the present invention, the image data processing method according to the ninth aspect includes the steps of temporarily storing encoded image data in a buffer storage area of the memory to delay encoded image data, and slowing down at a speed of 1 / N. In response to a reproduction request, repeatedly reading the top field and the bottom field N times from the buffer storage area, decoding the coded image data read from the buffer storage area, and decoding the coded image data. And supplying the physical banks.

An image data processing apparatus according to an eleventh aspect of the present invention includes a memory, and temporarily storing the decoded image data in the memory, generating a predictive image with reference to the decoded image data in the memory, and before encoding from the memory. A memory control / prediction image generating circuit that reads the decoded image data in the order of the original image of the image, a reduced conversion circuit that converts the decoded image data so that the image is reduced in units of blocks, and recording decoded image data in the memory. And a switching circuit for selecting whether or not to pass the reduced conversion circuit before, and for selecting whether to pass the reduced conversion circuit after reading decoded image data from the memory, wherein the memory control / The predictive image generation circuit is configured to decode the decoded image data. Rie that the recording and that the read from the memory, depending on whether or not the display mode is reduced mode or whether the reference picture in the decoded picture data is non, and a control circuit for controlling the switching circuit.

According to the eleventh aspect of the present invention, when reading display image data from the memory in the reduced display mode, since the data reading amount is smaller than before, the image data processing speed can be made slower than before. Contribute to manufacturing cost reduction

In an image data processing apparatus according to an eleventh aspect as a twelfth aspect of the present invention, in the control / prediction generation circuit, while the decoded image data is recorded in the memory, the display mode is a reduced mode and the image data is dereferenced. In the first case of the image, the switching circuit is controlled so that the image data passes through the reduction conversion circuit and is written to the memory. Otherwise, the image data does not pass through the reduction conversion circuit. The switching circuit is controlled to be written to a memory, and while reading decoded image data from the memory, the image data read from the memory is reduced in the first case or in the second case when the display mode is not in the reduced mode. Control the switching circuit so as not to pass through the conversion circuit, and In the case nor the second case, not even if one is to control the switching circuit the image data read from the memory to pass through the reduced conversion circuit.

An image data processing apparatus according to a thirteenth aspect of the present invention includes a memory, a reduction conversion circuit for converting image data so that images are reduced in units of blocks, and the reduction conversion circuit before recording image data in the memory. A switching circuit for selecting whether or not to pass through the reduction conversion circuit after reading image data from the memory, whether the image data is written to or read from the memory; And a control circuit for controlling the switching circuit in accordance with whether the display mode is a reduced mode and whether the image data is a non-reference image.

A 14th aspect of the present invention is an image data processing method for decoding coded image data having a decoded image temporary storage memory and a reduced conversion circuit for reducing a decoded image size, wherein decoded image data is recorded in the memory. In the first case where the display mode is the reduced mode and the decoded image data is a non-reference image, the decoded image data is passed through a reduction conversion circuit to be written to the memory. Otherwise, the decoded image data is not. Is written into the memory without passing through the reduced conversion circuit, and while the decoded image data is read from the memory for display, the decoded image data in the first case or in the second case when the display mode is not the reduced mode. Read from the memory to reduce A, and so as not to pass through neither the first case nor the second case case, it comprises a step of passing the image data read from the memory to the reduction converter.

In a fifteenth aspect of the present invention, a moving picture decoder decodes a frame memory and coded picture data to obtain decoded picture data, and writes the coded picture data to the frame memory, and generates reference picture data from the frame memory for decoding predictive image generation. A decoder which reads and decodes the decoded image data from the frame memory as display image data, and when the winding mode is a double speed mode, the decoder decodes the encoded image data at an average speed twice the normal speed. The decoder to write to the frame memory, to read a reference picture from the frame memory, and to read the decoded picture data as the display picture data by the decoder every other picture from the frame memory at a normal speed. Control circuit to supply control data to Has a furnace.

According to the moving picture decoder according to the fifteenth aspect of the present invention, it is possible to reproduce an image in the double-speed winding mode even when no B picture exists.

As a sixteenth aspect of the present invention, in the moving picture decoder according to the fifteenth aspect, the control circuit is supplied with a decoded vertical synchronizing signal having a pulse period equal to a field period, an image coding type and the winding mode, and the control circuit is configured to wind the winding. When the mode is a constant speed mode, a pulse of a decoding start signal is generated according to a pulse corresponding to the bottom field of the decoded vertical sync signal. When the winding mode is a double speed mode, the pulse is generated according to each pulse of the decoded vertical sync signal. Generate a pulse of a decoding start signal, generate a pulse of a reference picture reading start signal corresponding to the pulse of the decoding start signal except when the picture coding type indicates an I picture, and generate the decoding vertical synchronization signal Generating a display image reading start signal corresponding to the 1/2 divided and delayed signal; The decoding is started in synchronization with the decoding start signal, the reading of the reference image data is started in synchronization with the reference image reading start signal, and the reading of the display image data is started in synchronization with the display image reading start signal. .

According to the moving picture decoder according to the sixteenth aspect of the present invention, it is not necessary to double the operation speed of the control circuit.

As a seventeenth aspect of the present invention, in the moving picture decoder according to the sixteenth aspect, the control circuit comprises a first to third register and a decoded image recording start address to the first register at a pulse timing of the decoding start signal. Hold the output of the first register in the second register at the pulse timing of the reference picture read start signal, and output the output of the second register to the third register at the pulse timing of the display image read start signal. And a register control circuit for holding, wherein the decoder receives the output of the first register as the decoded image write start address, receives the output of the second register as a reference image read start address, The output is received as the display image read start address.

According to the moving picture decoder according to the seventeenth aspect, address management during access to the frame memory is simplified.

In an eighteenth aspect of the invention, in the moving picture decoder according to the seventeenth aspect, the register control circuit holds the start addresses of three regions in the first register in sequential cycles.

According to the eighteenth aspect of the present invention, the storage area allocation of the frame memory is simplified.

As a nineteenth aspect of the present invention, in the video decoder according to the seventeenth aspect, the data output end of the first register is connected to the data input end of the second register, and the data output end of the second register is connected to the third register. It is connected to the data input terminal.

According to the moving picture decoder according to the nineteenth aspect of the present invention, register control is simplified.

As a twentieth aspect of the present invention, in the moving picture decoder according to the fifteenth aspect, when the winding mode is a double speed mode, the control circuit doubles the operation of the decoder, so that the display image data from the frame memory is doubled. The reading is skipped every picture.

As a twenty-first aspect of the present invention, in the video decoder according to the twentieth aspect, the control circuit doubles the operation of the decoder by doubling its own control operation.

A system decoder according to a twenty-second aspect of the present invention includes a circuit for generating a clock pulse, a counter for counting the clock pulse and outputting the count value as a system time clock, and a synchronous pulse in a frame period in accordance with the clock pulse. A synchronizing pulse generating circuit to generate, storage means for temporarily storing the supplied presentation time stamp, a comparing circuit for detecting that the system time clock matches the presentation time stamp read from the storage means, and responding to the sync pulse. And a control circuit for reading out the presentation time stamp corresponding to the picture reproduction order from the storage means and loading the presentation time stamp into the counter, wherein the pulse generated when detecting the sync pulse or the match is Display image data read start pulse Is used.

According to the system decoder according to the twenty-second aspect of the present invention, even if the storage capacity of the frame memory is reduced than before, the start time of reading the display image data from the frame memory is shifted from the conventional presentation time stamp. Since an appropriate system time clock is generated, as a result, it becomes possible to reduce the storage capacity of the frame memory, which greatly contributes to reducing the manufacturing cost of the moving picture decoder.

In a twenty-third aspect of the invention, in the system decoder according to the twenty-second aspect, the control circuit has a time Δ and a time {(frame period T) -Δ} until the synchronization pulse is generated after the match is detected. When greater than the set value, the presentation time stamp is loaded into the counter.

According to the system decoder according to the twenty third aspect of the present invention, the shift time is automatically adjusted even if the shift time Δ or (T-Δ) becomes large enough to be ignored for some reason.

As a twenty-fourth aspect of the present invention, in a system decoder according to the twenty-second aspect, the system decoder further includes a selector for selecting one of a system clock reference and a presentation time stamp read from the storage means and supplying the counter to the counter; The circuit selects the system clock reference for the selector, then selects the presentation time stamp, and loads the output of the selector into the counter in response to the sync pulse.

In a twenty-fifth aspect of the invention, in a system decoder according to twenty-fourth aspect, the control circuit selects the system clock reference initially supplied to the selector and then selects the presentation time stamp.

According to the system decoder according to the twenty fifth aspect of the present invention, the misalignment time is adjusted immediately after the start of decoding.

In a twenty sixth aspect of the present invention, in the system decoder according to the twenty-second aspect, the circuit for generating the clock pulse includes the frequency of the clock pulse so that the value of the counter that counts the clock pulse coincides with the value of the system clock reference. This is a PLL circuit for feedback control.

In a system decoder according to a twenty-seventh aspect of the present invention, the circuit for generating the clock pulse is a free running clock generation circuit.

According to the system decoder according to the twenty-seventh aspect of the present invention, the configuration of the system decoder is simpler than that of the system decoder according to the twenty-sixth aspect, and the period of the clock pulse can be made more accurate than in the case of the feedback control according to the twenty-sixth aspect. .

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described with reference to the drawings, wherein like reference numerals designate like parts or corresponding parts.

[First Embodiment]

1 shows a schematic configuration of a moving picture decoder according to the first embodiment of the present invention corresponding to FIG. 15.

The apparatus 21 switches instead of the switching circuit 19 of FIG. 19 so as to select whether or not to transfer the data to the letter box conversion circuit 20 before or after writing the image data to the frame memory 14A. To 24).

In recording the moving picture recording in the frame memory 14A, when the display mode is the reduced mode and the decoded image data DAT2 is a B picture which is a non-reference picture, the memory control / prediction image generation circuit 15A switches the switching circuit 21. The switching circuit 22 is switched to the output side of the addition circuit 13, the switching circuit 22 is switched to the switching circuit 23 side, and the switching circuit 23 is switched to the switching circuit 22 side. As a result, the DAT2 is reduced to the letter box conversion circuit 20 and temporarily stored in the frame memory 14A as the DAT2A. In the letter box conversion circuit 20, 16x16 pixels are reduced to 16x12 pixels.

In recording the moving image to the frame memory 14A, the switching circuit 23 is switched to the output side of the addition circuit 13 in other cases. As a result, the DAT2 is temporarily stored in the frame memory 14A as the DAT2A.

In the image reading from the frame memory 14A, when the display mode is the reduced mode and the display image data DAT5 is the B image, or when the display mode is not the reduced mode, the switching circuit 24 performs the frame memory 14A. ) Is switched to the output side. As a result, the display image data DAT5 is taken out from the switching circuit 24 as the display image data DAT6. Therefore, when reading the display image data DAT5 of the B picture from the frame memory 14A, the data reading amount is reduced to three quarters of the conventional, and there is no need to perform the same high-speed processing as before.

In the image reading from the frame memory 14A, in the case other than the above, i.e., when the display mode is the reduced mode and the display image data DAT5 is not the B image, the memory control / prediction image generating device 15A is switched circuit 21. ) Is switched to the output side of the frame memory 14A, the switching circuit 22 is switched to the switching circuit 24 side, and the switching circuit 24 is switched to the switching circuit 22 side. As a result, the display image data DAT5 is reduced to the letter box conversion circuit 20 and taken out from the switching circuit 24 as the display image data DAT6. In this case, although it is the same as before, by storing the read display image data in a buffer memory not shown in the drawing, the processing speed of the entire reduced display image can be reduced than before.

The moving picture decoder of FIG. 1 is different from the moving picture decoder of FIG.

Second Embodiment

Next, the moving picture decoder according to the second embodiment that enables the storage capacity of the frame memory 14A to be reduced regardless of whether the display mode is the reduced mode or not. In the following description, the letter box conversion may be either of FIG. 1 or FIG. 15.

First, an outline of a bank that enables a storage capacity reduction and a method of using the same will be described.

In the display mode of the maximum number of pixels, the storage capacity of the frame memory 14A is represented by 2.X frames. A 0.X frame is for a B picture, which is at least two banks (one bank for writing and one bank for reading), where one bank is an integer multiple of one macroblock line, for example, 16 lines of an image on a display screen. This is because in the variable length decoder 10, the inverse quantization circuit 11 and the inverse DCT circuit 12 shown in Fig. 1, processing is performed in units of one macroblock of 16x16 pixels.

As shown in Fig. 5A, the division of a B image into banks is called a logical bank, and the division of a storage area for 0.X frames in the frame memory 14A into banks is called a physical bank. FIG. 5A shows a case where the capacity of the B picture is 4 banks and the 0.X frame is 2 banks.

When the DAT2A is a B picture, the logical banks 1 to 4 are stored in the physical banks A and B of the frame memory 14A, as shown in Figs. 5A to 5G. While Fig. 5A shows the allocation of the logical banks to the physical banks, Figs. 5B to 5G show the allocation of the physical banks to the logical banks and the display of the logical banks in chronological order.

Initially, the physical bank A and the physical bank B are in an empty state, and the contents of the logical bank 1 are recorded in the physical bank A (Fig. 5 (b)). Subsequently, the contents of logical bank 2 are recorded in physical bank B, and the contents of physical bank A are simultaneously read as DAT5 (Fig. 5 (c)). This writing and reading is mutually asynchronous. When the reading from the physical bank A is completed, the reading from the physical bank B is next started (Fig. 5 (d)). Since physical bank A is empty, the contents of logical bank 3 are then written to physical bank A (FIG. 5E). When the read from the physical bank B is completed, the read from the physical bank A is continued (Fig. 5 (F)). Next, the contents of logical bank 4 are written to physical bank B, and when reading from physical bank A is completed, reading from physical bank B is started (Fig. 5 (g)).

Physical banks A and B are rearranged in the frame memory 14A, as shown in FIG. FIG. 4 corresponds to FIG. 16 and shows the image type of the image data DAT2A sequentially supplied to the frame memory 14A and the image storage states ST1 to ST9 in the frame memory 14. In Fig. 4, I, P, and B indicate picture types, and the numbers attached to these picture types indicate the temporal order of coded picture data DAT0 (DAT2A). 4 denotes an image read out from the frame memory 14A as a display image.

Next, the writing of the DAT2A to the frame memory 14A and the reading of the display image data DAT5 from the frame memory 14A will be described schematically.

(ST1) The image I1 is recorded in the frame memory 14A. The next write address ADR is ADR = (last storage address of image I1) +1.

(ST2) The physical bank is secured from the address ADR. The predicted picture {I1} of the picture B2 is generated using the picture I1 as a reference picture, the picture B2 as an error picture is added to the picture data DAT1, and the picture B2 is decoded and recorded in the physical bank of the frame memory 14A. Next, the image B2 is read as the display image data DAT5. Hereinafter, these are simply shown by {I1} + B2 → B2, B2 display. When the display of the image B2 is completed, the area in which the image B2 is stored is released, so that ADR = (last storage address of the image I1) +1. The physical banks are reserved n banks, for example, two banks, from the address ADR before the start of the B picture storage.

(ST3) {I1} + B3 + B3, B3 display

(ST4) {I1} + P4 + P4, I1 display

The image P4 is stored from the same position as the start position of the released image B3 region. Since the image I1 is used as the reference image even after the display of the image I1 is completed, ADR = (the last storage address of the image P4) + 1.

(ST5) {I1 + P4} + B5 → B5, B5 display

When the display of the image B5 is completed, the area where the image B5 is stored is released, so that ADR = (the last address stored in the image P4) + 1.

(ST6) {I1 + P4} + B6 → B6, B6 display

(ST7) {P4} + P7 → P7, Image P4 display

When the picture P7 is stored from the address ADR to the final address of the frame memory 14A, the picture P7 is returned to the head address of the frame memory 14A, and the remaining picture P7 is stored. In other words, the address of the frame memory 14A is connected in a loop form.

ADR = (the last address stored in image P7) + 1.

(ST8) {P4 + P7} + B8 → B8, B8 display

(ST9) {P4 + P7} + B9 → B9, B9 display

In this way, the display image can be obtained in the order of the images B2, B3, I1, B5, B6, P4, B8, B9, and P7 in the same manner as the original moving image before encoding.

Fig. 2 shows a schematic structure of a moving picture decoder according to the second embodiment of the present invention using the above-described bank and its use method.

In the above apparatus, the read / write state of the buffer memory 26 is controlled by the buffer memory control circuit 25 and the buffer memory 26 is addressed so that the video bit stream VBS separated from the multiple bit stream is stored in the buffer memory ( 26 is temporarily stored at high speed, and the stored data is read at low speed from the buffer memory 26 and supplied to the variable length decoder in the decoder 27 as DAT0.

The decoder 27 is a predictive image generation circuit portion of the variable length decoder 10, the inverse quantization circuit 11, the inverse DCT circuit 12, the adder circuit 1, and the memory control / prediction image generation circuit 15 of FIG. Is made of. The decoded picture data DAT4 for reference is supplied to the decoder 27 from the frame memory 14A, and the decoder 27 performs prediction decoding to supply the DAT2 to the frame memory 14A.

The decoding / display control circuit 28 includes control information CI1 such as a system clock reference SCR, a decoding time stamp DTS, and a presentation time stamp PTS separated by a system decoder not shown in the figure when separating the video bit stream VBS; Control information CI2 such as a picture decoding type, a temporal reference, a motion vector, or a picture size separated from the variable length decoder in the decoder 27, a pause reproduction request signal PRQ, a slow reproduction request signal SRQ, and reproduction generated according to an operator's operation. Control information such as speed 1 / N is supplied. The decoding / display control circuit 28 generates various control data for decoding and display based on these control information, so that the buffer memory control circuit 25, the decoder 27, the frame memory control circuit 29, and the bank management are generated. Supply to the circuit 30 and the display circuit 115. The decoding / display control circuit 28 includes a start address register circuit 281, which is a buffer memory write start address BW, a buffer memory read start address BR, a frame memory write start address FW, and a frame memory reference image read start. And registers holding addresses FR1, FR2 and frame memory reference picture read start address FR3, respectively. The decoding / display control circuit 28 sets the contents of these registers in accordance with the control information.

At the time of reset, the buffer memory write start address BW is loaded into the address counter 251 of the buffer memory control circuit 25, and the buffer memory 26 is put into the write state by the buffer memory control circuit 25, thereby providing a video bit stream. VBS is written to the buffer memory 26. At this time, when the address counter 251 is incremented in response to the clock and data is written to the last address in the buffer memory 26, the start address of the buffer memory 26 is set by the buffer memory control circuit 25 to the address counter ( 251, recording of the video bit stream VBS is continued. The decoding start command and the buffer memory read head address BR are supplied from the decoding / display control circuit 28 to the buffer memory control circuit 25. When the BR is loaded into the address counter 251, the buffer memory 26 is put into the read state by the buffer memory control circuit 25, the address counter 251 is incremented in response to the clock, and the DAT0 is read. At this time, control information separated from the variable length decoder in the decoder 27 is supplied to the decoding / display control circuit 28.

The writing to the buffer memory 26 and the reading from the buffer memory 26 are time-divisioned in parallel by the buffer memory control circuit 25, so that when the control is changed from write to read or vice versa, The contents are retracted to one register (not shown), and the contents of the other register to be retracted are returned to the address counter 251 (not shown).

The read addresses are normally continuous in the recording order, but it is necessary to repeat the same contents in the slow reproduction described later. In this case, the buffer memory read from the decoding / display control circuit 28 to the buffer memory control circuit 25 is performed. The head address BR is supplied and loaded into the address counter 251.

When starting the access for one image to the frame memory 14A, the following processing is performed regardless of the image type.

That is, in the case where writing of DAT2 is started in the frame memory 14A, the write start command and the frame memory write start address FW are supplied from the decoding / display control circuit 28 to the frame memory control circuit 29, and this address FW is It is loaded into the address counter 291. When the display decoded image data DAT5 is started to be read from the frame memory 14A, a display image read start command and an ADR are supplied from the decoding / display control circuit 28 to the frame memory control circuit 29, and this ADR is supplied. It is loaded into the address counter 291. When the DAT4 is started to be read from the frame memory 14A, the reference image read start command and FR1 are supplied from the decoding / display control circuit 28 to the frame memory control circuit 29, and when two reference images are used. FR2 is further supplied, and the start addresses FR1 and FR2 are loaded to the address counter 291 by shifting the time from each other by the frame memory control circuit 29. As in the case of the buffer memory control circuit 25, the address counter 291 is incremented by a clock, and the read and write to the frame memory 14A are time-divisioned in parallel by the frame memory control circuit 29.

When accessing the logical bank which is a B picture to the frame memory 14A, the following processing is further performed.

That is, when the DAT2 of the logical bank, which is a B picture, is written to the frame memory 14A, the physical bank allocation request RQ2 and the write logic bank number L1N are supplied from the decoding / display control circuit 28 to the bank management circuit 30. do. When the physical bank allocation request RQ2 is received, the write logic bank number L1N is converted into the physical bank number P1N by the bank management circuit 30 and supplied to the frame memory control circuit 29. The frame memory control circuit 29 loads FW + P1N / BNK into the address counter 291 to control writing to the frame memory 14A. Here, BNK is a storage capacity value of one physical bank predetermined, and is supplied from the bank management circuit 30. P1N = 0 at first for each image.

When the DAT5 of the logical bank, which is a B image, starts reading from the frame memory 14A, the read logic bank number L2N is supplied from the decoding / display control circuit 28 to the bank management circuit 30, so that the read logic bank number L2N The bank management circuit 30 converts the data into the physical bank number P2N and supplies it to the frame memory control circuit 29. The frame memory control circuit 29 loads ADR + P2N BNK into the address counter 291 to perform read control from the frame memory 14A. The first time for each picture is P2N = 0.

The DAT5 is supplied to the display circuit 115, and format conversion, analog conversion, and the like are performed to generate the video signal VS for the display device.

3 shows an example of the configuration of the bank management circuit 30. This circuit 30 is provided with the components 32-37.

The physical bank number calculating section 32 calculates the bank number n of the above-mentioned 0.X frame as follows.

n = [(ADRe-ADRs + 1-2 FLM) / BNK]

Where ADRs is the start address of the frame memory 14A, ADRe is the end address of the frame memory 14A, FLM is the storage capacity of one frame determined by the display mode, and [] is an integer symbol indicating truncation after the decimal point. . The physical bank number n is supplied to the empty physical bank detector 33.

The physical bank allocation register 34 has the same number of bits as the maximum value N of n, and FIG. 3 shows the case where N = 4. Each bit of the physical bank assignment register 34 corresponds to a physical bank and is used as the physical bank assignment flags FA to FD. When this flag is '1', it indicates that logical bank allocation is completed, and when it is '0', it is not allocated.

In response to the physical bank search request RQ1 from the physical bank allocating unit 35, the stateful physical bank detecting unit 33 selects a first bit of '0' with respect to n bits from one end of the physical bank allocation register 34. Detects, inverts this bit to '1', supplies a detected physical bank number PDN = i to the logical / physical bank number converting unit 36, and sends an allocation completion notification (ACK1) to the physical bank allocating unit 35. Supply. If all of the n bits are '1', the processing is performed after any one of them becomes '0'.

The decoding / display control circuit 28 of FIG. 2 supplies the physical bank search request RQ2 to the physical bank allocator 35, and simultaneously decodes the decoding / decoding logical bank number L1N of the image data DAT1 to be decoded. It supplies to the number conversion part 36. FIG. The physical bank assignment unit 35 supplies the physical bank search request RQ1 to the empty state physical bank detection unit 33 before issuing the physical bank search request RQ2, and when both the allocation completion notification ACK1 and the physical bank search request RQ2 are received, The allocation control signal CNT1 is supplied to the logical / physical bank number conversion section 36, and at the same time, the physical bank assignment notification ACK2 is supplied to the decoding / display control circuit 28 of FIG. The physical bank allocator 35 supplies the physical bank search request RQ1 to the empty physical physical bank detector 33 after the output of the allocation control signal CNT1 and before receiving the next physical bank allocation request RQ2 to process the next logical bank. do.

The logical / physical bank number converting section 36 includes mapping registers MR1 to MR4, one of the mapping registers MR1 to MR4 is addressed to the decoded write logic bank number L1N, and assigned to the designated register at the timing of the control signal CNT1. The detection physical bank number PDN is maintained.

The logical / physical bank number conversion unit 36 cyclically reads the contents in the order of the mapping registers MR1 to MR4 in response to a request from the frame memory control circuit 29 of FIG. 2, and stores the frame as the physical bank number P1N. Supply to the memory control circuit 29. The frame memory control circuit 29 calculates FW + P1N BNK described above and loads it into the address counter 291. The content ADR of the address counter 291 is incremented in accordance with the clock, and DAT2A is sequentially written to this address ADR.

The decoding / display control circuit 28 of FIG. 2 supplies the logical bank number L2N to be displayed next to the logical / physical bank number converting section 36 and the physical bank opening section 37. FIG. The logical / physical bank number converter 36 addresses one of the mapping registers MR1 to MR4 with the read logic bank number L2N, and supplies the contents to the frame memory control circuit 29 of FIG. 2 as the physical bank number P2N. do. The frame memory control circuit 29 calculates ADR + P2N BNK described above, loads it into the address counter 291, and performs read control on the frame memory 14A. As a result, the display image data DAT5 is sequentially read from the frame memory 14A.

The physical bank opening section 37 detects that the coincidence detection circuit matches the contents ADR of the address counter 291 with ADR + (P2N + 1) BNK-1, thereby determining that the reading of DAT4 for one bank is completed. The logical bank number L3N holding the contents of the read logic bank number L2N and the bank open control signal CNT2 immediately before the change of the read logic bank number L2N are supplied to the logical / physical bank number conversion unit 36. In response to this, the logical / physical bank number converting unit 36 addresses one of the mapping registers MR1 to MR4 with the displayed logical bank number L3N, and the physical bank allocation register 34 corresponding to the content X is assigned. The Xth bit is reset to initialize the contents X of the address register.

6 is a time chart illustrating the circuit operation of FIG. 3.

(t01) The physical bank search request RQ1 is supplied to the empty physical bank detection unit 33.

(t02) The detected physical bank number PDN representing the physical bank A (= 0, the detected physical bank number PDN representing the physical bank B is 1) is output from the state physical bank detector 33, and the physical bank allocation register 34 is output. Becomes '1000'.

(t03) L1N and RQ2 are output from the decoding / display control circuit 28.

(t04) The allocation control signal CNT1 and the physical bank allocation notification ACK2 are supplied from the physical bank allocating unit 35 to the logical / physical bank number converting unit 36 and the decoding / display control circuit 28, respectively.

(t05) The detection physical bank number PDN corresponding to the physical bank A is held in MR1. The hatched portions in Fig. 6 indicate that the contents are initialized.

Next time t11-t15 is the same as time t01-t05.

(t17) The read logic bank number L2N is supplied to the logical / physical bank number converting section 36 and the physical bank opening section 37, P2N = 0 is output from the logical / physical bank number converting section 36, and physical Reading of the contents of the logical bank 1 from the bank A is started.

(t21) The physical bank search request RQ1 is supplied to the empty physical bank detection unit 33.

(t23) L1N and RQ2 are output from the decoding / display control circuit 28.

(t27) The read logic bank number L2N is supplied to the logical / physical bank number converting section 36 and the physical bank opening section 37.

(t26) The most significant bit of the physical bank allocation register 34 is cleared to zero by the logical / physical bank number conversion unit 36, and the contents of MR1 are cleared. P2N = 1 is output from the logical / physical bank number converting section 36, and the contents reading of the logical bank 2 is started in the physical bank B.

(t22) The detection physical bank number PDN indicating the physical bank A is output from the state physical bank detection unit 33, so that the contents of the physical bank assignment register 34 become '1100'.

(t24) The allocation control signal CNT1 and the physical bank allocation notification ACK2 are supplied from the physical bank allocating unit 35 to the logical / physical bank number converting unit 36 and the decoding / display control circuit 28, respectively.

(t25) The detection physical bank number PDN = 0 corresponding to the physical bank A is held in the mapping register MR3.

The following time t31-t37 is the same as the above, and the description is abbreviate | omitted.

According to the second embodiment, the storage capacity of the frame memory 14A can be reduced by bank division by the above-described processing of the B image.

Next, the slow regeneration process will be described.

In response to the slow regeneration request signal SRQ to the decoding / display control circuit 28 of FIG. 2, decoding and display control are performed so that the reproducing speed is the normal 1 / N based on the set reproducing speed 1 / N. Lose.

In the case of an I image or a P image, it is sufficient to repeatedly read N fields of the moving image read out from the frame memory 14A N times, and is performed in the same manner as before. In this case, the average value of the data transfer rate from the buffer memory 26 to the decoder 27 is 1 / N in the case of normal reproduction.

In the case of a B picture, when the decoded picture data of one logical bank is read as described above, the picture data of the next logical bank is overwritten and the image data of the previous logical bank is lost. The field is repeatedly read N times from the buffer memory 26. In this case, the combination of N repetitions and reproduction rate 1 / N causes the average value of the data transfer rate from the buffer memory 26 to the decoder 27 as in the case of normal reproduction.

Fig. 7A shows the decoded image sequence of the B image in the 1/2 slow reproduction mode, and the field images 50 to 53 are decoded in this order. Images 50 to 53 are the same frame, and images 50 and 51 are the same top field TF, and images 52 and 53 are the same bottom field BF.

Referring back to FIG. 2, whenever the control information CI2 of the picture header, which is a B picture, is supplied from the decoder 27 to the decoding / display control circuit 28, the buffer memory control circuit (from the decoding / display control circuit 28) The decode start command and the buffer memory read start address BR are supplied to the buffer memory control circuit 25 in order to load the buffer memory read start address BR into the address counter 251. In supplying the buffer memory read start address BR to the buffer memory control circuit 25, the same value is repeated twice for each of the top field TF and the bottom field BF of the same frame, as shown in Fig. 7A. BR1, BR1, BR2, and BR2 are in order. As a result, DAT0 of the same top field TF of the same frame is supplied to the decoder 27 twice from the buffer memory 26 to the decoder 27, and then DAT0 of the same bottom field BF of the same frame is decoded twice. Supplied to (27). In the case of the frame structure, one field is read by skipping the read line from the buffer memory 26 for each line, so as to be the same as in the case of the field structure.

For the B picture, the decoding command DRQ including the picture coding type supplied from the decoding / display control circuit 28 to the decoder 27, and the control supplied to the frame memory control circuit 29 and the bank management circuit 30. The data is repeated twice in accordance with the above two repetitions of the control data from the decoding / display control circuit 28 to the buffer memory control circuit 25, so that the display image order is the same as the decoded image order.

In Fig. 7C, the scanning line shown by the solid line represents the top field image TFP on the display screen, and the scanning line shown by the dotted line represents the bottom field image BFP on the display screen.

When DAT5 is the top field image 51 of Fig. 7A, control data for displaying the top field TF as the bottom field image BFP from the decoding / display control circuit 28 to the display circuit 115 is supplied. In the case of the bottom image 52, control data for displaying the bottom field BF as the top field image TFP is supplied. As a result, a pseudo frame image is displayed using the data of the field image regardless of the image type.

Fig. 7B shows the decoded image order of the B image in the 1/3 slow reproducing mode, which is decoded in the field images 60 to 65 order. Images 60 to 65 are the same frame, images 60 to 62 are the same top field TF, and images 63 to 65 are the same bottom field BF. The above two repetitions of the control data output from the decoding / display control circuit 28 are three times in this case. In the case of the frame structure, the field images 62 and 63 may be decoded as one frame image.

The same applies to the slow playback mode at a speed of 1/4 or less.

The pause reproduction operation performed in response to the pause reproduction request signal PRQ is the same as in the case of 1 / ∞ slow reproduction.

According to the second embodiment, even when the storage capacity of the frame memory 14A is less than three frames in the bank configuration, slow playback or pause playback can be performed by the above operation.

[Third Embodiment]

Fig. 8A shows a schematic structure of a moving picture decoder of the third embodiment of the present invention. 9 and 10 are time charts showing the operation of this video decoder. Fig. 9 shows the case of the constant speed mode, and Fig. 10 shows the case of the double speed mode.

The buffer memory control circuit 25 is accessed in the buffer memory 26 as described above. The buffer memory control circuit 25 starts reading the encoded image data DAT0 for one frame from the buffer memory 26 in synchronization with the decoding start signal DS from the system control circuit 70.

The system control circuit 70 is supplied with an image coding type PCT, a decoded vertical synchronization signal DSYNC, and a winding mode MOD. The decoded vertical synchronization signal DSYNC is generated in the moving picture decoder based on a clock. The winding mode MOD is a signal generated by the operator's mode switching operation. This picture coding type PCT is also supplied to the decoder 27A. The decoder 27A includes the decoder 27 of FIG. 2 and the frame memory control circuit 29.

The system control circuit 70 sends the decoding start signal DS, the display picture read start signal PS, the decoded picture write start address FW, the reference picture read start address FR, the display picture read start address ADR, and the decode vertical sync signal DSYNC to the decoder 27A. And the display vertical synchronizing signal ESYNC.

The decoder 27A starts decoding of DAT0 for one frame in synchronization with the decoding start signal DS. When the picture coding type PCT indicates an I picture, the decoded picture recording start address is stored in the frame memory 14. Record sequentially from FW. When this picture coding type PCT indicates a P picture or a B picture, starting from the address FR, the reference picture data DAT4 is read from the frame memory 14 to generate predictive picture data. The prediction image data and the error data obtained by decoding the DAT0 are added to the frame memory 14 in order from the FW to the decoded image data DAT2. The decoder 27A also reads display image data DAT5 for one frame sequentially from the address ADR of the frame memory 14 in synchronization with the display vertical synchronization signal ESYNC.

The storage areas of the frame memory 14 are divided into three sections, and these are called sections 1 to 3, respectively.

The system control circuit 70 includes a bank address management unit 70a as shown in Fig. 8B.

In the bank address management unit 70a, the start addresses ADR1 to ADR3 of the sections 1 to 3 of the frame memory 14 are stored in the registers 81 to 83, respectively, and one of the start addresses ADR1 to ADR3 is selected by the selector 84. The signal is selected in accordance with the selection control signal from the latch control circuit 85 and supplied to the data input terminal of the register 91. The supplied section start address is the decoded image write start address FW of the frame memory 14, which is held in the register 91 at the timing of the decode start signal DS. The data output terminal of the register 91 is connected to the data input terminal of the register 92, and at the timing of the reference image read start signal RS, the address FW is transferred to the register 92 as the reference image read start address FR of the frame memory 14. maintain. The data output terminal of the register 92 is connected to the data input terminal of the register 93, and at the timing of the display image reading start signal PS, the address FR enters the register 93 as the display image reading start address ADR of the frame memory 14; maintain. These decoding start signals DS, reference picture read start signals RS and display picture read start signals PS are generated by the latch control circuit 85 in accordance with the decoded vertical synchronization signal DSYNC, the picture coding type PCT, and the winding mode MOD.

As shown in Figs. 9 and 10, the pulse period of the decoded vertical synchronizing signal DSYNC is equal to the field period. The pulse of the decoding start signal DS is generated in accordance with the odd-numbered pulse of the decoding vertical synchronizing signal DSYNC (that is, the pulse corresponding to the bottom field) when the winding mode MOD is the constant speed reproduction mode, and the pulse period is the frame period. When the winding mode MOD is in the double-speed regeneration mode, the pulse period is generated in accordance with each pulse of the decoded vertical synchronizing signal DSYNC, and the pulse period becomes the same as the field period. The pulse period of the reference picture reading start signal RS is basically the same as the pulse period of the decoding start signal DS, but when the picture coding type PCT indicates an I picture, the pulse corresponding to the I picture is omitted from the reference picture reading start signal RS. do. The display image read start signal PS is generated in accordance with the even-numbered pulse of DSYNC after the second decoded vertical synchronizing signal DSYNC, and corresponds to dividing the delayed decoded vertical synchronizing signal DVSYNC by 1/2. The display vertical synchronizing signal ESYNC is a signal obtained by doubling the period of the decoded vertical synchronizing signal DSYNC and delaying it.

As can be seen from the FW shown in Figs. 9 and 10, the registers 81 to 83 are cyclically selected in this order by the selector 84 when there are no B pictures, and the B pictures are present. Is selected by the selector 84 in consideration of realignment of the B images.

Next, the operation of the moving picture decoder configured as described above will be described. First, with reference to FIG. 9, the case where the winding mode MOD is a constant speed reproduction mode will be described.

The register 81 is selected by the selector 84.

(t0) The start address ADR1 of section 1 is held in the register 91 at the pulse timing of the decoding start signal DS, which is supplied to the decoder 87 as the decoded picture recording start address FW. Since it is an I picture, no pulse of the reference picture read start signal RS is generated. Then, the register 82 is selected by the selector 84.

The encoded image data DAT0 of the I picture I0 is read from the buffer memory 26 starting from the address FW. Decoded image data DAT0 is decoded by the decoder 27A, and this DAT0 is stored as a decoded image data DAT2 starting from the address FW in section 1 of the frame memory 14.

(tl) Since DAT0 is a P picture, a pulse of the reference picture reading start signal RS is generated, and the output FW = ADR1 of the register 91 is held in the register 92 at the timing of this pulse, and this register 92 Is supplied to the decoder 27A as the reference picture read start address FR. Next, at the pulse timing of the decoding start signal DS, the start address ADR2 of section 2 is held in the register 91, and this start address ADR2 is supplied to the decoder 27A as the decoded picture recording start address FW. Next, the register 83 is selected by the selector 84.

The encoded data DAT0 of the P picture P1 is read from the buffer memory 26. The decoder 27A decodes the encoded image data DAT0 on one side and generates prediction error data. On the other side, the data DAT4 of the I image I0 is read from the section 1 of the frame memory 14 at the head of the address FR and predicted. Image data is generated. The predictive error data is added to the predictive picture data to generate decoded picture data DAT2, which is stored in section 2 of the frame memory 14 starting from the address FW.

(t1.5) The contents FR = ADR1 of the register 92 are held in the register 93 at the pulse timing of the display image read start signal PS.

By the decoder 27A, the data DAT5 of the I picture I0 is read from the section 1 of the frame memory 14, starting with the address ADR as the display data.

(t2) The output FW = ADR2 of the register 91 is held in the register 92 at the pulse timing of the reference picture read start signal RS, and the contents of this register 92 are the decoder 27A as the reference picture read start address FR. Supplied to. Next, at the pulse timing of the decoding start signal DS, the start address ADR3 of section 3 is held in the register 91, and this start address ADR3 is supplied to the decoder 27A as the decoded picture recording start address FW. The register 81 is selected by the selector 84.

The encoded data DAT0 of the P picture P2 is read from the buffer memory 26. The decoder 27A decodes the encoded image data DAT0 on one side and generates prediction error data. On the other side, the data DAT4 of the P image P1 leads the address FR as the reference data from section 2 of the frame memory 14. Is read to generate predictive image data. The prediction error data is added to the predictive image data to generate decoded image data DAT2, which is stored in section 3 of the frame memory 14 with the address FW at the head.

(t2.5) The contents FR = ADR2 of the register 92 are held in the register 93 at the pulse timing of the display image read start signal PS.

By the decoder 27A, the data DAT5 of P1 is read starting from the address ADR as display data from section 2 of the frame memory 14.

Hereinafter, the above processing is performed, and the decoding of the image data and the output of the display data in the same-speed reproduction mode are performed.

With reference to FIG. 10, the case where the winding mode MOD is the double speed reproduction mode will be described.

In FIG. 10, the winding mode MOD is the constant speed reproduction mode until time t2, and the winding mode MOD is switched to the double speed reproduction mode at time t2 by the mode switching operation of the operator. Up to time t2, the same operation as shown in FIG. 9 is performed.

(t2.5) Processing at time t2.5 and processing at time t3 in FIG. 9 are performed.

That is, the output FW = ADR3 of the register 91 is held in the register 92 at the pulse timing of the reference picture read start signal RS, and the contents of the register 92 are transmitted to the decoder 27A as the reference picture read start address FR. Supplied. Next, at the pulse timing of the decoding start signal DS, the start address ADR1 of the section 1 is held in the register 91, which is supplied to the decoder 27A as the decoded picture recording start address FW. The register 22 is selected by the selector 84. The encoded data DAT0 of the P picture P3 is read from the buffer memory 26. The decoder 27A decodes the coded image data DAT0 on one side and generates prediction error data. On the other side, the data DAT4 of the P image P2 leads the address FR as reference data from section 3 of the frame memory 14. Is read to generate predictive image data. The predictive error data is added to the predictive picture data to generate decoded picture data DAT2, which is stored in section 1 of the frame memory 14 starting from the address FW.

At the pulse timing of the display image read start signal PS, the contents FR = ADR3 of the register 92 are held in the register 93. By the decoder 27A, the data DAT5 of the P picture P2 is read from the section 3 of the frame memory 14 at the beginning of the address DAPA as data for display.

(t3) The same processing as that at time t2 is performed.

That is, the output FW = ADR1 of the register 91 is held in the register 92 at the pulse timing of the reference picture read start signal RS, and this output is supplied to the decoder 27A as the reference picture read start address FR. Next, at the pulse timing of the decoding start signal DS, the start address ADR2 of section 2 is held in the register 91, which is supplied to the decoder 27A as the decoded picture recording start address FW. The register 83 is selected by the selector 84.

The encoded data DAT0 of the P picture P4 is read from the buffer memory 26. In addition, the decoder 27A decodes the coded image data DAT0 on one side and generates prediction error data. On the other side, the data DAT4 of the P image P3 is the address FR as the reference data from section 1 of the frame memory 14. Is read at the beginning to generate predictive image data. The predictive error data is added to the predictive image data to generate decoded image data DAT2, which is stored in section 2 of the frame memory 14 starting from the address FW.

Hereinafter, the above-described processing is performed, and the image is decoded at twice the speed in the case of the constant speed reproduction mode, and the display image is output by filtering one image.

In the third embodiment, the decoded image data DAT2 is written to the frame memory 14 by using the section address management unit 70a as shown in FIG. 8B, and the reference image data DAT4 from the frame memory 14 is recorded. And since display image data DAT5 is read out, it becomes possible to reproduce an image in the double speed reproduction mode even if a B image does not exist.

In the above description, the case where the coded data of the B picture does not exist has been described. However, even if the coded data of the B picture is included, display image data can be output at twice the speed as described above.

[4th Embodiment]

FIG. 11 shows the configuration of main parts of the system decoder 110A according to the fourth embodiment of the present invention, which corresponds to FIG. 20A.

The clock pulse CLK and the system time clock STC are the same as the subtraction circuit 131, the D / A converter 133, the low pass filter 134, the voltage controlled oscillator 135 and the counter 132, as in FIG. 20A. It is generated by the PLL circuit configured. The clock pulse CLK is supplied to the clock input terminal of the N-definition counter 1391 and counted, and the count value is supplied to the decoders 1392 and 1393. The decoders 1392 and 1393 detect that this count value matches a predetermined value and generate pulses of the sync pulse USYNC and the vertical sync pulse VSYNC, respectively. The periods of the sync pulses USYNC and VSYNC are equal to the field periods, and VSYNC is equal to the delay of USYNC by δ shown in FIG. The synchronous pulse USYNC is divided into 1/2 by the frequency-divider front edge detection circuit 394, the rising of the pulse is detected, and the pulse is pulsed to start reading as shown in FIG. It is supplied to the video decoder 113 of FIG. 19 as a pulse ESYNC.

The clock pulse CLK is also supplied to the clock input terminal of the counter 140 and counted, and the count value is supplied to the comparator 38 as a system time clock STCA. Comparator 38 compares this STCA with the PTS from PTS / ADR table register 136 and outputs a coincidence pulse EQ when both match. STCA is used for processing video data. Since the decoding time stamp DTS according to the MPEG-2 system is not necessarily present, the read start pulse DSYNC is generated with a predetermined phase difference from the read start pulse ESYNC.

The selector 141 is supplied with a PTS and an SCR, one of which is selected and supplied to the data input terminal of the counter 140.

The control circuit 137A is supplied with CLK, SCR, ESYNC, and EQ, and the control circuit 137A accordingly corresponds to the counter 132, the PTS / ADR table register 136, the counter 140, and the selector 141. Control as follows.

The selector 141 is initially switched to the SCR side. When the control circuit 137A detects the first SCR, the control circuit 137A activates a load signal supplied to the counters 132 and 140 to load the SCRs into the counters 132 and 140. As a result, the output of the subtraction circuit 131 becomes zero, and the frequency of the clock pulse CLK becomes the standard value of the VCO 135. In addition, in tt0 of FIG. 12 (where t is real time), STC = STCT is satisfied.

Immediately after the load, control circuit 137A selects PTS for selector 141. The control circuit 37A counts the error time Δ shown in FIG. 12 in the clock pulse CLK after receiving the coincidence pulse EQ until receiving the next read start pulse ESYNC, and when Δ or T-Δ is equal to or larger than a predetermined value. At the timing of the read start pulse ESYNC, the load signal to the counter 140 is activated to load the PTS to the counter 140 (where T is a frame period). 12, PTS = PTS0 of the picture PIC0 is loaded into the counter 140 at t = t0, and the value of STCA is shifted from the value of STC.

The control circuit 37A next reads, from the PTS / ADR table register 136, the PTS and read start address ADR of the image to be displayed next to the PTS / ADR table register 136. Next, as shown in FIG.

In Fig. 12, when t = t1, PTS = PTS1, the reading of the picture PIC1 is started from the frame memory 14, and at t = t2, PTS = PTS2 is started, and the reading of the picture PIC2 from the frame memory 14 is started. do.

In the fourth embodiment, the storage capacity of the frame memory 14 is reduced to 3 frames or less (more than 2 frames) as in the case of FIG. 2, so that the read start time of the display image data VDAT5 from the frame memory 14 is reduced. Even if it shifts from STC = PTS, the time from the read start pulse ESYNC to the vertical synchronizing pulse VSYNC becomes almost equal to the optimum value δ, and as a result, the storage capacity of the frame memory 14 can be reduced.

δ may be zero.

Since the system time clock STCA is different from that of the STC, when the reading of the encoded image data VDAT0 from the buffer memory 26 is delayed, the storage capacity of the buffer memory 26 needs to be increased, but the buffer memory 26 is greatly increased. Since the compressed data is recorded, the increase in the storage capacity of the buffer memory 26 is very small compared to the decrease amount of 3 frames or less in the frame memory 14 storage capacity.

[Fifth Embodiment]

FIG. 13 shows the configuration of main parts of the system decoder 110B according to the fifth embodiment of the present invention corresponding to FIG.

In this system decoder 110B, a self-propelled clock generator instead of a PLL circuit composed of a subtraction circuit 131, a D / A converter 133, a low pass filter 134, a voltage controlled oscillator 135 and a counter 132. By using 142, the configuration of the system decoder 110B is simplified, and the period of the clock pulse CLK is more accurate than in the case of feedback control. Since the control circuit 137B does not need to generate a load signal for the counter 132 in FIG. 11, the configuration is simpler than that of the control circuit 137A. 12, the coincidence pulse EQ output from the comparator 38 is used as the read start pulse ESYNC.

The system decoder 110B is the same as the system decoder 110A of FIG. 11.

[Sixth Embodiment]

FIG. 14 shows the configuration of main parts of the system decoder 110C according to the sixth embodiment of the present invention corresponding to FIG.

The time δ in FIG. 12 is less than 1 ms, and time δ can be ignored depending on the configuration or processing speed of the video output circuit 115 in FIG. 20. Therefore, in the system decoder 110C, the decoder 1393 in FIG. 13 is omitted, and the vertical sync pulse VSYNC is also used as the sync pulse USYNC in FIG. Further, by supplying one bit of the data output of the counter 140, for example, the most significant bit, to the N binary counter 1391 as the clock?, The number of bits of the N binary counter 1391A is supplied to the N binary counter (Fig. 13). 391). Furthermore, the selector 141 of FIG. 13 is omitted, and the PTS is directly supplied to the data input terminal of the counter 140. Since the control circuit 137C does not need to control the selector 141, the configuration is simpler than that of the control circuit 137B of FIG. 13.

The control circuit 137C counts the clock pulse CLK after receiving the coincidence pulse EQ and receiving the read start pulse ESYNC, as shown in FIG. The load signal to the counter 140 is made active to load the PTS to the counter 140. The control circuit 137C then reads from the PTS / ADR table register 136 the PTS and read start address ADR of the image to be displayed next to the PTS / ADR table register 136.

Although the present invention has been described as a preferred embodiment, the present invention is not limited to the above embodiments and can be variously changed and modified without departing from the spirit and core features of the invention.

For example, in the first and second embodiments, the physical banks for the B picture may be secured in a predetermined region in the frame memory 14A. Since the storage capacity of the physical section is managed by dividing it into a top field and a bottom field, it may be an odd number of half of one macro block line. The frame memory 14A and the buffer memory 26 may be soft division regions in the memory, and the buffer memory control circuit 25 and the frame memory control circuit 29 are constituted by one block so that the address counter 251, 291 may be integrated into one address counter. In addition, you may apply when the other image reduction conversion circuit is used instead of the letter box conversion circuit 20.

In the third embodiment, for example, in the case where the winding mode MOD is in the double speed reproduction mode, the system control circuit 70 doubles the operation of the decoder 27A and the display image data from the frame memory in accordance with the skip signal. A skip signal may be supplied to the decoder 27A so as to skip reading one picture for each picture. In this case, the control circuit 12 may double the operation of the decoder 27A by doubling its own control operation. The bank number may be converted to the bank start address by using the bank number instead of the bank start addresses ADR1 to ADR3. The bank start addresses ADR1 to ADR3 or bank numbers may be output by wiring means for supplying the power supply potential and the ground potential without using the registers 21 to 23. Furthermore, in the case of including the B picture, the double speed reproduction mode may be realized by the conventional method, and in the case of not including the B image, the double speed reproduction mode may be realized by the method of the present invention.

In the fourth to sixth embodiments of the present invention, the address of the register in which the PTS is stored in the PTS / ADR table register 136 is started reading without writing the read start address ADR in the PTS / ADR table register 136. The read start address ADR may be written in correspondence with the address ADR or in correspondence with the order of storing the PTS in the PTS / ADR table register 136 in another part, for example, a part of the frame memory 14.

As described above, it is possible to provide an image data processing method and apparatus which can reduce the manufacturing cost by eliminating the need to reduce the memory capacity or increase the operating frequency for the image reduction processing with a simpler configuration.

Further, a moving picture decoder capable of reproducing an image in the double-speed winding mode even when no B picture exists can be provided, and a system decoder capable of reducing the capacity of the frame memory 14 and a moving picture decoder using the same can be provided. Can be.

Claims (28)

When m = (image data amount for one frame) / (image data amount for one bank) and m and p are integers satisfying 2 ≦ pm, the memory has a storage area of p, and In order to record the image data of the logical bank number or to read the image data of the logical bank number recorded in the memory, image data of one frame is divided into m banks and logical bank numbers are assigned to each bank. A first control circuit for outputting a logical bank number at the time; and when the physical bank numbers are assigned to the p banks, respectively, the logical bank numbers are assigned to one of the state physical bank numbers, and the corresponding physical banks are read. Each time of the completion, the assignment state of the logical bank number is opened to the empty physical bank number, and the logical bank number output from the first control circuit is changed to the logical bank number. A bank management circuit for converting into a physical bank number to which is assigned a memory, and a memory control circuit for sequentially accessing image data of the physical bank starting from an address corresponding to the converted physical number. Data processing unit. 2. The bank management circuit according to claim 1, wherein when the allocation control signal is active, the bank management circuit stores the relationship between the physical bank number supplied and the logical bank number to perform the allocation, and assigns the logical bank number in accordance with the allocation. A logical / physical bank number converting unit for converting to the physical bank number, an allocation state storage unit indicating which of the physical bank numbers is empty or allocated, and responding to a physical bank allocation request from the first control circuit The empty state is detected with reference to the contents of the allocation state storage unit, and the detected empty state is converted into the allocation state, and the physical bank number converted into the allocation state and the allocation control signal converted into the active state. And a state physical bank detection / allocation section for supplying a signal to the logical / physical bank number conversion section. Data processing apparatus. 3. The physical apparatus of claim 2, wherein the bank management circuit detects that the memory control circuit has completed access for one bank and makes the allocation state corresponding to the one bank accessed by the allocation state storage unit to be in the empty state. And a bank opening portion. The empty state physical bank detection / allocation unit detects the empty state with reference to the contents of the allocation state storage unit in response to a physical bank search request, and sets the detected empty state to the allocated state. A state-state physical bank detection section for converting, supplying the physical bank number converted to the allocation state to the logical / physical bank number conversion section, and outputting an allocation completion notice; outputting the physical bank search request; And a physical bank allocating unit for supplying the logical / physical bank number converting unit to the logical / physical bank number converting unit when the allocation request and the allocation completion notification are received. 2. The memory according to claim 1, wherein the memory includes a buffer storage area for coded image data, and the memory control circuit temporarily stores coded image data in the buffer memory area to delay the coded image data, and stores the buffer memory area. The decoder further reads the encoded image data from the apparatus, and the image data processing apparatus further includes a decoder for decoding the encoded image data read out from the buffer storage area and supplying the encoded image data to the memory. In response to the slow regeneration request for reproducing at a speed of, the top field and the bottom field are read N times from the buffer storage area of the memory repeatedly for the memory control circuit, and the p bank is stored in accordance with the readout. To perform the above recording and reading of the decoded image data in the area. Image data processing apparatus characterized in that the. 6. The image data processing apparatus according to claim 5, wherein the first control circuit performs the same operation as that performed for the slow reproduction request of speed 1 / ∞ in response to the pause reproduction request. The image data processing apparatus according to claim 1, wherein the image data is MPEG data, and a storage capacity of each physical bank is an integer multiple of one macroblock line. The image data processing apparatus according to claim 1, wherein the image data is MPEG data, and the storage capacity of each physical bank is an odd multiple of one macroblock line. When m = (image data amount for one frame) / (image data amount for one bank) and m is an integer, the image data is divided into m logical banks, and a logical bank number is assigned to the logical bank. assuming that p is an integer satisfying 2 ≦ pm, allocating a physical bank number to the physical bank by allocating a storage area of a p physical bank in a memory for storing image data; Is assigned to one of the public physical bank numbers, the allocated physical bank number is opened empty every time the reading of the corresponding physical bank is completed, and the allocated logical bank number is assigned to the corresponding physical bank number. Converting and sequentially accessing image data of one physical bank starting from an address corresponding to the converted physical number; Image data processing method. 10. The method according to claim 9, wherein the coded image data is temporarily stored in a buffer storage area of the memory in order to delay the coded image data, and the coded image data is identical in response to a slow reproduction request of speed 1 / N. Repeatedly reading the top field and the same bottom field from the buffer storage area N times, decoding the coded image data read from the buffer storage area, and supplying the coded image data to the physical bank. The image data processing method further comprises the step of. A memory control for temporarily storing decoded image data in the memory, in the memory, generating a predictive image with reference to the decoded image data in the memory, and reading the decoded image data from the memory in the order of the original image before encoding; A predictive image generation circuit, a reduction conversion circuit for converting the decoded image data so that the image is reduced in units of blocks, and whether or not to pass the reduced conversion circuit before recording the decoded image data in the memory; And a switching circuit for selecting whether or not to pass the reduced conversion circuit after reading the decoded image data from the memory, wherein the memory control / predictive image generation circuit includes whether or not decoded image data is written to the memory. Whether or not it is read from Degas and whether or not the reduction mode, according to whether or not the decoded image data is a non-reference image, the image data processing device, characterized in that for controlling the switching circuit. The decoded image data according to claim 11, wherein the control / prediction generation circuit is configured to perform the decoded image data when the display mode is a reduced mode and the decoded image data is a non-reference image while recording decoded image data in the memory. Control the switching circuit to pass through the reduction conversion circuit and to write to the memory; otherwise control the switching circuit so that the decoded image data is written to the memory without passing through the reduction conversion circuit; While the decoded image data is read from the memory, the decoded image data read from the memory does not pass through the reduced conversion circuit in the first case or in the second case when the display mode is not the reduced mode. To control the switching circuit and not the first case; If not, the image data processing apparatus is characterized in that the switching circuit is controlled so that the decoded image data read out from the memory passes through the reduced conversion circuit. A memory, a reduction conversion circuit for converting the image data so that the image is reduced in units of blocks, whether or not to pass the reduction conversion circuit before recording the image data in the memory, and the image data from the memory. A switching circuit for selecting whether or not to pass the reduction conversion circuit after reading, whether the image data is written to or read from the memory, whether the display mode is the reduction mode, and the decoding And a control circuit which controls the switching circuit in accordance with whether or not the image data is a non-reference image. An image data processing method for decoding coded image data having a memory for temporarily storing a decoded image of the decoded image data and a reduced conversion circuit for reducing the decoded image size, wherein the decoded image data is recorded in the memory. In the first case where the display mode is the reduced mode and the decoded image data is a non-reference image, the decoded image data is passed through the reduced conversion circuit to be recorded in the memory. Writing the image data into the memory without passing it through the reduction conversion circuit, and while reading the decoded image data from the memory for display, the first case or the second case when the display mode is not the reduced mode. The reduced image conversion circuit converts the decoded image data into And reading from the memory without passing through and passing the decoded image data from the memory to the reduction conversion circuit in the case of neither the first case nor the second case. Treatment method. Decoded image data is decoded and recorded in the frame memory to obtain a frame memory and decoded image data, reference image data is read from the frame memory to generate predictive image data, and the decoded image data from the frame memory is read. A decoder for reading as display image data, and when the winding mode is a double speed reproduction mode, the decoder decodes the coded image data at an average speed of twice the normal speed, writes the encoded image data to the frame memory, and And a control circuit which reads the reference picture data, and causes the decoder to filter the decoded picture data as the display picture data by filtering one picture from the frame memory at a normal speed. . 16. The decoding circuit according to claim 15, wherein the control circuit is supplied with a decoding synchronization signal having a pulse period equal to a field period, an image coding type, and the winding mode, and the control circuit performs the decoding synchronization signal when the winding mode is an equal-speed reproduction mode. Pulses of the decoding start signal are generated by filtering every one pulse of the signal, and when the winding mode is the double speed reproduction mode, the pulses of the decoding start signal are generated according to each pulse of the decoding synchronization signal, and the image encoding type is I picture. Except when is indicated, a pulse of the reference image reading start signal is generated in response to the pulse of the decoding start signal, and the display image reading start signal is generated in response to a signal that is divided into 1/2 and delayed the decoding synchronization signal. And the decoder starts decoding in synchronization with the decoding start signal and starts reading the reference picture. In synchronization with the call initiation reading of the reference image data, and the moving picture decoding apparatus, characterized in that for starting the reading of the display image data in synchronism with the displayed image reading start signal. 17. The control circuit according to claim 16, wherein the control circuit maintains a decoded image write start address in the first register at the first, second, and third registers and the pulse timing of the decode start signal. A register control circuit for holding an output of the first register in the second register at a pulse timing of, and holding an output of the second register in the third register at a pulse timing of the display image read start signal; The decoder receives the output of the first register as the decoded picture recording start address, receives the output of the second register as a reference picture read start address, and outputs the output of the third register to a display image read start address. A video decoding apparatus, characterized in that receiving as a. 18. The moving picture decoding apparatus according to claim 17, wherein the register control circuit maintains start addresses of three regions in the first register in sequential periods. 18. The video decoding apparatus of claim 17, wherein a data output terminal of the first register is connected to a data input terminal of the second register, and a data output terminal of the second register is connected to a data input terminal of the third register. . 16. The control circuit according to claim 15, wherein when the winding mode is a double speed reproduction mode, the control circuit doubles the operation of the decoder and skips reading of the display image data from the frame memory every picture. Moving picture decoding device. 21. The moving picture decoding apparatus according to claim 20, wherein said control circuit doubles the operation of said decoder to double the operation of said decoder. A circuit for generating a clock pulse, a counter for counting the clock pulse and outputting the count value as a system time clock, a synchronous pulse generating circuit for generating a synchronous pulse of frame period in accordance with the clock pulse, and a presentation time supplied A storage means for temporarily storing a stamp, a comparison circuit for detecting that the system time clock coincides with a presentation time stamp read from the storage means, and the presentation time stamp corresponding to an image reproduction sequence in response to the synchronization pulse. A control circuit which reads from the storage means and loads the presentation time stamp read from the storage means into the counter, wherein a pulse generated when detecting the sync pulse or the coincidence is a display image data read start pulse. Used as A system decoder, characterized by. 23. The apparatus of claim 22, wherein the control circuit sends the presentation time stamp to the counter when the time [Delta] and time {(frame period)-[Delta]} until the sync pulse is generated after the match is detected is greater than a set value. And a system decoder for loading. 23. The apparatus of claim 22, further comprising a selector for selecting one of a system clock reference and a presentation time stamp read from the storage means and supplying the counter to the selector, wherein the control circuit is configured to supply the selector with the system clock reference. Select the presentation time stamp, and load the output of the selector into the counter in response to the sync pulse. 25. The system decoder of claim 24, wherein the control circuit selects, for the selector, the system clock reference initially supplied and then selects the presentation time stamp. 23. The system decoder of claim 22, wherein the circuit for generating the clock pulse is a PLL circuit for feedback control such that the count value matches the system clock reference when the system clock reference is provided. 23. The system decoder of claim 22, wherein the circuit for generating the clock pulses is a self propagated clock generation circuit. A buffer circuit for temporarily storing image data supplied and encoded in the MPEG method, a memory control circuit for reading encoded image data in response to an encoded image reading start pulse, a frame memory, and reading from the buffer circuit for generating decoded image data. Decoded coded image data, store the decoded image data in the frame memory, read the decoded image data as reference image data from the frame memory, read the decoded image data from frame memory, and display image data. An image decoder for displaying in synchronization with a read start pulse, and a system decoder, wherein the system decoder includes a circuit for generating a clock pulse, a counter for counting the clock pulse, and outputting the count value as a system time clock; According to the clock pulse Therefore, a synchronous pulse generating circuit for generating a synchronous pulse of a frame period, storage means for temporarily storing the supplied presentation time stamp, and a comparison circuit for detecting that the system time clock matches the presentation time stamp read out from the storage means. And a control circuit that reads the presentation time stamp corresponding to the image reproduction order from the storage means in response to the sync pulse, and loads the presentation time stamp read from the storage means into the counter, A moving picture decoding apparatus, characterized in that a pulse generated when detecting a synchronization pulse or said coincidence is used as a display image data read start pulse.