JPH10261553A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a semiconductor substrate from suffering a loss by providing a groove for relaxing the concentration of stress to the semiconductor substrate due to the difference in thermal expansion between the semiconductor substrate and a support member at a region excluding a part where the circuit of the semiconductor substrate is provided. SOLUTION: Circuit regions 13A and 13B for first and second power FETs, respectively, are provided on a surface 12 of a semiconductor substrate 11 that is made of GaAs. Then, a groove 14 with a width of W and a depth of H for subdividing both circuit regions 13A and 13B is formed at a region excluding the parts of the circuit region 13A of the first power FET and the circuit region 13B of the second power FET being provided at the semiconductor substrate 11. The groove 14 relaxes the concentration of stress to the semiconductor substrate 11 due to the difference in thermal expansion between the semiconductor substrate 11 and a lead frame that is a support member for supporting it, thus reducing a stress that is operated on the semiconductor substrate 11 and preventing the semiconductor substrate 11 from suffering a loss.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IC chip formed by incorporating a circuit into a semiconductor substrate and fixed to a support member such as a lead frame of a circuit substrate or a package. Especially,
The present invention relates to a semiconductor element suitable for an IC chip which itself becomes a large-capacity heat source, such as a power FET for high output.

[0002]

2. Description of the Related Art An IC chip formed by incorporating a circuit in a semiconductor substrate is fixed to the circuit substrate, for example, by using a circuit substrate made of a material different from that of the semiconductor substrate as a supporting member, or a package. Is fixed to the lead frame as a supporting member. In a semiconductor package, an IC chip is sealed with a mold made of, for example, a resin material as a support member.

[0003]

The semiconductor substrate of such an IC chip is supported by the above-mentioned supporting member having a different coefficient of thermal expansion from the semiconductor substrate. Stress may be concentrated on the semiconductor substrate due to a difference in thermal expansion with the support member, and the concentration of the stress may cause a defect in the semiconductor substrate. In particular, in an IC chip incorporating a power FET for high output, which itself becomes a large-capacity heat source, local stress on the semiconductor substrate due to a difference in thermal expansion is strongly concentrated.
The concentration of stress on the semiconductor substrate has been a major problem.
Therefore, by preventing stress concentration on the semiconductor substrate due to the difference in thermal expansion between the semiconductor substrate of the IC chip and the supporting member supporting the IC chip and the loss of the semiconductor substrate due to this, a semiconductor element having excellent durability is provided. There has been a demand for the emergence of a technology that can provide the above.

[0004]

The present invention adopts the following constitution in order to solve the above points. <Structure> The present invention includes a semiconductor substrate in which a circuit is incorporated, and in a semiconductor element used when the semiconductor substrate is fixed to a supporting member by mounting, in a region excluding a portion where the circuit of the semiconductor substrate is provided, A groove is provided for alleviating stress concentration on the semiconductor substrate due to a difference in thermal expansion between the semiconductor substrate and the support member.

<Operation> In a semiconductor device according to the present invention, a groove is provided in a region of a semiconductor substrate other than a portion where a circuit is provided. In a high-temperature atmosphere, if a stress is to be generated in the semiconductor substrate due to a difference in thermal expansion between the semiconductor substrate and the supporting member to which the semiconductor substrate is fixed, the groove allows partial deformation of the semiconductor substrate in the groove. Concentration of strong stress on a local portion of the substrate is prevented. Thus, according to the present invention,
Since the concentration of the stress acting on the semiconductor substrate can be reduced and the stress acting on the semiconductor substrate can be reduced,
The semiconductor substrate can be prevented from being deficient.
A semiconductor element having excellent durability can be provided.

[0006] The groove may be a void. Alternatively, the groove may be filled with an elastic member having an insulating property such as rubber that allows partial deformation of the semiconductor substrate. Since the concentration of stress on the semiconductor substrate can be alleviated more effectively by making the groove empty, it is desirable to make the groove empty.

It is desirable that the depth dimension of the groove be approximately one half of the thickness dimension of the semiconductor substrate. Thereby, a predetermined strength can be ensured in the semiconductor substrate itself.

It is desirable that a circuit to be incorporated in a semiconductor substrate be divided into a plurality of circuit portions, the plurality of circuit portions be formed on the semiconductor substrate at intervals, and a groove be provided between the circuit portions. This example of division is particularly advantageous for a semiconductor device such as an IC chip incorporating a power FET for high output, which itself becomes a large-capacity heat source.
Heat is most likely to concentrate between a plurality of circuit portions formed by dividing the power FET circuit. By forming a groove between the circuit parts where heat is easily concentrated and a groove that promotes heat dissipation from the power FET as a heat source and allows partial deformation of the semiconductor substrate, concentration of stress due to a difference in thermal expansion is reduced. It can be effectively prevented.

A groove can be formed on one of the front surface and the back surface of the semiconductor substrate in which the circuit is incorporated. It is advantageous to form the grooves on the back side of the semiconductor substrate in that the circuits incorporated in the semiconductor substrate are not divided and, therefore, do not change the pattern of the circuit. However, since a circuit as a heat source is provided on the surface of the semiconductor substrate, it is desirable to form a groove on the surface of the semiconductor substrate in order to effectively prevent concentration of thermal stress on the semiconductor substrate. . Instead of these examples, grooves can be formed on both surfaces of the semiconductor substrate.

Further, the groove can be formed by dicing or etching. It is desirable to form the groove by etching in view of the processing accuracy such as the position of the groove and the width of the groove. The formation of the groove in the semiconductor substrate can be performed in the manufacturing process of the device, and instead,
After completion of the device, it can be performed prior to its mounting.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. FIG. 1 shows an example in which a semiconductor device according to the present invention is applied to a power FET IC chip. As shown in FIG. 1, a power FET IC chip 10 according to the present invention includes a semiconductor substrate 11 made of, for example, GaAs. In the example shown, a circuit area 1 for the first power FET and the second power FET is provided on the surface 12 of the semiconductor substrate 11.
3A and 13B are provided respectively. Between the circuit region 13A of the first power FET and the circuit region 13B of the second power FET, both circuit regions 13A and 13A
A groove 14 that partitions 3B is formed. The width dimension of the groove 14 is indicated by W, and the depth dimension is indicated by H.

In each of the circuit regions 13A and 13B, as well known in the art, a power FET 15 composed of, for example, an active element such as a transistor and a passive element such as a resistor and a resistor is incorporated as a circuit part. Have been. In the illustrated example, each of the circuit regions 13A and 1A
The 3B power FET 15 has, as its pads, one gate pad 16, two source pads 17 arranged on both sides of the gate pad 16 and connected in parallel with each other, and opposite to the pads 16 and 17. There are three drain pads 18 connected in parallel on the side.

The groove 14 is formed during the process of incorporating the power FET 15 into the semiconductor substrate 11, or
After the completion of assembling of No. 5, it can be formed by, for example, etching or dicing. The depth dimension H of the groove 14 can be set to a value less than half or more than half the thickness dimension D of the semiconductor substrate 11. In order to suppress weakening, secure a predetermined strength, and sufficiently allow thermal deformation of the semiconductor substrate 11, it is desirable that the depth dimension H be approximately half the thickness dimension D of the semiconductor substrate 11. .

Power FET IC chip 10 according to the present invention
Then, as a mounting form, for example, the semiconductor substrate 11
On the back surface 19, the semiconductor substrate 11 is fixed to a lead frame (not shown) made of a different material. After that, power F
Each pad 1 of the power FET 15 of the ETIC chip 10
6, 17 and 18 are electrically connected to the corresponding lead frames via wire bonding (not shown). If necessary, the power FET IC chip 10 and the lead frame are sealed with a resin molding material.

In the above-mentioned wire bonding step in the manufacturing process of the power FET IC chip 10, the semiconductor substrate 1
Since the pad provided on the surface 12 of the first substrate is heated to a high temperature, the semiconductor substrate 11 and the lead frame supporting the semiconductor substrate are heated via the pad.
Since the semiconductor substrate 11 and the lead frame supporting the same are made of different materials, a relatively strong stress tends to act on the semiconductor substrate 11 due to a difference in thermal expansion therebetween. However, a groove 14 is provided in the semiconductor substrate 11 on which the stress acts, and the groove 14 allows local deformation of the semiconductor substrate 11 in the space, so that the stress acting on the semiconductor substrate 11 can be reduced. This allows
Defects in the semiconductor substrate 11 are reliably prevented.

The power FET IC chip 10 itself becomes a large-capacity heat source. Therefore, power FE
By the operation of the TIC chip 10, the semiconductor substrate 11,
The lead frame and the molding material that seals them are heated strongly. The semiconductor substrate 11, the lead frame, and the molding material having different coefficients of thermal expansion cause thermal expansion, and a strong stress tends to act on the semiconductor substrate 11 due to a difference in thermal expansion therebetween.

At this time, heat is most easily concentrated on the semiconductor substrate 11 between the first power FET circuit region 13A and the second power FET circuit region 13B. Since the groove 14 is provided in the region where the heat is likely to concentrate, a strong stress that tends to act on the semiconductor substrate 11 due to a difference in thermal expansion due to the deformation of the groove 14 of the semiconductor substrate 11 into a void is absorbed. . As a result, the concentration of stress on the semiconductor substrate 11 is effectively reduced, so that the power FET IC chip 1
0 semiconductor substrate 11 is reliably prevented from being lost. Therefore, the reliability and durability of the power FET IC chip 10 can be improved.

FIG. 2 shows the power F of Embodiment 2 according to the present invention.
3 shows an ETIC chip. Power FET IC shown in FIG.
In the chip 10, a groove 14 was formed in the surface 12 of the semiconductor substrate 11 on which the pad of the power FET 15 was provided. Instead of this example, as shown in FIG. 2, a groove 14 'similar to that described above can be provided on the back surface 19 of the semiconductor substrate 11. Power FET IC shown in FIG.
In the chip 10 ', the same components as those shown in FIG. 1 except for the groove 14' are denoted by the same reference numerals.

The power FET IC chip 10 'is
On the back surface 19 of the semiconductor substrate 11 provided with 4 ', the semiconductor substrate 11 is fixed to, for example, the lead frame as a support member.
Under a high-temperature atmosphere, a strong stress tends to act on the back surface 19 of the semiconductor substrate 11 serving as a fixing surface thereof due to a difference in thermal expansion between the semiconductor substrate 11 and the lead frame. However, since the groove 14 ′ is provided on the back surface 19 of the semiconductor substrate 11, the concentration of the stress on the semiconductor substrate 11 is effectively reduced by deformation of the portion including the groove 14 ′ of the semiconductor substrate 11. Thus, the semiconductor substrate 11 of the power FET IC chip 10 'can be prevented from being damaged, and the durability of the power FET IC chip 10' can be increased. By forming the groove 14 'on the back surface opposite to the surface on which the circuit pattern is formed, even a semiconductor device such as a single FET composed of a single circuit can have its circuit pattern formed. And the groove 14 'can be formed at the optimum position.

As described above, the two power FETs 15 and 15 are incorporated in the power FET IC chip 10 or 10 ', and the surface 1 of the GaAs semiconductor substrate 11 between the two power FETs 15 and the circuit portion.
The example in which the groove 14 defining the void is formed on the second or back surface 19 has been described. Instead, the inside of the groove can be filled with an elastic member having an insulating property such as rubber that allows partial deformation of the semiconductor substrate. The groove can be formed by a straight line, a curve, or a combination of both, according to the circuit pattern provided on the semiconductor substrate. Also, various cross-sectional shapes such as a V-shape or a U-shape can be adopted as the cross-sectional shape of the groove. In addition, a reinforcing rib composed of a part of the semiconductor substrate can be appropriately formed in the groove, whereby a decrease in the strength of the semiconductor substrate due to the formation of the groove can be effectively prevented.

It is not necessary to provide grooves in all portions of the semiconductor substrate except for the portions where circuits are provided, and the above-described grooves may be provided appropriately in regions where stress concentration is likely to occur. it can. Also, if necessary, grooves can be formed on both surfaces of the semiconductor substrate.

The present invention can be applied to various semiconductor elements such as IC chips formed by incorporating a bipolar circuit into a semiconductor substrate made of silicon, for example, instead of the above-described specific examples.

[0023]

According to the semiconductor device of the present invention, as described above, the semiconductor substrate and the supporting member to which the semiconductor substrate is fixed are formed by providing the groove in the region of the conductive substrate other than the portion where the circuit is provided. Since the concentration of stress on the semiconductor substrate due to the difference in thermal expansion of the semiconductor substrate is alleviated, the stress acting on the semiconductor substrate can be reduced, and therefore, the semiconductor substrate can be prevented from being damaged. An excellent semiconductor element can be obtained.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a power FET IC chip of Example 1 according to the present invention.

FIG. 2 is a perspective view showing a power FET IC chip of Example 2 according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 (power FET IC chip) semiconductor element 11 semiconductor substrate 12, 19 surface of semiconductor substrate 14 groove 15 (power FET) circuit

Claims (6)

[Claims] 1. A semiconductor device having a circuit mounted on a semiconductor substrate fixed to a support member, wherein the semiconductor substrate and the support member are provided in a region of the semiconductor substrate other than a portion where the circuit is provided. A groove for reducing concentration of stress on the semiconductor substrate due to a difference in thermal expansion of the semiconductor element. 2. The semiconductor device according to claim 1, wherein the groove defines a space in the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein a depth dimension of the groove is approximately one half of a thickness dimension of the semiconductor substrate. 4. The semiconductor device according to claim 1, wherein the circuit includes a plurality of circuit portions formed on the semiconductor substrate at intervals from each other, and the groove is provided between the circuit portions. 5. The semiconductor device according to claim 1, wherein the groove is formed on one of a front surface and a back surface of the semiconductor substrate in which the circuit is incorporated. 6. The semiconductor device according to claim 1, wherein the groove is formed by dicing or etching.