JP2007250664A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for easily improving performance of a transistor. <P>SOLUTION: The semiconductor device is provided with a semiconductor chip on which the transistor is formed, first mold resin for resin-sealing a surface-side of the semiconductor chip, and second mold resin for resin-sealing a rear-side of the semiconductor chip. A thermal expansion coefficient of first mold resin differs from that of second mold resin. The semiconductor chip is physically bent by a difference of contraction force when first and second mold resins are cooled. Distortion is introduced into a channel region of the semiconductor chip. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which strain is intentionally introduced into a channel region, and particularly to a semiconductor device capable of improving the performance of a transistor by physically bending a semiconductor chip on which a transistor is formed.

  A MISFET (Metal Insulator Semiconductor Field Effect Transistor) is a semiconductor element in which a gate insulating film and a gate electrode are sequentially formed on a semiconductor substrate. In this MISFET, in order to suppress the short channel effect, a technique is used in which an extension connected to the source / drain is shallowly formed under the side wall of the gate electrode. This structure is known as an LDD (Lightly Doped Drain) structure.

  In addition, the semiconductor element is packaged with a resin or the like in order to block outside air and prevent failure and deterioration. In order to cope with the high speed, a multi-chip module (MCM) in which a plurality of semiconductor devices are mounted on one substrate is also manufactured. Conventional semiconductor packages have been devised so that the packages do not warp during molding in order not to affect the semiconductor elements.

  In recent years, there has been a rapid demand for higher integration of semiconductor integrated circuits in order to increase the functionality of mobile devices and reduce costs. I'm following. When the gate length is reduced, the most serious problems are threshold variation due to the short channel effect and an increase in subthreshold leakage current. In order to suppress this short channel effect, the impurity concentration of the channel region is increased and the source / drain extension region is formed shallowly. However, by increasing the impurity concentration in the channel region, carrier mobility is reduced due to impurity scattering, and as a result, the current driving capability of the transistor is reduced. Also, forming the source / drain extension region shallowly increases the parasitic resistance and reduces the current driving capability. As described above, there is a problem in that the current driving capability is reduced as the gate length is reduced.

  In order to solve this problem, a fine MOS transistor in which distortion is intentionally introduced in the channel region has been proposed in order to improve carrier mobility. Conventionally, however, distortion has been introduced in the wafer manufacturing stage or in the wafer process during the formation of transistors. As an example, a strained Si substrate in which a biaxial tensile strain is applied to the outermost Si by epitaxially growing a SiGe film having a lattice spacing larger than Si on the Si substrate and then epitaxially growing the Si film. There is a technique for improving the current drive capability of both the N-type MOS transistor and the P-type MOS transistor by using it (see, for example, Non-Patent Documents 1 and 2).

  As another example, a high tensile stress SiN is formed on the gate of the N-type MOS transistor to apply a uniaxial tensile strain in the channel length direction. There is a technique of improving both current drive capacities by applying uniaxial compressive strain in the channel length direction by using SiGe as a drain (see, for example, Non-Patent Document 3).

K. Rim et al., Sympo.on VLSI Tech., P59, 2001 K. Rim et al., Sympo.on VLSI Tech., P98, 2002 T. Ghani et al., Tech. Dig. Int. Electron Device Meet.p.978, 2003

  However, since semiconductor devices are increasingly miniaturized and the process is complicated and difficult to control, it is difficult to apply distortion at the transistor level in a fine process.

  Further, the method using a strained Si substrate has a problem that junction leakage current increases due to a penetration defect from the SiGe film to the surface. In addition, in order to maintain a large lattice spacing of the strained Si layer, the strained Si layer must be made extremely thin. In a normal MISFET high-temperature process, Ge diffusion from the underlying SiGe layer to the strained Si layer surface is difficult. It cannot be ignored. In addition, crystal defects are likely to be formed by hetero-epi growth of the SiGe film on the Si substrate. Therefore, it is difficult to ensure the reliability of the gate insulating film due to the diffusion of Ge to the surface of the strained Si upper layer and the arrival of the penetrating defect starting from the crystal defect.

  In addition, the method using SiGe as the source / drain also has a problem that a crystal defect is generated in Si and a leakage current increases, and a number of steps of the wafer process increases and becomes complicated.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device that can easily improve the performance of a transistor.

  A semiconductor device according to the present invention includes a semiconductor chip on which a transistor is formed, a first mold resin for resin-sealing the front side of the semiconductor chip, and a second mold resin for resin-sealing the back side of the semiconductor chip. The first mold resin and the second mold resin have different coefficients of thermal expansion, and the semiconductor chip is physically bent due to the difference in contraction force when the first and second mold resins cool down, Distortion is introduced into the channel region of the semiconductor chip. Other features of the present invention will become apparent below.

  According to the present invention, the performance of a transistor can be easily improved by physically bending the semiconductor chip on which the transistor is formed.

Embodiment 1 FIG.
1 is a top view showing a semiconductor device according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line AA 'in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line BB' in FIG. is there. As shown in the drawing, a semiconductor chip 11 in which transistors (N-type MOS transistor and P-type MOS transistor) are formed on a Si substrate is bonded to a lead frame 13 with a resin-based adhesive 12 such as an epoxy-based or silicon-based resin. Both are fixed and connected by an aluminum wire 14. The front surface (semiconductor element surface) side of the semiconductor chip 11 is resin-sealed with a first mold resin 15a, and the back surface side of the semiconductor chip 11 is resin-sealed with a second mold resin 15b. Here, the first and second mold resins 15a and 15b are made of a material having sufficient adhesion with Si. The aluminum wire 14 is not fixed to the mold resins 15a and 15b.

  Here, the first mold resin 15a contains a filler 16 made of silica which is an inorganic material having a smaller thermal expansion coefficient than the mold resin. On the other hand, the second mold resin 15 b does not contain the filler 16. Therefore, the thermal expansion coefficient of the entire first mold resin 15a including the filler 16 is smaller than that of the second mold resin 15b.

  Thus, when the first mold resin 15a and the second mold resin 15b have different coefficients of thermal expansion, when the semiconductor chip 11 is cooled to room temperature after molding, the semiconductor chip 11 has the first and second mold resins 15a, 15a, It is physically bent so that the surface side becomes convex due to the difference in contraction force of 15b. As a result, biaxial tensile strain is introduced into the channel region of the semiconductor chip 11.

  As a result, only the carrier mobility can be improved without changing other electrical characteristics. Therefore, the on-state current can be increased with little increase in the off-state current of the transistor, and the operation speed of the integrated circuit can be improved. Since tensile strain is introduced in both the channel direction and the channel width direction, the current drive capability of both the N-type MOS transistor and the P-type MOS transistor can be improved.

  In addition, since it is not necessary to use a special process and a conventional high-temperature process can be applied, the current driving capability can be improved at a low cost without impairing the reliability of the gate insulating film. In addition, problems such as diffusion of Ge and increase in leakage current can be avoided as compared with the case of using a strained Si substrate as in the prior art or the case of using SiGe for the source / drain. Further, since distortion is generated in the packaging process, it is not necessary to generate distortion at the transistor level, which continues to be miniaturized.

  In the present embodiment, the case where the molding resin is applied to the package has been described. However, the present invention is not limited to this. For example, the molding resin may be molded from ceramic. Also in this case, the same effect as described above can be obtained if the magnitude relationship between the thermal expansion coefficients of the molding materials on the front surface side and the back surface side is the same as described above.

Embodiment 2. FIG.
In the present embodiment, as shown in FIG. 4, the first and second mold resins 15a and 15b are formed in a circular shape. Other configurations are the same as those in the first embodiment. As a result, not only the same effect as in the first embodiment is obtained, but the entire package is uniformly warped, so that the stress applied to the channel region of the semiconductor chip is uniform over the entire surface of the semiconductor chip.

Embodiment 3 FIG.
In the present embodiment, as shown in FIG. 5, the first and second mold resins 15a and 15b are formed in a circular shape, and the semiconductor chip 11 is an octagon. Other configurations are the same as those in the first embodiment. As a result, not only the same effects as those of the first and second embodiments are obtained, but the entire package is more uniformly warped, so that the stress applied to the channel region of the semiconductor chip is more uniform over the entire surface of the semiconductor chip. It becomes.

Embodiment 4 FIG.
A manufacturing process of the semiconductor device according to the fourth embodiment of the present invention will be described below with reference to the drawings.

  First, as shown in FIG. 6, a semiconductor chip 11 having a transistor formed on a Si substrate is bonded and fixed to a lead frame 13 with an adhesive 12, and both are connected by an aluminum wire 14. The wafer for which the pre-process of this semiconductor process is completed is divided for each semiconductor chip. Next, the semiconductor chip 11 is sealed with a molding resin 15 to form a package 17. Here, a material having sufficient adhesion with Si is used as the mold resin 15. The aluminum wire 14 is not fixed to the mold resin 15. The lead frame 13 is shaped in consideration of future deformation.

  Next, as shown in FIG. 7, a highly shrinkable resin 18 is bonded to either the back side or the front side of the package 17. As the highly shrinkable resin 18, a material having a thermal expansion coefficient larger than that of the mold resin 15 and excellent in adhesion to the mold resin 15 after cooling is used. Specifically, the highly shrinkable resin 18 can be obtained by intentionally reducing substances that suppress shrinkage, such as alumina powder and ceramic, contained in the material of the normal mold resin 15.

  Then, as shown in FIG. 8, the entire package 17 is deformed into a convex shape by solidifying and shrinking the highly shrinkable resin 18. As a result, the semiconductor chip 11 can be physically bent to introduce strain into the channel region of the semiconductor chip 11.

  As described above, in this embodiment, after all the pre-processes of the semiconductor process are completed, the package 17 is physically bent by the contraction force when the high-shrinkage resin 18 is cooled, and distortion is introduced into the channel region. To do. As a result, only the carrier mobility can be improved without changing other electrical characteristics. Therefore, the on-state current can be increased with little increase in the off-state current of the transistor, and the operation speed of the integrated circuit can be improved.

  This effect can be obtained by making a slight change in the subsequent process of the semiconductor process. In addition, the above method does not involve abrupt deformation that causes physical shock to the semiconductor chip 11, and thus does not cause excessive damage to the semiconductor chip 11 and does not deteriorate reliability.

  Further, if the mold resin 15 is bent before it is completely solidified, only the mold resin 15 is deformed and the strain is not transmitted to the essential semiconductor chip 11. On the other hand, if the molded resin 15 solidified as described above is deformed, the distortion can be reliably transmitted to the semiconductor chip 11. However, as a premise, it is necessary to use a mold resin 15 having a strong adhesion with the semiconductor chip 11.

  In addition, since the thickness and the number of additions of the highly shrinkable resin 18 can be easily changed, the amount of distortion can be easily controlled as necessary. If a concave deformation is required, a highly shrinkable resin 18 may be added to the upper surface of the package 17.

  As shown in FIG. 9, biaxial convex deformation can be caused in the semiconductor chip 11 by adhering a highly shrinkable resin 18 to the entire lower surface of the package 17. Thereby, since biaxial tensile strain is introduced into the channel region of the semiconductor chip 11, the current drive capability of both the N-type MOS transistor and the P-type MOS transistor can be improved.

  On the other hand, as shown in FIG. 10, if the highly shrinkable resin 18 is arranged in a stripe shape in one direction on the lower surface of the package 17, a convex deformation close to uniaxiality can be caused in the semiconductor chip 11. Thus, if tensile strain is introduced in the channel width direction, the current driving capability of the P-type MOS transistor can be improved, and if tensile strain is introduced in the channel direction, the N-type MOS transistor can be improved. Current drive capability can be improved.

  In addition, the semiconductor chip 11 is usually rectangular, and this causes no problem when uniaxial deformation occurs. However, in the case of biaxial deformation, it is desirable to mold the mold resin 15 into a circle and to make the semiconductor chip 11 into an octagon in consideration of symmetry. Further, if necessary, a larger strain can be introduced by repeating the adhesion and curing of the highly shrinkable resin 18.

Embodiment 5 FIG.
FIG. 11 is a top view showing a semiconductor device according to the fifth embodiment of the present invention, and FIG. 12 is a sectional view thereof. A linear filler 21 having a thermal expansion coefficient smaller than that of the mold resin 15 is embedded in the mold resin 15 only in one of the upper side and the lower side from the center of the package 17.

  When the filler 21 is attached to the upper side of the package 17, when cooled, the package 17 curves upward along the direction of the linear filler 21, and uniaxial strain is introduced into the channel region of the semiconductor chip 11. The Further, by setting the end of the semiconductor chip 11 to a free end without fixing, pure uniaxial strain is introduced into the channel region of the semiconductor chip 11.

  Here, when the surface of the semiconductor chip 11 is directed upward, uniaxial tensile strain is introduced into the channel region. Thus, if tensile strain is introduced in the channel width direction, the current driving capability of the P-type MOS transistor can be improved, and if tensile strain is introduced in the channel direction, the N-type MOS transistor can be improved. Current drive capability can be improved. On the other hand, when the surface of the semiconductor chip 11 is faced down, uniaxial compressive strain is applied to the channel region, so that it is possible to improve the current drive capability of the opposite conductivity type MOS transistors.

Embodiment 6 FIG.
FIG. 13 is a top view showing a semiconductor device according to the sixth embodiment of the present invention, and FIG. 14 is a sectional view thereof. A flat plate member 22 having a higher coefficient of thermal expansion than the mold resin 15 is provided in the mold resin 15 below the center of the package 17.

  When cooled, the package 17 curves upward and biaxial tensile strain is introduced into the channel region of the semiconductor chip 11 to improve the current drive capability of both the N-type MOS transistor and the P-type MOS transistor. Can do. In addition, pure biaxial distortion is introduced into the channel region of the semiconductor chip 11 by fixing the end of the semiconductor chip 11 to a free end.

Embodiment 7 FIG.
FIG. 15 is a top view showing a semiconductor device according to Embodiment 7 of the present invention, and FIG. 16 is a cross-sectional view thereof. A rod-shaped member 23 having a higher coefficient of thermal expansion than the mold resin 15 is provided in one direction in the mold resin 15 and below the center of the package 17.

  When cooled, the package 17 is convexly curved in the lateral direction of FIG. 15, and uniaxial tensile strain is introduced into the channel region of the semiconductor chip 11. Thus, if tensile strain is introduced in the channel width direction, the current driving capability of the P-type MOS transistor can be improved, and if tensile strain is introduced in the channel direction, the N-type MOS transistor can be improved. Current drive capability can be improved. On the other hand, when the surface of the semiconductor chip 11 is faced down, uniaxial compressive strain is applied to the channel region, so that it is possible to improve the current drive capability of the opposite conductivity type MOS transistors. Further, by setting the end of the semiconductor chip 11 to a free end without fixing, pure uniaxial strain is introduced into the channel region of the semiconductor chip 11.

  Here, in the first to seventh embodiments, when the semiconductor chip 11 is shifted to the upper side or the lower side from the center of the package 17 during resin sealing, a larger strain can be introduced. This is because the strain applied to the semiconductor chip 11 is 0 at the center, and a greater tensile strain is applied to the upper side and a higher compressive strain is applied to the lower side.

Embodiment 8 FIG.
FIG. 17 is a top view showing a semiconductor device according to the eighth embodiment of the present invention, and FIG. 18 is a sectional view in a direction perpendicular to the rod-shaped member. In the mold resin 15, on the upper side and the lower side of the semiconductor chip 11, rod-shaped members 23 having a higher coefficient of thermal expansion than the mold resin 15 are arranged in a stripe shape in one direction.

  When cooled, the rod-shaped member 23 contracts in the lateral direction of FIG. A compressive strain is introduced into the channel region of the semiconductor chip 11 by the contraction force of the rod-like member 23. Thus, if compressive strain is introduced in the channel width direction, the current driving capability of the N-type MOS transistor can be improved, and if compressive strain is introduced in the channel direction, the P-type MOS transistor can be improved. Current drive capability can be improved. In addition, by fixing both lateral ends of the semiconductor chip 11 and free both longitudinal ends, pure uniaxial compressive strain is introduced into the channel region of the semiconductor chip 11.

Embodiment 9 FIG.
19 is a top view showing a semiconductor device according to the ninth embodiment of the present invention, FIG. 20 is a cross-sectional view taken along the line AA ′ of FIG. 19, and FIG. 21 is a cross-sectional view taken along the line BB ′ of FIG. is there. After the transistors are formed and the wiring process is performed, the diced semiconductor chip 11 is bonded to the curved surface of the support substrate 31 with an adhesive 32. Further, the support substrate 31 is bonded to the lead frame 33 with an adhesive 32. Here, as the adhesive 32, silicon, epoxy, Au-Si, solder, or the like is used. Further, as shown in FIG. 22, the support substrate 31 has a biaxial convex curved surface, and the material of the support substrate 31 fixes the semiconductor chip 11 and heat treatment for bonding and curing the adhesive. Any material may be used as long as it does not deform when heat-curing during wire bonding and mold resin heat-curing in the molding process, such as ceramic.

  As a result, the semiconductor chip 11 is physically bent along the curved surface of the support substrate 31, and biaxial tensile strain is introduced into the channel region of the semiconductor chip 11. Accordingly, since tensile strain is introduced in both the channel direction and the channel width direction, the current drive capability of both the N-type MOS transistor and the P-type MOS transistor can be improved.

  In addition, by making the curved surface of the support substrate 31 equal at all points, the strain introduced into each transistor in the semiconductor chip 11 becomes equal, and in-plane variation in current drive capability can be prevented. Also in the laminated chip, as shown in FIG. 23, two semiconductor chips 11 are respectively bonded to the curved surface of the support substrate 31 with an adhesive 32, whereby a biaxial tensile strain is applied to the two semiconductor chips 11 together. can do. 24, only the upper semiconductor chip 11 is bonded to the curved surface of the support substrate 31, or only the lower semiconductor chip 11 is bonded to the curved surface of the support substrate 31, as shown in FIG. You can also.

Embodiment 10 FIG.
26 and 27 are cross-sectional views showing the semiconductor device according to the tenth embodiment of the present invention. FIG. 26 corresponds to the cross-sectional view taken along the line AA ′ of FIG. 19, and FIG. This corresponds to the cross-sectional view at ′. In the present embodiment, the support substrate 31 has a uniaxial convex curved surface as shown in FIG. Other configurations are the same as those of the ninth embodiment.

  As a result, the semiconductor chip 11 is physically bent along the curved surface of the support substrate 31, and uniaxial tensile strain is introduced into the channel region of the semiconductor chip 11. Therefore, if tensile strain is introduced in the channel width direction, the current driving capability of the P-type MOS transistor can be improved, and if tensile strain is introduced in the channel direction, the current of the N-type MOS transistor can be improved. Driving ability can be improved.

  In addition, by making the curved surface of the support substrate 31 equal at all points, the strain introduced into each transistor in the semiconductor chip 11 becomes equal, and in-plane variation in current drive capability can be prevented. The present embodiment can be applied to a laminated chip as in the ninth embodiment.

Embodiment 11 FIG.
29 and 30 are cross-sectional views showing the semiconductor device according to the eleventh embodiment of the present invention. FIG. 29 corresponds to the cross-sectional view taken along the line AA 'in FIG. 19, and FIG. This corresponds to the cross-sectional view at ′. In the present embodiment, the support substrate 31 has a uniaxial concave curved surface as shown in FIG. Other configurations are the same as those of the ninth embodiment.

  As a result, the semiconductor chip 11 is physically bent along the curved surface of the support substrate 31, and uniaxial compressive strain is introduced into the channel region of the semiconductor chip 11. Therefore, if compressive strain is introduced in the channel width direction, the current driving capability of the N-type MOS transistor can be improved, and if compressive strain is introduced in the channel direction, the current of the P-type MOS transistor is improved. Driving ability can be improved.

  In addition, by making the curved surface of the support substrate 31 equal at all points, the strain introduced into each transistor in the semiconductor chip 11 becomes equal, and in-plane variation in current drive capability can be prevented. The present embodiment can be applied to a laminated chip as in the ninth embodiment.

Embodiment 12 FIG.
A manufacturing process of the semiconductor device according to the twelfth embodiment of the present invention will be described below with reference to the drawings.

  First, as shown in FIG. 32, the semiconductor chip 11 on which the transistor is formed after the previous process is bonded to a TAB (Tape Automated Bonding) tape 42 with an adhesive 41. Next, the semiconductor chip 11 is electrically connected to the copper wiring 43 via the aluminum wire 14. Then, the TAB tape 42 is bonded to the plastic support substrate 44. Furthermore, by bending the support substrate 44 into a convex shape with a physical force, the semiconductor chip 11 is physically bent to introduce strain into the channel region of the semiconductor chip 11.

  As a method of bending the support substrate 44, a method of attaching the highly shrinkable resin 18 to the back surface of the support substrate 44 can be used as in the fourth embodiment. Thereafter, as shown in FIG. 33, the semiconductor chip 11 and the copper wiring 43 are resin-sealed with the mold resin 15.

  As described above, after all the previous steps of the semiconductor process are completed, the semiconductor chip 11 is physically bent together with the support substrate 44 to introduce strain in the channel region, thereby obtaining the same effect as in the first embodiment. Further, by changing the bending method of the support substrate 44, the type and amount of strain applied to the semiconductor chip 11 can be easily adjusted. For example, a concave deformation can be added, and a uniaxial strain or a biaxial strain can be selected.

  Further, since there is no force point for applying stress on the semiconductor chip 11, there is a low possibility that the semiconductor chip 11 is cracked due to deformation. Even if the strain amount of the semiconductor chip 11 is not directly measured, the strain amount of the semiconductor chip 11 can be found by measuring the strain of the mold resin 15 and the support substrate 44, so that the strain amount can be easily adjusted. The thicker the support substrate 44, the more efficiently the strain is introduced into the semiconductor chip 11 mounted on the surface.

Embodiment 13 FIG.
When an inverter circuit as shown in FIG. 34 is formed on a semiconductor chip, normally, as a semiconductor chip, as shown in FIG. 35, an N-type MOS transistor and a P-type MOS transistor are arranged so that the channel directions are parallel to each other. The formed one is used. As shown in the figure, the gate electrode 51, the source electrode 52, and the drain electrode 53 of both transistors extend in parallel.

  Here, when uniaxial tensile strain is introduced in the vertical direction of FIG. 35, the current increases in the N-type MOS transistor whose channel is directed in the strained direction, and the current decreases in the P-type MOS transistor. Therefore, when the current value of the N-type MOS transistor is lower than the assumed value and the current value of the P-type MOS transistor is higher than the assumed value and unbalanced, the introduction of this uniaxial tensile strain in the vertical direction It can be close to the expected value. In the reverse case, the unbalance can be adjusted in the same manner.

  However, when subjected to uniaxial tensile strain in the channel direction, the N-type MOS transistor has increased carrier mobility and improved performance, whereas the P-type MOS transistor has decreased performance. On the other hand, when subjected to uniaxial compressive strain in the channel direction, the performance of the N-type MOS transistor decreases and the performance of the P-type MOS transistor increases. For this reason, in the arrangement as shown in FIG. 35, if one attempts to improve the performance of either the N-type MOS transistor or the P-type MOS transistor, the other is lowered.

  Therefore, in the thirteenth embodiment, a semiconductor chip in which an N-type MOS transistor and a P-type MOS transistor are formed so that the channel directions are orthogonal to each other is used as shown in FIG. Thereby, only one side can improve performance by uniaxial distortion. In other words, if the performance of the P-type MOS transistor is insufficient, the performance of the P-type MOS transistor is improved without significantly degrading the performance of the N-type MOS transistor by introducing compressive strain in the channel direction of the P-type MOS transistor. can do. Similarly, only the performance of the N-type MOS transistor can be improved.

It is a top view which shows the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in AA 'of FIG. It is sectional drawing in BB 'of FIG. It is a top view which shows the semiconductor device which concerns on Embodiment 2 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 4 of this invention. It is a bottom view which shows an example of the semiconductor device which concerns on Embodiment 4 of this invention. It is a bottom view which shows the other example of the semiconductor device which concerns on Embodiment 4 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 5 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 6 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 7 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 7 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 8 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 8 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 9 of this invention. It is sectional drawing in AA 'of FIG. It is sectional drawing in BB 'of FIG. It is a perspective view which shows the support substrate which concerns on Embodiment 9 of this invention. It is sectional drawing which shows an example of the semiconductor device of the laminated chip which concerns on Embodiment 9 of this invention. It is sectional drawing which shows the other example of the semiconductor device of the multilayer chip concerning Embodiment 9 of this invention. It is sectional drawing which shows the further another example of the semiconductor device of the laminated chip concerning Embodiment 9 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 10 of this invention. It is a perspective view which shows the support substrate which concerns on Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 11 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 11 of this invention. It is a perspective view which shows the support substrate which concerns on Embodiment 11 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 12 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 12 of this invention. It is a circuit diagram which shows a CMOS inverter. FIG. 5 is a layout diagram of a normal transistor. It is a layout diagram of transistors according to the thirteenth embodiment of the present invention.

Explanation of symbols

11 Semiconductor chip 15, 15a, 15b Mold resin 17 Package 18 High shrinkable resin (member)
21 Filler
22 Flat members (members)
23 Bar-shaped member
31, 44 Support substrate

Claims (12)

A semiconductor chip on which a transistor is formed;
A first mold resin for resin-sealing the surface side of the semiconductor chip;
A second mold resin for resin-sealing the back side of the semiconductor chip;
The first mold resin and the second mold resin have different coefficients of thermal expansion, and the semiconductor chip is physically bent due to a difference in contraction force when the first and second mold resins are cooled. A semiconductor device, wherein a strain is introduced into a channel region of the semiconductor chip.   The semiconductor device according to claim 1, wherein one of the first mold resin and the second mold resin contains a filler, and the other does not contain the filler.   The semiconductor device according to claim 1, wherein the first and second molding resins are formed in a circular shape. A semiconductor chip on which a transistor is formed;
Mold resin for resin-sealing the semiconductor chip;
A member having a coefficient of thermal expansion different from that of the mold resin, which is provided only on the upper side or the lower side of the center of the package made of the semiconductor chip and the mold resin;
The semiconductor device is characterized in that the semiconductor chip is physically bent by a difference in contraction force when the mold resin and the member are cooled, and strain is introduced into a channel region of the semiconductor chip.   The semiconductor device according to claim 4, wherein the mold resin is formed in a circular shape.   The semiconductor device according to claim 1, wherein the semiconductor chip is an octagon.   The semiconductor device according to claim 1, wherein the semiconductor chip is shifted upward or downward from a center of the package. A semiconductor chip on which a transistor is formed;
Mold resin for resin-sealing the semiconductor chip;
A member having a coefficient of thermal expansion greater than that of the mold resin provided on the upper and lower sides of the semiconductor chip;
2. A semiconductor device, wherein compressive strain is introduced into a channel region of the semiconductor chip by a contraction force when the member cools.   The semiconductor device according to claim 4, wherein the members are arranged in a stripe shape in one direction. A semiconductor chip on which a transistor is formed;
A support substrate having a convex or concave curved surface, wherein the semiconductor chip is bonded to the curved surface,
The semiconductor device, wherein the semiconductor chip is physically bent along the curved surface, and strain is introduced into a channel region of the semiconductor chip. A semiconductor chip on which a transistor is formed;
A plastic support substrate to which the semiconductor chip is bonded;
A mold resin for resin-sealing the semiconductor chip,
The semiconductor device is characterized in that the semiconductor chip is physically bent together with the support substrate, and strain is introduced into a channel region of the semiconductor chip.   12. The semiconductor device according to claim 9, wherein an N-type MOS transistor and a P-type MOS transistor are formed on the semiconductor chip so that the channel directions are orthogonal to each other. .

Images