JPH10255471A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate time division of control to a semiconductor memory and to obtain a system simplified and making good use of operation performance of the semiconductor memory, by enabling read-operation and write- operation from a different system to be carried out asynchronously during read-operation of the semiconductor memory. SOLUTION: Read-operation and write-operation from a device such as a CPU and the like in a system are performed with non-asynchronism during read-operation. A memory cell storing data by a read/write address input circuit 2 is selected, a read/write control circuit 4 reads out data from a memory cell for a data input/output circuit 3 at the time of read-operation, and writes data in the memory cell at the time of write-operation. Also, a read-control circuit 7 reads out data from a memory cell selected by a read-address input circuit 5, and sends out it to a data output circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having an address input circuit and a data output circuit dedicated to a read operation.

[0002]

2. Description of the Related Art Normally, a semiconductor memory device such as an SRAM basically has only one set of address input circuits for read and write operations or one set of address input circuits dedicated to read and write operations. Therefore, if a read operation or a write operation from another system on the system is attempted during the read operation of the semiconductor memory device,
Since it is necessary to time-divide the control operations from the plurality of systems to the semiconductor memory device, a circuit for time-sharing is required, and the system becomes complicated and the scale is increased. It has been difficult to make the most of the operation speed of the semiconductor memory device.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to asynchronously perform read and write operations from another system on a system during a read operation of a semiconductor memory device, thereby controlling the control of the semiconductor memory device. An object of the present invention is to realize a system that does not require time division, simplifies the system, and utilizes the operation performance of a semiconductor memory device.

[0004]

The above object can be achieved by providing an address input circuit and a data output circuit dedicated to a read operation.

[0005]

According to the above construction of the present invention, by providing an address input circuit and a data output circuit for a read operation in a semiconductor memory device, reading and writing from another system in the system during a read operation of the semiconductor memory device. The operation can be performed asynchronously.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments with reference to the drawings.

FIG. 1 is a configuration diagram showing a semiconductor memory device. Reference numeral 1 denotes a memory cell constituting a semiconductor memory device. A memory cell for storing data is selected by the read / write address input circuit 2, and the read / write control circuit 4 reads data from the memory cell to the data input / output circuit 3 during a read operation, and reads data from the memory cell during a write operation. Is written to the memory cell.

The read control circuit 7 reads data from the memory cell selected by the read address input circuit 5 and sends the data to the data output circuit 6.

FIG. 2 is a block diagram showing a case where a semiconductor memory device is used in a control system of a display device as an embodiment of the present invention. In this display device control system, the display control circuit 11 periodically reads display data stored in the semiconductor memory device 12 and sends the data to the display device.
Also, an external CPU is required for the control system of the display device.
Reference numeral 13 denotes data read to the semiconductor memory device through the input / output buffer circuit 8, the input / output control circuit 9, and the data register 10 asynchronously regardless of the timing at which the display control circuit 11 reads data from the semiconductor memory device 12. And can be lighted. Therefore, in this semiconductor memory device, there is no need to provide a circuit for time-sharing another control from the two systems, so that the system can be simplified.

In addition, since the operation performance of the semiconductor memory device can be more efficiently utilized as compared with the conventional method of time-sharing the control of the memory device, data transmitted to the display device per time can be utilized. It also has the effect of increasing the amount.

It should be noted that the embodiment described here is merely an example, and it is needless to say that the embodiment can be applied to all systems that require a plurality of controls for the memory device.

[0012]

As described above, according to the present invention, the semiconductor memory device is provided with a dedicated address input circuit and a dedicated data output circuit for a read operation. Read and write operations can be performed asynchronously. Compared with the conventional semiconductor memory device, read operations from a plurality of systems can be performed simultaneously without time division, so that a system design utilizing the operation performance of the semiconductor memory device can be realized. Further, a circuit for time division is not required, and the system can be simplified, which is advantageous in terms of cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram when the present invention is used in a display device control system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell 2 ... Read / write address input circuit 3 ... Data input / output circuit 4 ... Read / write control circuit 5 ... Read address input circuit 6 ... Data output circuit 7 ..Read control circuit 8 ... I / O buffer circuit 9 ... I / O control circuit 10 ... Data register circuit 11 ... Display control circuit 12 ... Semiconductor memory device 13 ... CPU

Claims (1)

[Claims] In a semiconductor memory device, a read-only address circuit and a data output circuit for data are provided in addition to a conventional address input circuit for a data write operation and a conventional data read operation. A semiconductor memory device wherein a high-speed operation can be realized by being able to asynchronously receive a read operation and a write operation from another device on a system such as a CPU.