JPH10254723A - Duplex computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a duplex computer system which can continue a processing even against the abnormality of software. SOLUTION: The central processing unit 2B of a preliminary computer executes a processing delayed by one transaction on transaction output from an input buffer 5 through a buffer 10. When an abnormality detection mechanism 8 detects abnormality during the processing of the central processing unit 2A of an operation computer, the output of the central processing unit 2B is switched to actual output by a switch instruction to a switching mechanism 6 when the processing of the central processing unit 2B terminates. A processing procedure 4B identifying the occurrence of abnormality takes the avoiding means of an abnormality processing by switching a system to an abnormality avoiding processing mechanism 12 corresponding to the type of transaction and referring to a transaction pointer 11 at the time of abnormality so as to continue the processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual computer system in which a central processing unit, a main storage device and an auxiliary storage device are duplicated in order to ensure the reliability of data processing, and in particular, one of the computers becomes abnormal. The continuation of processing by the other computer when

[0002]

2. Description of the Related Art A central processing unit, a main storage unit and an auxiliary storage unit which constitute a computer system are not 100% reliable. May result in failure.

For example, in an auxiliary storage device using a magnetic material as a storage medium, if data is read immediately after writing,
Although it is necessary to be able to read the same value as at the time of writing, if the magnetic material at that portion peels off after writing, the written value cannot be read.

In order to avoid such a situation, as shown in FIG. 2, main storage devices 1A and 1B and central processing units 2A and 2B of two computers A and B constituting an A system and a B system, respectively. And the auxiliary storage devices 3A and 3B have exactly the same configuration, and both computers execute exactly the same processing in parallel. For example, even if the auxiliary storage device 3B of the computer B becomes inoperable due to the above-described factors, the device of the computer A Allows normal processing to be continued.

[0005]

The conventional dual computer system has sufficiently achieved the object in view of the problem to be solved.

However, with the improvement of the hardware manufacturing technology and the clock speed, a large amount of software can occupy the central processing unit at one time, and the computer can operate due to a software defect. Abnormal stoppage has also become important as a problem to be avoided, and the conventional parallel processing method cannot cope with this.

That is, in a duplex system in which the same software is simultaneously executed using the same hardware, even if no defect occurs in the hardware, software defects are encountered at the same time. Both computers at the same time end abnormally and lose the means to a normal result.

As shown in FIG. 3, when the central processing units 1B and 2B of the computers 1 and 2 try to execute the same instruction at the same time as shown in FIG. When it is no longer possible, both central processing units 1B,
2B is abnormally stopped at the same time, and the system goes down. This will be described in the following specific example.

FIG. 4 shows a specific example of FIG. 2 or FIG. A system central processing unit 2A and B system central processing unit 2B
Are the main storage devices 1A and 1B or the auxiliary storage device 3 respectively.
Processing procedure 4A and processing procedure 4B of A and 3B are executed, and the contents of processing procedure 4A and processing procedure 4B in this case are completely the same. The processes of the central processing unit 2A and the central processing unit 2B perform exactly the same processing until an abnormality appears in the central processing unit 2A or its processing procedure.

Central processing unit 2A and central processing unit 2B
Starts processing, and the transactions used in the processing are stored in the input buffer 5, and are taken out in the order of storage and given to the central processing units 2A and 2B.

While the central processing unit 2A is operating normally, the switching mechanism 6 connects the output generated by the central processing unit 2A to the output to the output device 7, which is the actual output. The newly generated transactions to be input to the input buffer 5 are also connected to those generated by the central processing unit 2A.

If the abnormality detection mechanism 8 detects an abnormality in the central processing unit 2A or the processing procedure 4A, the abnormality detection mechanism 8 gives a stop instruction to the central processing unit 2A and sends an instruction to the switching mechanism 6 Is switched from the one generated by the central processing unit 2A to the one generated by the central processing unit 2B. The input buffer 5 includes an input device 9.
The transaction generated from is also submitted.

The transaction referred to here is a combination of data used in one process and information for identifying the process, and corresponds to a processing unit called a task or a thread. Although the processing according to the processing procedure for one transaction involves the generation of an output or a new transaction, it is assumed that there is no operation to wait for a new input.

Therefore, in the event of an abnormality in the hardware such as the central processing units 2A and 2B, the switching mechanism 6 can switch to the other transaction and output by the abnormality detection of the abnormality detecting mechanism 8 and continue the normal processing. When an abnormality is detected, the other central processing unit that is processing with the same software also becomes abnormal at the same time, and cannot perform normal processing even if the transaction and output are switched.

An object of the present invention is to provide a redundant computer system capable of continuing processing even if software is abnormal.

[0016]

According to the present invention, there is provided a duplicated computer system having an operation computer and a standby computer for performing the same processing, wherein the standby computer has one or more transactions with respect to the processing of the operation computer. Providing means for executing processing with a delay and performing processing for avoiding an abnormality in execution of a transaction from when the abnormality occurrence signal of the driving computer is given, and when an abnormality occurs in the operation computer,
At the end of the transaction being processed by the spare computer, an abnormality occurrence signal is given to the spare computer and a transaction signal being processed by the operating computer when an abnormality occurs, and an actual output is output from the output of the operating computer to the standby computer. Characterized in that an abnormal-time switching means for switching to the output of (1) is provided.

With this configuration, the spare computer
This is to perform a process that is delayed by one transaction to the driving computer to avoid the transaction processing abnormality that occurred during the transaction processing in which the driving computer became abnormal. When the error is detected, the operation computer is stopped, the output of the standby computer is switched to the actual output, and the abnormality is avoided immediately before the transaction processing in which the abnormality occurs.

[0018]

FIG. 1 is a block diagram showing an embodiment of the present invention. The differences from FIG. 4 are a buffer 10, an abnormal transaction pointer 11, and an abnormality avoiding mechanism 12.
Is provided.

Central processing unit 2A and central processing unit 2B
Is in a state of waiting for the first transaction due to the initialization of the entire system. When the first transaction occurs due to a key input from the input device 9, for example, a keyboard, the first transaction occurs first in the processing procedure 4A of the central processing unit 2A.
And enters the input buffer 10 of the central processing unit 2B and waits for the processing of the central processing unit 2A to end.

At this time, the abnormal-state transaction pointer 11 indicating the storage position of the transaction generated in the processing when the abnormality has occurred in the central processing unit 2A is pointed to the first storage position in the input buffer 5 of the entire system. Set to. All transactions that occur during the processing of the central processing unit 2A enter the input buffer 5 of the entire system and wait for processing.

The processing for the first transaction by the central processing unit 2A ends after some transactions have been generated and some outputs have been performed. When the processing of the central processing unit 2A ends normally, the processing of the second transaction is started by the central processing unit 2A, and the processing for the first transaction is started by the central processing unit 2B according to the processing procedure 4B. The second transaction is stored in the input buffer 10.

At this time, the abnormal-time transaction pointer 11 points to the next position of the input buffer 5 storing the last transaction. The central processing unit 2A processes the second transaction in the same way as for the first transaction and ends. Similarly, the central processing unit 2B processes the first transaction and ends the processing.
Transactions generated by the central processing unit 2B are not recorded in the input buffer 5.

After confirming that the central processing unit 2A has completed the processing of the second transaction and that the central processing unit 2B has completed the processing of the first transaction, the central processing unit 2A executes the processing of the third transaction. Starting, the central processing unit 2B starts processing the second transaction. In the same manner, the processing is continued until the processing of all transactions is completed or an abnormality occurs in the A system.

The input buffer 5 and the input buffer 1
0, abnormal transaction pointer 11, processing procedure 4
B is assumed to be protected from the processing of A system.

Next, in FIG. 1, the abnormality detecting mechanism 8
It is assumed that the functions are realized by combining functions such as a memory protection function for detecting an access to an illegal address and a checkpoint confirmation using a watchdog timer.

Here, for example, when an abnormality caused by software occurs during the processing of the third transaction by the central processing unit 2A and the abnormality detecting mechanism 8 detects an abnormality of the A system, the abnormality detecting mechanism 8 firstly executes the central processing. Stop the device 2A,
Then, it waits for the end of the processing of the central processing unit 2B. When the processing of the central processing unit 2B is completed, the abnormality detection mechanism 8 switches the processing result of the central processing unit 2B so that the processing result is output to the output device 7 according to a switching instruction to the switching mechanism 6, and outputs an abnormality to the central processing unit 2B. An occurrence signal is given to indicate that an abnormality has occurred.

When the central processing unit 2B identifies the occurrence of an abnormality in the central processing unit 2A by the abnormality occurrence signal, the processing procedure 4B is switched to the abnormality avoiding processing procedure 12 corresponding to the third transaction type, and the abnormality avoiding processing is started. Move on to execution. The abnormality avoiding processing procedure 12 is, for example, a procedure given as a subroutine of the processing procedure 4B, and refers to the abnormal time transaction pointer 11 when operating in the central processing unit 2B, for example, to provide means for avoiding abnormal processing. Take.

The procedure for avoiding the abnormal processing includes, for example, restricting data processing in the third transaction processing,
By performing the fourth transaction processing without executing the processing, the processing can be continued.

The delay of the transaction processing of the spare computer is not limited to one transaction, but may be two or more transactions.

[0030]

As described above, according to the present invention, there is provided a spare system for executing transaction processing with delay.
If the operating system has failed in the preceding transaction processing, select the error avoidance procedure for the transaction in which the operating system has failed after the end of the subsequent transaction processing of the spare system. Since it is possible to continue the operation of the system when an abnormality occurs in the hardware of the system which must be constantly operated, the operation of the system can be continued even when an abnormality occurs in the control program.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of duplication of processing in the related art.

FIG. 3 is an explanatory diagram of an operation of the conventional system for a software defect.

FIG. 4 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 1A, 1B Main storage device 2A, 2B Central processing unit 3A, 3B Auxiliary storage device 4A, 4B Processing procedure 5 Input buffer 6 Switching mechanism 7 Output device 8 Abnormality detection mechanism 9 Input device 10 Buffer 11: Transaction pointer at abnormal time 12: Abnormality avoidance mechanism

Claims (2)

[Claims] 1. A duplicated computer system comprising an operation computer and a standby computer that perform the same processing, wherein an abnormality detection means for giving an error occurrence signal to the standby computer when an error occurs in the operation computer; When the abnormality detection unit detects an abnormality, the system includes an abnormality-time switching unit that switches the output of the system from the output of the operating computer to the output of the standby computer, and performs the processing of the standby computer with respect to the processing of the operating computer. A duplicated computer system characterized by being executed later than a transaction. 2. The spare computer is provided with an abnormality avoiding means for performing a process for avoiding an abnormality on a transaction executed by the operating computer when an abnormality occurs. Item 2. A duplicated computer system according to Item 1.