JPH10253738A - Gps receiving system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a GPS receiving system in which the system configuration can be simplified by setting an identical integration completing timing every time for all tracking satellites. SOLUTION: The value of a cyclic code is counted back by a hardware or a software for the code phase 0 starting integration from a tracking code phase Pn. Despread integration is started from the code phase 0 at each time and finished at a code phase Pe before receiving the integration results. A decision is made whether the 1/0 bit transition point is present by monitoring the value of tracking code phase and the change of sign and absolute value of short time integration. At the same time, a decision is made whether it is a correct value thus avoiding control with an erroneous integrated value. Since despread processing can be completed at a same time, a system load can be examined easily and system configuration can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a GPS (Glob).
The present invention relates to a GPS receiving method for accurately receiving and tracking a radio wave from a satellite in a receiver of an al Positioning System and performing a positioning calculation to obtain an accurate current position.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a conventional GPS receiver.
FIG. 10 is a diagram showing an example of implementation of despread integration in the GPS receiver. In FIG. 9, a GPS receiving apparatus includes an amplifier 2 for amplifying a GPS satellite signal received by an antenna 1, a despreading circuit 3 for despread spectrum, and a code control circuit for controlling a code phase and a carrier frequency to be synchronized at that time. 4 and carrier control circuit 5
And an integrator 6 that integrates the signal obtained by the despreading, and a CPU 7 that determines whether the synchronization of the signal is correct based on the integrated signal, and feeds back control to the control circuit to correct the deviation. It is configured.

The shift to be corrected is a code phase and a carrier frequency.
It is detected using the I and Q components. Early and Late are the respective spectrum despread integral values obtained when the code phase is shifted by -1/2 and +1/2 chips with respect to the currently tracked phase, respectively. The smaller the shift of the code phase, the smaller the difference between them. The I and Q components of the signal are the sine component of the integrated value and c, respectively.
os component, and the smaller the carrier frequency shift
The component becomes smaller. Control for reducing the shift in carrier frequency is referred to as carrier tracking, and control for reducing the shift in code phase is referred to as code tracking.

[0004] Despreading is performed as follows. A satellite always has an atomic clock synchronized between satellites at an accurate time, and a signal is transmitted by superimposing a unique cyclic code for each satellite on transmission data at a period of 1 msec in synchronization with the clock.
As a result, the signal can be spread over a frequency band wider than the frequency of the transmission radio wave, which is called spectrum spreading, and is excellent in confidentiality and noise performance. Therefore, exactly 1
The cyclic code sequence is started in the msec cycle,
The receiving device restores the signal by multiplying the same cyclic code sequence in synchronization with the radio wave from the satellite, and this is called spectrum despreading. If the satellite and the receiver are both stationary, the cyclic code generation interval is constant. However, as the GPS satellite orbits about 20,000 km above the ground, Doppler is generated.
In the S receiving apparatus, the start timing of the cyclic code superimposed on the signal of the received radio wave is shifted. Therefore, following this shift, the start time of the cyclic code generated by the GPS receiver, that is, the code phase is also shifted.

[0005] FIG. 10 shows a conventional despreading integration operation, and the uppermost stage shows the passage of time. The middle stage shows the progress of the occurrence of the cyclic code in the despreading, and the bottom stage shows the despreading integration period and the integration value received by the software. Times 1, 2 and 3 are 1
It is an msec interval, and the time shorter than 1 msec is represented by a code phase, and is divided into 1024 chips from 0 to 1024 chips. Assuming that the code phase of the satellite is p1 at time 1, the code phase changes to p2 at time 2 and p3 at time 3 due to Doppler of the satellite. p1, p2, and p3 change little by little. The direction and speed of this change is proportional to the direction and magnitude of the satellite Doppler.

The change in the code phase means that the signal transmitted from the satellite at the code phase 0 at the time 1 is received at the code phase p1 at the time 1 and the code phase 0 at the time 2 is received.
Is received at the code phase p2 at time 2. Therefore, in order to revive a signal by despreading, it is necessary to generate a cyclic code from the code phase p1 at time 1 and multiply it by the received signal. That is, the generation of the cyclic code is started at the timing of the code phase p1 at the time 1, and the integration is performed until immediately before the code phase p2 at the time 2, to obtain the despread integral value 1. continue,
The generation of the cyclic code is started at the timing of the code phase p2 at the time 2, and the integration is performed until immediately before the code phase p3 at the time 3, to obtain the despread integral value 2. That is, the generation timing of the cyclic code gradually changes from p1 to p2 to p3. However, the value C0 at the start of the occurrence of the cyclic code is the same every time, and the sequence of the cyclic code is also the same.

[0007]

In this GPS receiver, in order to obtain a despread integral value, which is control information for carrier tracking and code tracking, the cyclic code of a cyclic code is tracked following a Doppler shift of a signal from a satellite. The occurrence time has been shifted. Therefore, the integration start time shifts with the Doppler of the satellite radio wave, and since the Doppler differs for each satellite, the integration start time also differs for each tracking channel. As a result, the integration completion time also changes as the time elapses, and differs for each channel, requiring complicated processing in the system configuration.

The present invention solves the above-mentioned problem, and provides a GPS reception system which simplifies the system configuration by making the integration completion time constant by inversely calculating the value of the cyclic code at the time of starting the integration from the tracking phase. The purpose is to:

[0009]

According to the first aspect of the present invention, there is provided a communication system comprising:
In order to simplify the system by making the timing to start the spectrum despread integration of the signal from the S satellite the same for all channels, the value of the cyclic code at the start of the integration is calculated by hardware using the value of the tracking code phase. Ask for it.

According to a second aspect of the present invention, the process of calculating the value of the cyclic code when starting the integration is performed by software.

According to a third aspect of the present invention, the integrated value and the reliability of the code are changed according to the value of the code phase, whereby 1
Avoid mistakenly using the integral value when / 0 includes a changing bit break.

According to a fourth aspect of the present invention, a portion where the sign of signal data, that is, 1/0 of a bit is unknown due to low reliability is estimated by estimating the sign from the manner of change of the sign of the signal before and after. , Ie, a sign change point of the signal is detected.

According to a fifth aspect of the present invention, a change in the absolute value of the 1 msec integrated value and a change in the sign of the 1 msec integrated value are observed for a short period of time in order to prevent a period in which the integrated value cannot be used for control for a long time due to low reliability. By doing so, the 1 msec integrated value including the 1/0 change of the bit is detected, and this alone is not used for control.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention described in claim 1 is a GPS
While entering the tracking state of the satellite signal, the integration start timing is the same while following the change in the code phase. Instead of changing the cyclic code generation start timing in accordance with the changing code phase, the cyclic code generation timing is the same every time, but the cyclic code value at the start of the generation is changed. The hardware calculates the value at the start of generation of the cyclic code from the code phase value. In other words, the code phase changes due to the Doppler change, but the interval between the previous integration start time and the current integration start time is always a fixed time interval, and the integration start timing and integration end timing become constant. The system configuration can be simplified.

According to a second aspect of the present invention, the processing for inverting the value at the start of the generation of the cyclic code from the code phase according to the first aspect is performed by software, and the integration start timing and the integration end The timing is constant and the system configuration can be simplified.

According to the third aspect of the present invention, in order to make the integration start timing the same every time, a bit break of a signal superimposed on a cyclic code may be included during an integration period. When the value of / 0 changes, the sign of the correlation value changes, so that the integral value becomes smaller than the actual value. Therefore,
Such a case where the value becomes smaller than the actual value is estimated from the tracking phase value, and the reliability of the integrated value is changed. Can be avoided for tracking.

According to a fourth aspect of the present invention, the sign can be estimated even when the reliability of the signal value is reduced by observing the changes in the absolute value of the integral value and the sign for a short time. That is, even if the sign of the signal becomes unknown by lowering the reliability of the integrated value, a break between bits can be detected from a change in the sign of the integrated value every time.

According to a fifth aspect of the present invention, a 1 msec integrated value including a 1/0 bit change is detected by observing a change in the absolute value and the sign of the integrated value for a short time, and only this is used. Even when the state of low reliability of the integrated value continues because the Doppler change is gradual, only the wrong one can be excluded from the control target and the uncontrolled period can be minimized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a GPS receiver according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the flow of the satellite signal tracking process, and FIG. 3 is a diagram showing an example of the despreading integration. 4 is a diagram showing an example of a method for obtaining a start value of the cyclic code, and FIG.
FIG. 6 is a diagram showing an integration result when a 0 change is included, FIG. 6 is a diagram showing a possible range of the same tracking code phase, and a relationship between the phase and the reliability of the integration result, and FIG. 7 is a 1/0 change of the same bit. FIG. 8 shows an example of a method for detecting
It is a figure which shows the difference of the presence or absence of a change.

FIG. 1 shows a signal flow and a control block diagram of the GPS receiving apparatus.
Radio waves from the satellite are amplified by an amplifier 2 and input to a despreading circuit 3 that performs spectrum despreading. The despread signal is integrated for a certain period of time and output as an I component and a Q component. The carrier frequency and the code phase which need to be synchronized in the satellite signal tracking change according to the movement of the satellite and the GPS receiver itself and the original vibration change of the oscillator due to the temperature drift, so that it is necessary to follow them. For this purpose, the CPU 7 calculates the deviation amount of the carrier frequency from the I component and the Q component obtained as a result of the despreading, and performs feedback control to the carrier control circuit 5 of the despreading block. Also, the CPU 7 is required to follow the code phase.
Is the despread integral value Earl before and after the tracking code phase
A code phase shift is calculated based on y and Late, and feedback control is performed to the code control circuit 4 of the despreading block.

The algorithm of the tracking control processing of the change in the frequency and code phase of the satellite signal is as follows. Values I and Q components obtained by integrating the despread signal for a predetermined time are taken out of the integrator and averaged. The equation for averaging is shown in (Equation 1). The shift of the carrier frequency is calculated based on the signal value obtained by averaging. The calculation formula is described in (Equation 2). I component is sin component of signal, Q component is cos
Since the component is a component, the unit of the value obtained by (Equation 2) is an angle (radian). Therefore, the angle ΔΦ → frequency Δf conversion is performed. The conversion equation is shown in (Equation 3).

[0022]

(Equation 1)

[0023]

(Equation 2)

[0024]

(Equation 3)

The obtained carrier frequency deviation is fed back to the carrier control circuit 5 in FIG. 1 to perform a process for following the frequency transition. Code tracking is performed at a constant period as control to follow a change in code phase. If the implementation timing, Ear obtained
A code phase shift is calculated based on the signal values of ly and Late. At this time, the influence of noise is reduced by performing past averaging processing. The equation for calculating the shift amount is shown in (Equation 4). Feedback is applied to the code control circuit 4 of FIG. 1 so as to correct the calculated code phase shift amount. At that time, in order to reduce the influence of noise, all the correction amounts obtained by one calculation are not fed back, but a fixed ratio thereof is fed back once.

[0026]

(Equation 4)

FIG. 2 shows a schematic algorithm of a conventional process in which despreading is performed and integration is performed for a predetermined time in order to obtain an integrated value serving as a tracking material. When the software specifies the code phase following the change in the satellite signal to the despreading circuit 3, the hardware waits until the specified code phase timing to start the cyclic code. In other words, the generated cyclic code starts from the same value each time and continues in the same arrangement. Integrator 6 until just before the cyclic code makes one turn
Performs integration, and upon completion, the software takes out the integrated value, performs tracking based on this value, obtains a code phase for starting the next integration, and sets it in the despreading circuit 3. The despreading circuit 3 generates a cyclic code sequence at the designated time and code phase, restores the signal by despreading multiplied by the received signal, and integrates this for about 1 msec to obtain a signal value. Note that the cyclic code sequence to be generated differs for each satellite, and in the case of different satellites, the correlation appears weakly.
It determines which satellite the signal is from.

FIG. 3 shows the despreading integration operation according to the present invention, and the top row shows the passage of time. The middle stage shows the progress of the occurrence of the cyclic code in the despreading, and the bottom stage shows the despreading integration period and the integration value received by the software. Description will be made on the assumption that the code phase changes due to the Doppler of the satellite as in FIG. Instead of changing the generation timing of the cyclic code according to the code phase change, the generation of the cyclic code is started at the timing of the code phase 0 at each time. However, if the same value is generated every time, the signal cannot be synchronized with the cyclic code superimposed on the satellite signal, so that no correlation appears and a correct signal value cannot be obtained. Therefore, the cyclic code values c1, c2 at the moment of the code phase 0 are set such that the cyclic code starts at the moment of the code phases p1, p2, p3.
It is necessary to determine c2 and c3.

The code phases p1, p with Doppler
2 and p3, the values c1, c2 and c3 of the cyclic code also change. Since the sequence of the cyclic code is different for each satellite and is unique, the code phases p1, p are determined to obtain the changing c1, c2, and c3.
2, p3 can be obtained by back calculation. Actually, the value of the cyclic code is c for the time of (1 msec-p1).
It can be obtained by proceeding from zero. As described above, since the cyclic code is generated at the timing of the code phase 0 at the times 1, 2, and 3 to perform the integration, the integration completion time is set to the times 2, 3,
4 until just before the code phase 0, and each integration period is constant. Since this is the same for all satellites, even when a plurality of satellites are tracked at the same time, the completion timing of the despreading integration of the signals of all the satellites is the same.

FIG. 4 shows a flow of a process of reversely calculating the value of the cyclic code generated at the timing of the code phase 0 from the value of the code phase being tracked. FIG. 4A shows the reverse calculation performed by hardware. In the case (b), the reverse operation is performed by software. In (a), the code phase Pn tracked by the software
And the next integration start time to the hardware, the hardware calculates the start value Cn of the cyclic code generated from the code phase Pn, and starts the generation of the cyclic code at the timing of the code phase 0 at the designated time. The integration operation is performed, and the software receives the integration value after the integration is completed. In (b), when the start value Cn of the cyclic code generated from the code phase Pn tracked by the software is calculated, and the next integration start time and the value of the cyclic code to start generating are given to the hardware, Performs the integration operation by starting the generation of the cyclic code at the timing of the code phase 0 at the designated time,
After the integration is completed, the software receives the integration value.

FIG. 5 shows the form of signal data transmitted on a radio wave from a satellite and the process in which the GPS receiver of the present invention restores the signal data by despreading the spread spectrum signal data. . Signal data is 50b
1 bit is 20 ms because it is transmitted at a transmission speed of ps
ec. Bits 1 and 0 are determined by the sign of the I component of the received signal. That is, if the sign of the signal of 20 msec is positive, it is 1; if it is negative, it is 0. In order to find the bits and the breaks of the bits, the sign of the despreading integral every 1 msec may be monitored to find a change point that changes from positive to negative or from negative to positive. However, in the present embodiment, the despreading integration period is the same every time, and the integration is not performed in synchronization with the head of the bit of the signal transmitted by the satellite. Therefore, a bit change point may exist during the integration period of 1 msec. This situation is shown in FIGS. In the case where no bit break is included, and in the case where the same bit continues such as 1 → 1 or 0 → 0, the sign is not inverted during 1 msec despreading integration, so that the integration value is correct. Is obtained. On the other hand, when the change point where 1/0 of the bit changes is included in the 1 msec despreading integration, the despread results with different codes are added, so that a value smaller than the actual value is obtained. This situation is shown at the bottom of FIG. The result of the despreading integration performed from the code phase 0 at time 1 to the code phase Pe at time 1 has a small value 6 because the sign of the despread result is inverted in the phase P1. On the other hand, from the code phase 0 at time 2 which does not include the change point of the code to the code phase Pe at time 2
The result of the inverse diffusion integration performed up to this point has a value of 7 since the sign inversion of the inverse diffusion result does not occur. Here, value 6 <value 7. Similarly, the result of the despreading integration performed from the code phase 0 at time 3 to the code phase Pe at time 3 does not include the sign inversion of the result of the despreading, so that the value 8 is larger than the value 6 and almost as large as the value 7. It is. As described above, 1 /
The absolute value of the result of the despreading integration including the timing at which the 0 change occurs during the integration period is smaller than the actual value, and using this value may cause a malfunction.

FIG. 6 shows that the absolute value of the result of the despreading integration including the timing at which the 1/0 change of the bit occurs during the despreading integration period is smaller than the actual value, and using this value causes a malfunction. This is an explanation of a means for solving the problem of being lost. In the present embodiment, the integration period is from phase 0 to phase Pe at each time. As shown at 9 in FIG. 6, the tracking code phase changes in the range from code phase 0 to code phase 1024, and it is at the position of this tracking code phase that a 1/0 change in bit occurs. For three typical locations within this range, each 1/0 of a bit
What happens to each integration result when a change occurs is shown in FIGS. 10, 11, and 12 in comparison with a value FULL when a 1/0 bit change does not occur. Note that bit 1
The / 0 change considers a change from positive to negative, that is, a change from 1 to 0.

In FIG. 6, reference numeral 10 denotes a case where the tracking code phase is a relatively small code phase. In the integration result obtained, the result of despreading after the code change becomes dominant, and no 1/0 bit change occurs. There is almost no difference compared to the value FULL in the case. In FIG. 6, reference numeral 11 denotes a case where the tracking code phase is an intermediate code phase between the maximum value and the minimum value. Since the sum of the despread results before and after the code change is almost the same, the obtained integration result is almost zero. This is very different from the value FULL when the 1/0 change of the bit does not occur.

The reference numeral 12 in FIG. 6 shows a case where the tracking code phase is a relatively large code phase. In the obtained integration result, the result of despreading before the code change is dominant, and no 1/0 bit change occurs. There is almost no difference compared to the value FULL in the case. From the above, 1 mse is determined by the value of the tracking code phase.
It is possible to determine whether the result of the inverse diffusion integration of c is almost correct or wrong. That is, as shown by 13 in FIG. 6, when the tracking code phase is small and large, the integration result is almost correct, and when the tracking code phase is an intermediate value, the integration result is considerably small and incorrect. It is possible to avoid a malfunction by discriminating a range that can be determined to be almost correct and a range that can be determined to be wrong by a tracking code phase and avoiding use of a wrong value. However, when the tracking code phase is an intermediate value, the degree of credibility is fixed, and the state in which tracking control cannot be performed at all is continued.

Also, like the absolute value of the integral value, the sign has low reliability, so that it is difficult to judge from the sign whether or not a 1/0 change of a bit has occurred. Therefore, it is assumed that the case where the sign change point is included within 1 msec is detected, and only this is invalidated.

FIG. 7 is a diagram showing a method for solving the difficulty of detecting the occurrence of the 1/0 change of the preceding bit. That is, it is a simplified flowchart of an algorithm for detecting whether or not a sign change point is included within 1 msec.

In general, by observing the sign change of a plurality of 1 msec integrated values in a short time to detect a 1/0 change of a bit, the 1/0 change point of the bit is despread by 1 msec. It is to detect the presence during the integration period. This is based on the following principle. The 1 msec integration including the sign change point has the characteristic that the value is small, and whether or not the value has reliability can be determined by the tracking code phase. In addition, at 1 msec before and after the change point of 1/0 of the bit, since the bit break is not included, the integrated value is not reduced, and the signs of the integrated values are different from each other. Therefore, even if the reliability is low from the value of the code phase, it can be determined that the 1/0 change of the bit has not occurred unless the sign of the preceding and following 1 msec integration is different. In this case, since the integral value is a correct value, it may be used for control.

In step 1 in FIG. 7, it is determined from the tracking code phase value and 13 in FIG. 6 whether or not the current result of the despreading integration has reliability. As a result, when it is determined that the credit is high, the code change point is detected from the state of the signal change in the past 20 msec in step 2 similar to the conventional GSP receiver. On the other hand, if it is determined that the credit is low, the current integration result cannot be used as it is, and it may be a change point of 1/0 of the bit. Therefore, 2ms
Compare the sign of the integration result before ec with 1m if it is different
It detects that a 1/0 bit change has occurred in the tracking code phase before sec. If the signs are the same, it is detected that a 1/0 bit change has not occurred.

FIG. 8 shows an example of a change in the 1 msec integrated value obtained when the reliability of the integrated value is low. If the tracking code phase is in a range where the reliability of the integrated value is low, the state will change continuously at a certain speed, which depends on the speed of the Doppler of the satellite. Since the change in the code phase is small during several tens of msec, the state in which the reliability of the integrated value is low continues for such a short time. This is shown in FIG. Although the 1-msec integrated value 21 at a certain point in time has low creditworthiness, the 1-msec integrated values 20 and 2 before and after the 1-msec integrated value
Since the signs of 2 are not different and the magnitudes of the integral values are almost the same, it can be determined that the 1/0 change of the bit has not occurred. On the other hand, 25 indicates that the sign of the integral 24 before 1 msec is positive, whereas the sign of the integral 26 after 1 msec is negative, and the absolute value of the integral is also 24.
Since 25 is considerably smaller than that of and 26, it can be determined that a 1/0 change in the bit has occurred. That is, while 21 is a correct value and can be used for tracking, 25 is a wrong value and is prohibited from being used for tracking.

As described above, by observing the state of the sign change of the 1 msec integral value and the state of the magnitude change of the absolute value for a short time, it is determined from the code phase whether or not the integrated value can be used for tracking even when the reliability of the integrated value is low. Thus, only the one including the bit break can be excluded from the tracking target, and it is possible to avoid a situation where the code phase value cannot be used for long-time tracking.

[0041]

According to the first and second aspects of the present invention, the integration start timing and the integration end timing are constant and the system configuration can be simplified.

According to the third aspect of the present invention, the use of a low-reliability item for tracking can be avoided by not using a low-reliability item.

According to the fourth aspect of the present invention, even if the sign of the signal becomes unknown by lowering the reliability of the integral value, a break between bits can be detected from a change in the sign of the integral value every time.

According to the fifth aspect of the present invention, even when a state in which the reliability of the integrated value is low because the Doppler change is gradual, only the wrong one is excluded from the control target to minimize the uncontrolled period. it can.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a GPS receiver according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a flow of a satellite signal tracking process according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of implementation of despreading integration in one embodiment of the present invention.

FIG. 4 is a diagram showing an example of a method for obtaining a start value of a cyclic code according to an embodiment of the present invention.

FIG. 5 is a diagram showing an integration result when a 1/0 change of a bit is included in despread integration according to one embodiment of the present invention;

FIG. 6 is a diagram showing a possible range of a tracking code phase and a relationship between the phase and the reliability of an integration result according to the embodiment of the present invention;

FIG. 7 shows 1/0 of a bit in one embodiment of the present invention.
Diagram showing an example of a method for detecting a change

FIG. 8 shows 1/0 of a bit in one embodiment of the present invention.
Diagram showing the difference of presence or absence of change

FIG. 9 is a configuration diagram of a conventional GPS receiver.

FIG. 10 is a diagram showing an example of implementation of despread integration in a conventional GPS receiver.

[Explanation of symbols]

 Reference Signs List 1 antenna 2 amplifier 3 despreading circuit 4 code control circuit 5 carrier control circuit 6 integrator 7 CPU

Claims (5)

[Claims] In order to simplify the system by making the timing of starting spectrum despread integration of a signal from a GPS satellite the same for all channels, the value of a cyclic code at the start of integration is determined by using the value of a tracking code phase. GPS receiving method characterized by calculating by hardware. 2. The GPS receiving system according to claim 1, wherein the process of calculating the value of the cyclic code at the time of starting the integration is performed by software. 3. The method according to claim 1, wherein the integral value and the reliability of the code are changed according to the value of the code phase, thereby avoiding erroneous use of the integral value in the case of including a bit break where 1/0 changes. The GPS receiving method according to claim 1, wherein 4. Where the sign of signal data, that is, 1/0 of a bit, is unknown due to low reliability, the sign of the bit is estimated by estimating the sign from the manner in which the sign of the preceding and following signals changes, thereby providing a break in the bit, that is, the signal. 4. The GPS receiving method according to claim 3, wherein a sign change point is detected. 5. In order to prevent a long period of time during which the integrated value cannot be used for control due to low reliability, a period of 1 msec.
1 ms including 1/0 bit change by observing a change in magnitude and a sign change of the absolute value of the integral value for a short time
4. The GPS receiving system according to claim 3, wherein an ec integral value is detected and not used alone for control.