JPH10253709A - Test head for semiconductor, method and system for testing semiconductor using the test head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test head for semiconductor, along with a method and a system for testing a semiconductor, in which the delay time of output signal from a semiconductor to be tested (DUT: device under test) is compensated for various hardwares of semiconductor tester being employed in each fabrication process. SOLUTION: A test head for semiconductor where an additional capacitor 61 is connected between a semiconductor switch 14 and an input part 20 through a relay 65 is employed in a semiconductor tester for test program developing process and correlation between the capacitance before/after switching a relay 65 and a signal delay time from a DUT is derived. Subsequently, the capacitance is measured for every semiconductor tester to other process and inputted to a conversion program along with the correlation thus generating a test program compensating for the signal delay time in each test process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a measuring apparatus, a measuring method and a measuring system using the same, and more particularly to a semiconductor test head and a semiconductor testing method and a semiconductor test system using the same.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor devices has been rapidly increasing, and the functions of integrated circuits have become more and more complicated as LSIs and VLSIs have changed to ULSIs. Therefore, quick and accurate examination of test methods has become important in each manufacturing process, especially at the stage of design development.

Here, a test process in the development stage of an LSI will be described with reference to the drawings.

FIG. 12 is a flow chart of a test process in a manufacturing process in an LSI development stage.

First, in the design stage, a design is made in consideration of a test, and a test program in each manufacturing process is created at this stage (S200).

[0006] Next, in a wafer probing test (S230) performed through a mask manufacturing (S210) and a wafer process (S220), a probe is mechanically brought into contact with a bonding pad of an LSI chip in a wafer state, and electrical characteristics are obtained. Is measured.

In the electrical characteristic test (S250) after the assembly process (S240), detailed data is collected from various aspects, organized and analyzed to evaluate the performance of the LSI.

Further, in the electrical characteristic test (S260) in the reliability evaluation test, the application of stress and the aging stability of various characteristics are evaluated.

[0009] Wafer probing test (S230),
LS to be tested in the electrical characteristic test (S250) after the assembly process and the electrical characteristic test (S260) in the reliability evaluation test
When a defect of I is found, its cause is analyzed (S
270), design / test program creation (S200),
It is immediately fed back to the mask manufacturing (S210) and the wafer process (S220), and when all the characteristic tests pass, the LSI development / design is completed (S30).
0).

As described above, various tests are required in the development of semiconductor devices, and test devices are developed and used for each process.

The center of the electrical characteristic test is a functional test. When a predetermined operating condition is given to the LSI, the function test is performed.
This is a test for confirming whether the function of the SI operates normally. The most difficult of these functional tests is the logic test of a logic LSI.

FIG. 13 is a block diagram showing an outline of a logic test method in a general-purpose LSI function test.

First, the logic pattern generation means 124 generates a test logic pattern and an expected value pattern which is a reference for pass / fail judgment. Next, the LSI under test 300 (hereinafter referred to as DU)
T: Device Under Test. ) Is input to the input terminal 290.

Further, the DU driven by the power supply 190
The pattern which the logic circuit of T300 outputs to the output terminal 310 according to the logic pattern is compared with the pattern comparing means 1
45 is compared with the expected value pattern supplied from the expected value pattern supply means 126, and the pass / fail determination means 400 makes a pass / fail judgment.

Although not shown in FIG.
A test signal is input to the input terminal 290 of T, an output signal corresponding thereto is received from the output terminal 310, the output signal is compared with a predetermined reference voltage, and the result is supplied to the pattern comparison means 145. This is the semiconductor test head. The input and output interfaces with the DUT are tester pins of the semiconductor test head. The number of tester pins is required for the number of DUT signal pins.

FIG. 14 is a circuit diagram of a conventional semiconductor test head 10. In recent semiconductor test heads, a test pattern input driver 11 and signal comparators 15 and 16 are provided to each tester pin 18 so that the output section 37 and the input section 20 can share the tester pin 18.
Is installed. In each of the following figures, FIG.
The same reference numerals are used for portions corresponding to.

In FIG. 14, a high-level signal comparator 15
Compares a high level signal among output signals from the DUT with a set value. The low-level signal comparator 16 outputs D
A low-level output signal from the UT is compared with a set value.

The semiconductor switch 12 is connection control means for electrically disconnecting the test pattern input driver 11 and the signal comparators 15 and 16 from the tester pin 18, respectively. When the test pattern signal is output, the semiconductor switch 12 is turned on. Further, when receiving an input signal from the DUT, the semiconductor switch 12 is turned off so that the signal flows to the signal comparators 15 and 16.

The backmatch resistor 13 is a resistor for adjusting the characteristic impedance of the semiconductor test head 10 when the test pattern input driver 11 outputs a test pattern signal so that the characteristic impedance matches the DUT.

The semiconductor switch 14 is connection control means for controlling the input / output of the semiconductor test head 10 itself.

FIG. 15 is a circuit diagram showing an example of a connection between the DUT 300 and a semiconductor test head of such a conventional semiconductor test system. FIG. 16 shows an equivalent circuit diagram of a portion from the output driver 32 of the DUT 300 to the signal comparator 36 of the semiconductor test head 10 in the circuit diagram shown in FIG.

In FIG. 15, a semiconductor test head 10 is shown.
Output unit 37 applies a logic pattern signal sent from a semiconductor test apparatus main body (not shown) to an input terminal of the DUT. The response signal is taken from the output terminal of the DUT via the pin cable 153 into the signal comparator 36 of the semiconductor test head 10 and compared with a predetermined reference voltage. The comparison result is sent to a pattern value comparator (not shown) of the semiconductor test apparatus main body, where it is compared with an expected value pattern, and the logic function of the DUT is evaluated.

[0023]

However, the above-described semiconductor test head based on the prior art and the semiconductor test system using the same have a problem that a delay time occurs in the output signal from the DUT. . Hereinafter, this problem will be described with reference to the drawings.

Most semiconductor devices as DUTs
The output resistance 33 of the output driver 32 of the DUT shown in FIG.
Is considerably larger than the resistance value of the transmission resistance of the tester pin (see FIG. 14) of the semiconductor test head 10,
It is difficult to match the T output resistance, the transmission resistance of the pin cable 153, and the input resistance of the semiconductor test head 10. Therefore, in obtaining the output signal from the DUT,
The input resistance of the semiconductor test head is considerably increased, and signals are directly received by the signal comparators 15 and 16. However, in this method, as shown in FIG. 16, the pin cable 153 acts as a cable capacitor 41 and the semiconductor test head 10 acts as a load capacitance as an input capacitor 42 when viewed from the DUT side. At the input to the signal comparator, the signal waveform becomes as shown in FIG. 17B, and FIG. 17A showing the response of the actual device.
, Signal delay times 57 and 58 occur. Further, since the output resistance of each output pin of the DUT is not necessarily designed to have the same resistance value, when the output resistance is further increased, the signal delay time is further increased as shown by 59 and 60 in FIG. Become. This problem is due to DU
This also occurs when a different comparison level is set for each T output pin.

The above problem can be solved to some extent by considering the same kind of hardware of the semiconductor test apparatus in advance when developing a test program.

However, the same test must be carried out for each semiconductor device in the test evaluation of the semiconductor, but as described above, it is used in the wafer probing test after the wafer process and the electrical characteristic test after the assembly process. And the load capacity seen from the DUT side also differs. For example, as compared with the test program development process apparatus shown in FIG. 18, in the wafer process apparatus shown in FIG. 19, a ring 75 and a needle card 76 are provided between the DUT board 74 and the DUT 300, and FIG. In the apparatus for the manufacturing test process shown, a socket board 77 is provided between a DUT board 74 and a DUT 300 by a socket board cable 78.
When viewed from the DUT side, the load capacity increases only in these portions.

Therefore, it is necessary to change the comparison timing for each test program of such various semiconductor test apparatuses to maintain the correlation, while the output resistance and the comparison level are different for each hardware. It is extremely difficult to adjust the timing, and the operation requires an enormous amount of time.

As described above, the conventional technique in which the delay time of the output signal from the DUT must be adjusted for each piece of hardware of the semiconductor test apparatus causes a delay in production line construction and an increase in product cost. There were drawbacks.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object the purpose of testing and evaluating a DU in a semiconductor device.
An object of the present invention is to provide a method of detecting a delay time of an output signal from T in advance and easily compensating for different hardware, a semiconductor test head for performing the method, and a semiconductor test system using the same.

[0030]

According to the present invention (claim 1), an output section for outputting a test pattern signal to a semiconductor device to be tested, and an input section from the semiconductor device under test in response to the test pattern signal. An input unit having a signal comparator for comparing a signal voltage with a reference voltage; a tester pin for transmitting and receiving signals to and from the semiconductor device under test; and a first connection control between the tester pin and the input unit. And a signal delay compensating means connected through the means for compensating a signal delay time caused by the semiconductor test apparatus.

The signal delay compensating means is preferably provided for each tester pin.

Further, it is preferable that the first connection control means is means for selectively controlling connection with a plurality of signal delay compensation means.

The signal delay compensating means may be a signal delay compensating means comprising a capacitor.

The first connection control means may be a connection control means comprising a semiconductor switch circuit.

Further, it is preferable that the tester pin is selectively connected to the output section and the input section via second connection control means.

According to the present invention (claim 7), a signal of the test pattern is input to the semiconductor device under test by using a test program including a test pattern for the semiconductor device under test and a determination reference pattern. In a semiconductor test method for determining the quality of a semiconductor device under test by comparing a signal output from the semiconductor device under test with the determination reference pattern, a capacitance measurement is performed for each tester pin for one semiconductor test device. Step 1, and selectively connecting a capacitor between a tester pin and an input unit of the semiconductor test apparatus, measuring output signal delay times before and after connection of the capacitor for each of the tester pins, Second to derive a correlation between capacity and signal delay time
And a third step of measuring the capacitance for each tester pin for another semiconductor test apparatus, and from the correlation obtained in the second step and the measurement value obtained in the third step, A fourth step of calculating a signal delay time for each tester pin for the other semiconductor test apparatus, and inputting the calculated value obtained in the fourth step and converting the test program to compensate for an output signal delay time A semiconductor test method comprising:

Further, according to the present invention (claim 8), a CPU for issuing various command signals to control the entire system.
A control unit having an input / output unit for operating the CPU and displaying information; an internal power supply unit; a test pattern signal and an expected value pattern in accordance with instructions from the CPU. A logic pattern generating means for generating a signal, a timing signal generating means for generating a clock pulse for determining a test timing in accordance with a command from the CPU, and a timing signal transmitted from the timing signal generating means. Format control means for performing waveform shaping of a test pattern signal and outputting the waveform to a semiconductor test head;
DA conversion means for converting a digital signal sent from the CPU into an analog signal, setting a reference voltage for an output signal and an input signal, and controlling an input driver and a signal comparator of the semiconductor test head; The test driver sends the test pattern signal to the semiconductor device under test by the input driver, compares the signal input from the semiconductor device under test with a reference voltage by the signal comparator, and compares the result with the pattern value. 7. The semiconductor test head according to claim 1, which is sent to comparison means, and a comparison analysis between a comparison result signal sent from the semiconductor test head and an expected value pattern signal sent from the logic pattern generation means. Pattern value comparing means for sending the analysis result to the fail analysis storage means, and a solution by the pattern value comparing means. The semiconductor test system that includes a measurement portion having said fail analyzing memory means for storing the results of the information is provided.

According to the present invention, the relationship between the load capacitance and the signal delay time is measured in advance for each output pin of the DUT, so that the signal delay time is calculated from the capacitance of the hardware of each test apparatus. Therefore, the start-up of the semiconductor test system in each semiconductor test process can be performed in advance in the test program development process. Thus, the lead time from product development to mass production can be reduced. Further, since the correlation between the test steps can be theoretically matched, the quality control of the device is also facilitated.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings.

First, the principle of the semiconductor test method according to the present invention will be described with reference to FIGS.

Generally, in order to predict the signal delay time with respect to the load capacitance, it is necessary to know the output resistance of the DUT.
However, as can be seen from the output signal characteristic diagrams of the DUT shown in FIGS. 6A and 6B, the output resistance of the DUT is not determined as a constant. On the other hand, it can be seen from the characteristic diagrams of FIGS. 7A and 7B that the relationship between the load capacitance and the output signal delay time has a substantially linear characteristic. The present invention utilizes this relationship.

As shown in FIG. 8, there is a semiconductor test apparatus for developing a test program of a capacitance A [pF] for a certain output pin of a certain DUT, and a signal delay time when using this is Ta [ns]. Is measured. Also,
It is assumed that the signal delay time is Tb [ns] when measured by another semiconductor test device having a capacitance B [pF]. Then, the signal delay time Tc when using the measuring device of the load capacitance C [pF] is as follows: Tc = (ba) * C / (BA) + a- (ba) * A / (B- A) It can be easily calculated by [ns] (1).

Therefore, by selectively connecting the additional load capacitance of the semiconductor test apparatus for test program development and measuring the signal delay time before and after the connection for each pin of the DUT, the above-mentioned (1) can be achieved. A correlation can be derived.

The capacitance of the hardware of the measuring device in the other steps can be easily measured by a known capacitance meter, for example, a low-current capacitance meter. With the measured value as a standard value, almost the same value can be used even when the type of DUT changes, and the signal delay time of the DUT output can be predicted from the correlation of (1) and can be easily compensated.

Next, an embodiment of a semiconductor test method according to the present invention based on the above-described principle will be described with reference to a flowchart of FIG. 4 and a characteristic diagram of FIG.

First, a test program for a development process is created, and a conversion program for converting the program into a program for another process is created (S100).

Next, the capacitance of the hardware of the semiconductor test apparatus in each of the other steps is measured for each tester pin of the semiconductor test head (S110), and is input to a conversion program (S120).

Next, the signal delay time with respect to the load capacitance for each output pin of the DUT is measured using the hardware of the semiconductor test apparatus used in the test program development process when connecting and disconnecting the additional load capacitance. Then, the value of each constant of the correlation of (1) is determined (S130).

For example, as shown in FIG.
It is assumed that there is a measuring device for developing a test program of pF (point A), and a signal delay time Ta when this is used for a certain pin of a certain DUT is measured as 50 ns (point a). When a total of 100 pF (point B) was measured by adding a load capacitance of 70 pF between the measurement device and the DUT, the signal delay time Tb was 60 ns (point b). Therefore, the relational expression of (1) is specified as follows. Tc
= (60-50) C / (100-30) + 50- (60
−50) * 30 / (100−30) = C / 7 + 50−3
0/7 [ns] (2) In this way, the signal delay time is measured for each DUT, and the correlation of (2) is obtained.

The correlation is input to the test program created in the development process to correct the signal delay time (S140). Thereafter, the program conversion is performed manually or automatically using a conversion program based on the data of the signal delay time to complete a test program for another process (S150).

As a result, in the example of FIG. 5, for the measuring device for test program development, a correction of 50 ns can be made. For example, the capacitance of the corresponding tester pin of the measuring device for the wafer process can be corrected. Is 70 pF, C = 70 pF in the correlation of (2), and the signal delay time Tc = 55.7 ns (point c). Therefore, correction for 55.7 ns is performed for the test program for the wafer process. It can be carried out.

Next, some embodiments of the semiconductor test head according to the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of a semiconductor test head according to the present invention. In FIG.
A test pattern input driver, an output unit including a semiconductor switch and a backmatch resistor, an input / output control unit, and an input unit including a high-level signal comparator and a low-level signal comparator are described with reference to FIGS. Since they are the same, the same portions are denoted by the same reference numerals and description thereof will be omitted.

As shown in FIG. 1, an additional capacitor connection relay 65 and an additional capacitor 61 are characteristic parts of the present invention. The additional capacitor 61 is connected to the connection 17 between the semiconductor switch 14 and the input section 20 by an additional capacitor. It is selectively connected via a connection relay 65. The additional capacitor 61 can be easily replaced, and its capacitance value can be set to a standard value based on experience from the variation in capacitance between the test devices. Additional capacitor connection relay 65
By opening and closing, the signal delay time can be measured for each output pin of the DUT before and after the connection of the additional capacitor 61, so that the relational expression (1) can be derived for each DUT.

FIG. 2 shows the first embodiment of the present invention shown in FIG. 1 more specifically, and is a circuit diagram of a device using a semiconductor switch 70 as an additional capacitor connection relay.

Since the semiconductor switch circuit is used as the connection relay, the size and weight of the semiconductor test head can be reduced.

FIG. 3 is a circuit diagram of a second embodiment of the semiconductor test head according to the present invention. Also in FIG. 3, the test pattern input driver 11, the output unit 37 including the semiconductor switch 12 and the backmatch resistor 13, the semiconductor switch 14, the input unit 20 including the high-level signal comparator 15 and the low-level signal comparator 16 include: And FIG. 14 for explaining the prior art.

The present embodiment is characterized in that two additional capacitors 61 and 62 are selectively connected to the input section 20 of the semiconductor test head via an additional capacitor connection relay 69. is there. Therefore, in the second embodiment, since the number of times of replacement of the capacitor is reduced as compared with the first embodiment in which only one capacitor is connected, the work efficiency is improved, and the correction / signal of the test program of each process is improved. The delay time can be compensated at an early stage, and the time required for the test is greatly reduced, so that the lead time from product development to mass production can be significantly reduced.

Next, an embodiment of a semiconductor test system according to the present invention will be described with reference to the drawings.

FIG. 9 is a block diagram showing the configuration of the first embodiment of the semiconductor test system according to the present invention.

The semiconductor test system shown in FIG.
It comprises a measuring unit 100 for measuring various characteristics of T and a control unit 200 for controlling the same.

The control unit 200 includes a CPU (Central Processing Unit) 210 such as a minicomputer, and a storage device 2 such as a magnetic disk device or a flexible disk device.
20, input / output devices 2 such as a keyboard and a line printer
30 and the like.

The measuring section 100 includes a logic pattern generator 12 for generating a test pattern signal according to a command from the CPU.
0, a timing generator 110 for generating a clock pulse for determining test timing, a timing generator 110
Format controller 130 and CPU 210 for shaping the waveform of the test pattern signal based on the pulse signal of
A digital-to-analog converter 170 that converts a digital signal sent from the DUT into an analog signal, outputs a test pattern signal to the DUT, and compares a signal input from the DUT with a reference voltage by a built-in signal comparator 150. ,
It comprises a pattern value comparator 140 for comparing and analyzing the signal of the comparison result with the expected value pattern signal, a fail analysis memory 160 for storing information of the analysis result, a programmable power supply 190 and the like.

The operational relationship between the components is as follows.

First, in response to a command from the CPU 210, the logic pattern generator 120 generates a pattern signal for a function test and sends it to the format controller 130. The logic pattern generator 120 drives a signal to the DUT and also outputs a signal as to whether or not to compare the signal from the DUT with an expected value for each pattern.

The timing generator 110 has a CPU
In accordance with the command of 210, a functional test cycle or a rising or falling timing pulse of a clock pulse is generated and sent to the format controller 130. Note that the timing edges include those for driving and those for comparison. The timing edges for driving include the semiconductor test head 1.
There is also one for switching input / output at 50 input / output shared tester pins.

Next, the format controller 130
Is used to shape a test pattern signal of logic “1” and logic “0” generated from the logic pattern generator 120 into a predetermined waveform mode by a timing pulse sent from the timing generator 110, and send it to the semiconductor test head 150. .

On the other hand, the DA converter 170
The digital signal transmitted from 0 is converted into an analog signal, and the level setting of the input pattern to the DUT 300 of the semiconductor test head 150 and the determination level of the output pattern from the DUT 300 are performed.

Next, the semiconductor test head 150 is
The format controller 1 is controlled by the test pattern input driver 151 whose level is set by the A converter 170.
The voltage level of the test pattern signal sent from the terminal 30 is determined and applied to the input pin of the DUT 300 via the tester pin (see FIG. 1).

Further, the semiconductor test head 150 has a D
A signal output from the UT 300 in accordance with the input test pattern signal is received via a tester pin (see FIG. 1), and is compared with the reference voltage set by the DA converter 170 by the signal comparators 155 and 156. Then, the comparison result is sent to the pattern value comparator 140. At this time, of the input signals from the DUT, a high level signal is input to the high level signal comparator 15.
5 and the low-level input signal is compared and determined by the low-level signal comparator 156.

Next, the pattern value comparator 140 compares the comparison result signal sent from the signal comparators 155 and 156 of the semiconductor test head 150 with the expected value, and sends the comparison result to the fail analysis memory 160. The expected value includes a logic “1”, a logic “0”, and a high impedance state. In addition, the information on the comparison result includes information on a test result of pass / fail of each pin, an address position of a test pattern in which a defect occurs, and the like.

The fail analysis memory 160 stores the information of the comparison result sent from the pattern value comparator 140. These pieces of information are extremely important for research and development and reliability evaluation, and are used for failure analysis of the DUT 300, debugging of functional test patterns, and the like.

The above operation is repeated for various logic patterns to determine the quality of the DUT.

Since the semiconductor test system shown in FIG. 9 employs the semiconductor test head according to the present invention shown in FIG. 1 as the semiconductor test head, the delay time of the output signal for each output pin of the DUT is measured by the tester pin. It can be easily calculated in advance every time, and the test program of the semiconductor test system in another semiconductor test process can be corrected to easily compensate for the signal delay time. As a result, the test time in each manufacturing process can be significantly reduced.

FIG. 10 is a block diagram showing the configuration of a second embodiment of the semiconductor test system according to the present invention, in which a current is applied to a DUT to measure a voltage or to apply a voltage. In a semiconductor test system provided with a DC test unit 180 which is a means for measuring current, the semiconductor test head according to the present invention shown in FIG. 1 is employed.

Therefore, also in the semiconductor test system shown in FIG. 10, the delay time of the output signal for each output pin of the DUT is calculated in advance for each tester pin, and the test program of the semiconductor test system in another semiconductor test process is corrected. Therefore, it is possible to easily compensate for the signal delay time. As a result, the test time in each manufacturing process can be significantly reduced.

FIG. 11 is a block diagram showing the configuration of the third embodiment of the semiconductor test system according to the present invention. As the semiconductor test head, the second embodiment of the semiconductor test head according to the present invention shown in FIG. 3 is employed. By using the present system, the delay time of the output signal for each output pin of the DUT can be calculated more quickly, and the correction of the test program and the correction of the signal delay time for other test processes are further facilitated. As a result, the test time in each manufacturing process can be further reduced, and the lead time from product development to mass production can be significantly reduced.

The embodiment of the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the gist thereof. For example, in the semiconductor test head according to the present invention, three or more capacitors may be selectively connected, and the additional capacitor connection relay may be appropriately changed to a MOS relay if the connection control means. can do.

[0079]

As described in detail above, the semiconductor test head according to the present invention, the semiconductor test method and the semiconductor test system using the same have the following effects.

That is, in the semiconductor test head according to the present invention (claim 1), the signal delay compensating means is selectively connected to the input section of the semiconductor test head via the connection relay, and therefore, for each DUT. The correlation between the capacitance and the signal delay time can be easily derived. For this reason, the signal delay time can be calculated in advance for each DUT for the hardware of each test apparatus, and the signal delay time can be quickly and easily compensated. Can be performed in advance in the test program development process. As a result, the lead time from product development to mass production can be shortened, and the manufacturing cost can be reduced.

In the semiconductor test head according to the present invention (claim 2), the signal delay compensating means is provided for each tester pin of the semiconductor test head.
The correlation between the capacitance and the signal delay time can be easily derived for each output pin of the UT. For this reason, the signal delay time can be calculated in advance for each output pin of each DUT for the hardware of each test apparatus, so that the signal delay time from the DUT can be compensated more quickly. is there.

Further, in the semiconductor test head according to the present invention (claim 3), a plurality of signal delay compensating means are selectively connected to the input section of the semiconductor test head via the connection means. The correlation between the capacitance and the signal delay time can be more efficiently derived for each output pin of the DUT. As a result, the signal delay time can be calculated earlier for each output pin of each DUT for the hardware of each test apparatus, so that the signal delay time from the DUT can be compensated more quickly. is there.

In the semiconductor test method according to the present invention (claim 7), a capacitor is selectively connected between the tester pin of the semiconductor test apparatus and the input section, and the output signal delay time before and after the connection is reduced. The signal delay time is calculated in advance for each DUT for the hardware of each test device based on the correlation between the measured capacitance and the output signal delay time for each tester pin, and the output signal delay time is calculated. Therefore, the start-up of the semiconductor test system in each semiconductor test process can be performed in advance in the test program development process. As a result, the efficiency of the test is greatly improved, and the lead time from product development to mass production can be shortened, and the production cost can be reduced.

The semiconductor test system according to the present invention (claim 8) uses the semiconductor test head according to the present invention (claims 1 to 6) and the semiconductor test method according to the present invention (claim 7). Therefore, a highly efficient semiconductor test can be performed quickly. For this reason, there is an effect that the lead time from product development to mass production can be shortened, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor test head according to the present invention.

FIG. 2 shows a first embodiment of the present invention shown in FIG.
FIG. 11 is a circuit diagram of a device using a semiconductor switch 70 as an additional capacitor connection relay.

FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor test head according to the present invention.

FIG. 4 is a flowchart for explaining a semiconductor test method according to the present invention.

FIG. 5 is a characteristic diagram showing a correlation between a signal delay time and a load capacity for explaining one embodiment of a semiconductor test method according to the present invention.

FIG. 6 is a characteristic diagram showing a relationship between an output current I0 and an output voltage V0 in an output signal of the DUT. That is, FIG.
6A is a characteristic diagram showing the relationship between the output current I0 and the output voltage V0 in the output signal of the N-channel DUT, and FIG. 6B is the characteristic diagram showing the output current I0 and the output voltage V0 in the output signal of the P-channel DUT. FIG. 4 is a characteristic diagram showing a relationship between

FIG. 7 is a characteristic diagram showing a relationship between a signal delay time and a load capacitance in an output signal of a DUT. That is, FIG.
FIG. 7B is a characteristic diagram showing the relationship between the signal delay time tPLH and the load capacitance CL in the output signal of the N-channel DUT. FIG. 7B shows the signal delay time tPHL and the load capacitance CL in the output signal of the P-channel DUT. FIG. 4 is a characteristic diagram showing the relationship of FIG.

FIG. 8 is a characteristic diagram illustrating a correlation between a signal delay time and a load capacity for explaining a principle of predicting a DUT output signal delay time according to the present invention.

FIG. 9 is a block diagram showing a first embodiment of the semiconductor test system according to the present invention.

FIG. 10 shows a second example of the semiconductor test system according to the present invention.
It is a block diagram showing an embodiment.

FIG. 11 shows a third example of the semiconductor test system according to the present invention.
It is a block diagram showing an embodiment.

FIG. 12 is a flowchart of a test process in a manufacturing process in an LSI development stage.

FIG. 13 is a block diagram illustrating an outline of a logic test method in a general-purpose LSI function test.

FIG. 14 is a circuit diagram showing an example of a conventional semiconductor test head.

FIG. 15 is a circuit diagram showing one connection example between a semiconductor test head and a DUT in a semiconductor test system according to a conventional technique.

16 is an equivalent circuit of a portion from a DUT output to a signal comparator of a semiconductor test head in the circuit diagram shown in FIG.

FIG. 17 is a waveform diagram showing a signal waveform of an output signal from the DUT. That is, FIG. 17A is a waveform diagram showing an actual signal waveform of an output signal from the DUT, and FIG.
FIG. 7 is a waveform diagram showing a signal waveform of an output signal from the DUT when signal delay times 57 and 58 occur. FIG. 17C is a waveform diagram showing a signal waveform of an output signal from the DUT when signal delay times 59 and 60 longer than those in FIGS. 17B and 57 are generated.

FIG. 18 is a perspective view showing a specific example of a connection relationship among a DUT 300, a DUT board 74, and a semiconductor test head 10 in a semiconductor test apparatus used in a test program development process.

FIG. 19 shows DUT 300, ring 76, needle card 75, and DU among semiconductor test devices used in the wafer process.
FIG. 3 is a perspective view showing one specific example of a connection relationship between a T board 74 and a semiconductor test head 10.

FIG. 20 is a perspective view showing a specific example of a connection relationship among a DUT 300, a socket board 77, a socket board cable 78, a DUT board 74, and a semiconductor test head 10 among semiconductor test apparatuses used in a product test process. .

[Explanation of symbols]

 10, 150, 250, 400 Semiconductor test head 11, 151 Test pattern input driver 12, 14, 70 Semiconductor switch 13 Backmatch resistor 15, 155 High level signal comparator 16, 156 Low level signal comparator 17 I / O relay 14 18 between tester pin 20 input section 32 output driver 33 output resistance 36 signal comparator 37 output section 41 cable capacitor 42 input capacitor 51 DUT output waveform at no load 52 DUT output waveform at low capacity load 53 DUT output waveform under high capacity load 55 High comparison level 56 Low comparison level 57 Signal delay time t1 58 Signal delay time t2 59 Signal delay time t3 60 Signal delay time t4 61 First additional capacitor 62 Second additional capacitor 65, 69 Additional capacitor connection relay 74 DUT board 75 Ring 76 Needle card 77 Socket board 78 Socket board cable 100 Measurement unit 110 Timing generator 120 Logic pattern generator 124 Logic pattern generation means 125 Logic pattern supply means 126 Expected value pattern supply means 130 Format controller 140 Pattern value comparison 145 Pattern comparison means 153 Pin cable 160 Fail analysis memory 170 DA converter 180 DC test unit 190 Programmable power supply 200 Control unit 210 CPU 220 Storage device 230 Input / output device 290 DUT input terminal 300 DUT 310 DUT output terminal 400 Pass / fail judgment means

Claims (8)

[Claims] An output unit that outputs a test pattern signal to the semiconductor device under test; and a signal comparator that compares a voltage of a signal input from the semiconductor device under test with a reference voltage according to the test pattern signal. An input unit, a tester pin for transmitting and receiving signals between the semiconductor device under test, and a signal connected to the tester pin and the input unit via first connection control means, the signal being caused by the semiconductor test device. A semiconductor test head comprising: signal delay compensation means for compensating a delay time. 2. The semiconductor test head according to claim 1, wherein said signal delay compensating means is provided for each tester pin. 3. The semiconductor test head according to claim 1, wherein said first connection control means is means for selectively controlling connection with a plurality of signal delay compensation means. 4. The semiconductor test head according to claim 1, wherein said signal delay compensation means comprises a capacitor. 5. The semiconductor test head according to claim 1, wherein said first connection control means comprises a semiconductor switch circuit. 6. The semiconductor according to claim 1, wherein said tester pin is selectively connected to said output section and said input section via second connection control means. Test head. 7. A test program including a test pattern and a judgment reference pattern for a semiconductor device under test, a signal of the test pattern is input to the semiconductor device under test, and a signal output from the semiconductor device under test is In a semiconductor test method for judging pass / fail of a semiconductor device under test by comparing with a judgment reference pattern, a first step of measuring a capacitance for each tester pin for one semiconductor test device, and a tester pin of the semiconductor test device And an input unit, a capacitor is selectively connected, an output signal delay time before and after the connection of the capacitor is measured for each of the tester pins, and a correlation between the capacitance and the output signal delay time is determined. A second step of guiding; a third step of measuring capacitance for each tester pin for another semiconductor test apparatus; A fourth step of calculating an output signal delay time for each tester pin for the other semiconductor test device from the correlation obtained in the step and the measurement value obtained in the third step; A fifth step of inputting the calculated value and converting the test program to compensate for the output signal delay time. 8. A CPU for controlling the entire system by issuing various command signals, a storage means for storing various information,
A control unit having input / output means for operating the CPU and displaying information; an internal power supply means; a logic pattern generating means for generating a test pattern signal and an expected value pattern signal according to a command from the CPU; A timing signal generating means for generating a clock pulse for determining a test timing in accordance with the command of the above; A format control means for outputting to the head; a digital signal sent from the CPU being converted into an analog signal to set a reference voltage of an output signal and an input signal to control an input driver and a signal comparator of the semiconductor test head. DA conversion means, and the format control means The test driver sends the test pattern signal to the semiconductor device under test by the input driver, compares the signal input from the semiconductor device under test with a reference voltage by the signal comparator, and compares the result with pattern value comparing means. The semiconductor test head according to any one of claims 1 to 6, wherein a comparison result signal transmitted from the semiconductor test head and an expected value pattern signal transmitted from the logic pattern generation unit are compared and analyzed. A semiconductor test system comprising: a pattern value comparison unit that sends an analysis result to a failure analysis storage unit; and a measurement unit that includes the fail analysis storage unit that stores information on an analysis result obtained by the pattern value comparison unit.