JPH10247648A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten the surfaces of insulating layers between wiring layers and to reduce a parasitic capacitance between wirings within each wiring layer by a method wherein a plurality of the second wiring layers are electrically connected with first wiring structures via through holes formed in an insulating film. SOLUTION: First wiring layers 12 are formed on the surface of a semiconductor substrate 11 and the layers 12 are respectively connected electrically with device structures at prescribed positions on the surface of the substrate 11. Second wiring layers 22 are arranged on an interlayer insulating layer 21 and one part of the layers 22 is electrically connected with the layer 12 via a contact hole 23. Third wiring layers 32 are formed on an interlayer insulating layer 31. Some of the layers 32 are electrically connected with the layers 22 via contact holes 33 and 34. An insulating layer 41 is arranged on the upper surfaces of the layers 32 in such a way as to cover the whole body. In this three-layer structure, wirings within each wiring layer are separated from the wirings adjacent to each other by each air gap, the dielectric constant of the wirings is equal with that of a vacuum and is about 1/3 of that of a silicon oxide film. A parasitic capacitance between the wirings is reduced to about 1/3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a highly integrated semiconductor device and a method of manufacturing the same, and more particularly to a high-speed and low power consumption highly integrated semiconductor device which can be manufactured at a low manufacturing cost and a method of manufacturing the same.

[0002]

2. Description of the Related Art As the degree of integration of a semiconductor integrated circuit device increases, the area occupied by circuit elements such as transistors and capacitors formed on a semiconductor chip decreases. The reduction in the area occupied by the circuit element leads to a reduction in the area occupied by the electrode structure and the wiring pattern formed thereon.

In order to reduce the width of the wiring to half and to pass the same current, the height of the wiring must be doubled in order to avoid deterioration of the wiring life due to an increase in current density. Even if the wiring intervals after forming the wiring patterns are the same, the aspect ratio of the gap between the wirings is doubled. If the wiring interval is also halved, the aspect ratio of the gap is quadrupled.

[0004] In a highly integrated semiconductor device, multilayer wiring is indispensable. When forming an upper wiring in the lower wiring layer, it is necessary to cover the surface of the lower wiring with an interlayer insulating film. If the surface irregularities of the interlayer insulating film are severe, not only is lithography difficult, but when a current is applied, wiring at the irregularities is
The disconnection is easily caused by the migration, and the reliability of the upper layer wiring is reduced. Therefore, various techniques for flattening the underlying surface of the wiring layer have been developed.

An example of the prior art will be described with reference to FIGS. In FIG. 7A, it is assumed that a semiconductor device structure is already formed on a semiconductor substrate 101, an interlayer insulating film is provided thereon, and the surface is planarized. An electrode structure 102 is formed on the semiconductor substrate 101.

As shown in FIG. 7B, the electrode structure 10
An insulating film 103 is formed, for example, by CVD on the surface of the substrate 101 on which the substrate 2 is formed. At this time, the electrode structure 1
If the aspect ratio of the gap between the layers 02 is high, the gap cannot be completely filled with the insulating film 103, and the cavity 10
4 may occur. Further, the insulating film 103 formed on the surface of the electrode structure 102 takes over the underlying shape, and the surface thereof has irregularities.

As shown in FIG. 7C, a wiring layer 110 is formed on the insulating film 103. The wiring layer 110 grows according to the shape of the underlying surface, a grain boundary is generated at a position corresponding to a boundary between the electrode structures 102, and a constricted portion 111 is easily generated on the surface.

When a wiring pattern is formed by patterning such a wiring layer 110 and a current is passed, electromigration is likely to occur due to a high resistance at a grain boundary portion. The movement of atoms in the wiring pattern 110 due to electromigration causes disconnection of the wiring. In order to eliminate such a failure, the insulating layer 10
3 flatten the surface, and form a wiring layer 110 on the flattened surface.
It is desired to form

There is a method of using a coating insulating film (such as SOG) instead of forming the CVD insulating film or together with the CVD insulating film. Since the coating insulating film is a liquid, a flat surface can be formed even when applied on a surface having a step. However, the quality of the oxide film formed by the coating insulating film is lower than that of the CVD insulating film. Further, when a thick coating insulating film is formed, cracks are apt to be formed in the insulating film. As described above, it is difficult to form a highly reliable insulating film using only the applied insulating film.

FIG. 8 shows an example in which an upper wiring is formed on an insulating film having a planarized surface. As shown in FIG. 7B, the surface of the semiconductor substrate on which the insulating film 103 has been grown is polished by, for example, chemical mechanical polishing (CMP) to flatten the surface.
The surface of the electrode structure 102 is exposed.

At this time, as shown in FIG. 8A, the upper end of the internal cavity 104 may be exposed on the upper surface.

When the upper end of the cavity 104 is exposed, as shown in FIG.
The surface is flattened and the electrode structure 102 is exposed.

As shown in FIG. 8C, an insulating film 107 is formed on a substrate whose surface is flattened. The insulating film 107 is
It can be formed flat on the flattened surface.

As shown in FIG. 8D, a wiring layer 110 is formed on the insulating film 107 having a flat surface. Since the wiring layer 110 is formed on a flat base, it has a flat surface and can prevent generation of grain boundaries inside. After that, the wiring layer 110 is patterned to form a wiring pattern.

Since the wiring layer 110 is formed on a flat surface, it is possible to prevent an accident such as a decrease in accuracy in photolithography or a disconnection during use.

BPSG containing boron (B) and phosphorus (P) in a silicon oxide film can be reflowed by a heat treatment. Even if the surface of the BPSG film immediately after the deposition has irregularities, for example, at a temperature of 850 ° C. or more,
By performing the heat treatment for about a minute or more, unevenness can be reduced. However, it has been reported that boron contained in BPSG has a radioactive isotope, generates neutrons, and causes a soft error similar to alpha rays. For this reason, BPSG containing B is in a direction of avoiding use. Further, the use of BPSG is limited to wiring using a high melting point material, and a low melting point material such as Al cannot be used because it cannot withstand 850 ° C. heat.

As described above, by flattening the surface of the insulating layer, the formation of the upper wiring becomes easy. However,
As the width and height of the wiring pattern become narrower, a problem different from the surface step occurs. When the height of the wiring layer doubles, the area of the side surface of the wiring layer also doubles, and the parasitic capacitance between adjacent wirings also increases. The increase in parasitic capacitance hinders high-speed operation and low power consumption of the integrated circuit.

In order to reduce the wiring resistance, studies have been made to use Cu instead of Al. However, it is known that Cu easily diffuses in the silicon oxide film.
When a silicon oxide film is used as an insulating film between wirings, C
There is a high possibility that the insulation between the u wirings is deteriorated. There is a demand for a technique using Cu wiring and realizing good insulation between the wirings.

[0019]

As semiconductor devices become more highly integrated, flattening of the surface of the insulating layer between wiring layers is required, and reduction in parasitic capacitance between wirings is desired.

An object of the present invention is to provide a semiconductor device capable of planarizing the surface of an insulating layer between wiring layers and reducing the parasitic capacitance between wirings.

Another object of the present invention is to provide a manufacturing method capable of efficiently manufacturing such a semiconductor device.

[0022]

According to one aspect of the present invention, there is provided a semiconductor chip having a device structure and a plurality of semiconductor chips formed on the semiconductor chip and having the same level of upper surface and separated from each other by a gap. A first wiring structure of
An insulating film attached to an upper surface of the first wiring structure and having a through hole on at least a part of the upper surface of the first wiring structure; and an insulating film formed on the insulating film and partially through the through hole. A semiconductor device having a plurality of second wiring layers electrically connected to the first wiring structures is provided.

According to another aspect of the present invention, a semiconductor chip having a device structure has an upper surface at the same level,
Forming a plurality of first wiring structures separated by a gap; and attaching an insulating film on top surfaces of the plurality of first wiring structures to form cavities between adjacent first wiring structures. And a wiring forming step of forming a second wiring on the insulating film.

By making the upper surfaces of many first wiring structures the same level and attaching an insulating film to the upper surfaces, the surface of the insulating layer can be flattened. In addition, since the first wiring structures are separated by the air gap, the parasitic capacitance is reduced.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1A, a first wiring structure 2 is formed on an insulating surface of a semiconductor substrate 1 on which a device structure is formed.
To form The first wiring structure 2 is electrically connected to a semiconductor device in the semiconductor substrate 1 at a predetermined position. The width of each first wiring structure is, for example, 0.25 μm or less, and the height is 0.5 μm or more. In particular, in a highly integrated semiconductor device, the width of the first wiring structure 2 is 0.15.
μm or less, and the height is 0.45 μm. In these wiring structures, the aspect ratio is 2 or more or 3 or more.

As shown in FIG. 1B, an auxiliary substrate having an insulating layer 4 and an adhesive layer 5 formed on a supporting substrate 3 is prepared separately from the semiconductor substrate 1. The support substrate 3 is formed of, for example, a metal such as Al or stainless steel, or a semiconductor or an insulator such as plastic such as silicon or polyimide. The insulating layer 4 is, for example, a silicon oxide film having a thickness of about 100 nm to 500 nm, and is formed by sputtering, CVD, SOG, or the like.
And the like.

The materials of the support substrate 3 and the insulating layer 4 are selected so that the support substrate 3 can be selectively removed by etching or the like. When the support substrate 3 is formed of a film such as a plastic, the support substrate 3 may be separated from the insulating layer 4. The adhesive layer 5 is provided as needed, and is for bonding the insulating layer 4 to the first wiring structure 2.
After bonding, it is formed of a material that becomes an insulator by being integrated with the insulating layer 4.

The first wiring structure 2 is a wiring pattern of, for example, Al or Cu. Further, a semiconductor material such as polycrystalline silicon such as a storage electrode of a capacitor of a DRAM may be used. It is assumed that the first wiring structure 2 has been flattened so that its upper surface is at the same level. The flattening process can be performed by, for example, chemical mechanical polishing (CMP). Of course, as long as it has an upper surface of the same level without performing the flattening process, it may be used as it is.

As shown in FIG. 1C, the auxiliary substrate 6 is turned upside down and arranged on the upper surface of the first wiring structure 2 on the semiconductor substrate 1. In this state, the auxiliary substrate 6 is bonded to the first wiring structure on the semiconductor substrate 1 (temporary fixing). For bonding,
It can be performed by an electrostatic adsorption method, a vacuum adsorption method, adhesion with an adhesive, or the like.

For example, when a metal substrate is used as the support substrate 3, a voltage is applied between the semiconductor substrate 1 and the support substrate 3, and the two are electrostatically bonded. Note that strong adhesion can be obtained by a subsequent heat treatment or the like.

The support substrate 3 may be formed of an aluminum substrate having an oxide film formed on the surface, an SOG film applied on the surface, and the two substrates bonded together using the SOG film as an adhesive layer.

As another method, an aluminum substrate is used as the support substrate 3, an SOG layer is used as the insulating layer 4 thereon, and a semi-dry state is obtained. No separate adhesive layer is used.
The semi-dried SOG layer has a strength enough to maintain a planar shape even after lamination, but has a softness enough to be bonded by pressure. Such two substrates can be bonded together.

After the two substrates are stacked, the environment including both the substrates is evacuated, the pressure in the internal space between the substrates is reduced, and then the substrate is taken out to the outside air. Due to the difference between the low pressure inside and the outside air pressure, both substrates are strongly pressed and bonded. Further, heat treatment may be performed, and the two substrates may be strongly bonded by using an interface melt or by OH bonding or the like.

After the two substrates are stacked, pressure may be applied from both sides to press the substrates together.

At the time of bonding, if both substrates are bowed in an arc shape and bonded gradually from the center, the possibility of leaving air bubbles near the center can be reduced.

After bonding the auxiliary substrate 6 on the semiconductor substrate, the support substrate 3 is removed as shown in FIG.
When the supporting substrate is Al, dissolving Al using an acid other than hydrofluoric acid leaves only the insulating layer 4. When the insulating layer 4 is formed of a silicon oxide film, the silicon oxide film is not etched by an acid other than hydrofluoric acid.

When a nitride film is used as the insulating layer 4, hydrofluoric acid can be used for removing the supporting substrate because the silicon nitride film has resistance to hydrofluoric acid. In addition, when plastic or the like is used for the support substrate, the insulating layer 4 is preferably formed by an SOG method, a sputtering method, or the like in accordance with the heat resistance of the support substrate.

A relatively soft film of vinyl or the like is used as the support substrate 3, an SOG film is applied to the surface, and the surface is adhered to the first wiring structure on the semiconductor substrate 1 while maintaining a flat surface by external force. It is possible. When an organic material such as plastic is used as the support substrate, the support substrate can be removed using an organic solvent or the like.

Further, an insulating film without a supporting substrate can be used as the auxiliary base 6. For example, a thin insulating film of polyimide or the like may be held on a support jig and softly bonded on the wiring structure.

Since the auxiliary substrate having the same structure can be used for various semiconductor devices, it can be mass-produced. If the cost is reduced by mass production, the increase in cost due to the use of the auxiliary base will be slight. On the other hand, since an interlayer insulating film having a flat surface is easily formed, manufacturing costs can be reduced.

A cavity 7 is formed between adjacent first wiring structures 2. Since this cavity is formed in a vacuum, low-pressure gas atmosphere, air, or the like, its dielectric constant is equivalent to that of a vacuum, and is about 1/3 of that of a silicon oxide film. Therefore, the parasitic capacitance between the wirings is reduced to about 1/3.

The insulating layer 4 provides a flat insulating surface on the first wiring structure 2. Therefore, the upper wiring layer can be easily formed on the insulating layer 4.

If necessary, a contact hole is formed through the insulating layer 4 (and the adhesive layer 5).
An electrical contact between the upper wiring layer formed thereon and the first wiring structure 2 is formed.

FIG. 2 schematically shows a wiring structure of a semiconductor device in which a multilayer wiring is formed by the steps shown in FIG.
FIG. 2A is a cross-sectional view, and FIG. 2B schematically shows a partial planar structure of a one-layer wiring structure.

In FIG. 2A, a first wiring layer 12 is formed on the surface of a semiconductor substrate 11. The first wiring layer 12
It is formed by laminating a Ti layer 12a, a TiN layer 12b, and an Al alloy layer 12c. The first wiring layer 12 is electrically connected to a device structure on the surface of the semiconductor substrate 11 at a predetermined position.

An interlayer insulating layer 21 is arranged on the first wiring layer 12 by the process described with reference to FIG. The interlayer insulating layer 21 has a contact hole 23. Interlayer insulation layer 2
The second wiring layer 22 is disposed on the first wiring layer 22. Part of the second wiring is electrically connected to the first wiring layer 12 through the contact hole 23.

On the upper surface of the second wiring layer 22, an interlayer insulating layer 3
1 is arranged. Contact holes 33 and 34 are formed in the interlayer insulating layer 31.

On the interlayer insulating layer 31, a third wiring layer 32
Are formed. Part of the second wiring layer 32 is electrically connected to the second wiring layer 22 via the contact holes 33 and 34. On the upper surface of the third wiring layer 32, an insulating layer 41 is disposed so as to cover the entire surface. This insulating layer 41 can also be formed by the process shown in FIG.

In this three-layer wiring structure, the wiring in each wiring layer is separated from the adjacent wiring by an air gap. Therefore, the parasitic capacitance between the wirings arranged at the same interval is reduced to １ ／ as compared with the case where the wiring is insulated and separated by the silicon oxide.

Since the surface of each interlayer insulating layer is flattened, the upper wiring layer can be easily formed.

FIG. 2B schematically shows a planar structure of the first wiring layer below the contact hole. The wiring layer 12
The portion located below the contact hole has a wide width. A contact hole 23 is formed on the wide portion, and the upper wiring is electrically connected through the contact hole 23.

FIG. 3 shows an example of the configuration of a chip peripheral portion. 3A shows a plan view of the wafer, FIG. 3B shows a plan view of the chips in the wafer, and FIG. 3C shows a cross-sectional view at a chip end.

As shown in FIG. 3A, the silicon wafer 51 includes a large number of semiconductor chips 52 on the surface thereof.

FIG. 3B shows one semiconductor chip 52 in an enlarged manner. A scribe area 53 is formed between each chip. In the scribe area 53, each chip 52 is separated by cutting the semiconductor wafer along the scribe line 54.

FIG. 3C shows a sectional structure around the scribe region. On the surface of the semiconductor substrate 11, a three-layer wiring structure as shown in FIG. 2 is formed. In the scribe area 53, the entire area is occupied by the wiring layers 12, 22, and 32. When the chip is cut along the scribe line 54, the side surface of the outer periphery of the chip becomes the wiring layer 12,
22 and 32 and the interlayer insulating layers 21, 31 and 41 are hermetically sealed.

The wiring layers 12, 22, and 32 arranged in the scribe area 53 are not used as wirings but are used as sealing members. Therefore,
It may be formed of a material different from the wiring layer actually used as the wiring, for example, a dielectric material.

Further, a dummy wiring layer having the same height as the wiring layer may be provided in a region other than the region where the wiring is actually provided, so as to support the interlayer insulating layer.

In FIG. 3C, the scribe area 53
This wiring layer surrounds the entire periphery of the chip in a loop shape. Although the inside of the chip is hermetically sealed by this, a plurality of loop-shaped dummy wiring layers may be further formed inside the chip to form a multiple seal structure.

The case where the upper surface of the wiring layer is adjusted to the same level and the interlayer insulating layer is disposed thereon has been described above.
An electrode structure can be used instead of the wiring layer on the semiconductor substrate. In this sense, in this specification, the wiring structure includes an electrode structure.

FIG. 4 shows a case where the above-mentioned air isolation type multilayer wiring structure is applied to a DRAM.

As shown in FIG. 4A, the semiconductor substrate 61
A field oxide film 62 is formed on the surface to define an active region. The portion shown on the left side in the figure corresponds to the memory cell region, and the portion shown on the right side corresponds to the contact portion of the peripheral circuit.

In the memory cell region, an insulated gate electrode structure 63 is formed on the surface of the active region. Gate electrode 6
Side wall spacers 64 are formed of an insulator or the like on the three side walls. Ion implantation is performed using the insulated gate electrode structure and the field oxide film 62 as a mask to form impurity-doped regions 65 and 66. The impurity-doped region 65 serves as a source / drain region of the memory cell region, and the impurity-doped region 66 serves as a contact formation region in a peripheral contact portion.

As shown in FIG. 4B, the semiconductor substrate 61
An insulating film 67 is formed on the surface, and the surface is planarized by CMP or the like.

As shown in FIG. 4C, a resist pattern is formed on the surface of the insulating film 67, and a contact hole 70 penetrating the insulating film 67 is formed. After that, the resist pattern is removed. By forming the contact holes, the impurity doped regions 65 and 66 are exposed in the contact holes.

As shown in FIG. 4D, a buried electrode 71 is formed in the contact hole 70. For example, a metal layer or a semiconductor layer is deposited on the surface and polished by CMP or the like to form a flat surface where the insulating film 67 is exposed.

As shown in FIG. 4E, a bit line 72 is formed by forming a conductive layer of metal or the like on the flattened surface and patterning it using a resist pattern.

As shown in FIG. 4F, an insulating layer 73 is formed to cover the bit line 72, and the surface is flattened by CMP or the like.

As shown in FIG. 5G, a resist pattern is formed on the insulating layer 73, and a contact hole 74 exposing the embedded electrode 71 is formed. After forming the contact hole, the resist pattern is removed.

As shown in FIG. 5H, a first doped polycrystalline silicon layer 75 is formed on a semiconductor substrate, and a silicon nitride film 76 is formed thereon by CVD. Forming a resist pattern on the surface of the silicon nitride film 76;
Silicon nitride film 76, first doped polycrystalline silicon layer 7
5 is patterned to form a storage electrode 75a in the memory cell region and an extraction electrode 75b in the peripheral contact region. Thereafter, an insulating layer 77 serving as a capacitor insulating film is deposited on the surface by CVD or the like. For example, the capacitor insulating film 77 is formed using a silicon nitride oxide film.

As shown in FIG. 5I, a second doped polycrystalline silicon layer 78 is deposited thinly (about 100 nm) on the substrate surface, anisotropically etched, and a first doped polycrystalline silicon layer 75a is formed. , 75b as sidewalls. In the cell portion, since the distance between the first doped polysilicon layers 75a is narrow, the distance between the first doped silicon layers 75a is completely the second as shown in FIG.
Although it is buried with doped polycrystalline silicon, it becomes a sidewall at a portion 75b of the peripheral contact region.
Second doped polycrystalline silicon layer 78 serves as a counter electrode in the memory cell region.

The steps so far are described in Japanese Patent Application No. 8-293.
No. 593 in the column of Examples. Next, the auxiliary base described in the above embodiment is attached on the upper surface,
An interlayer insulating layer is formed.

As shown in FIG. 6J, a contact hole 81 is formed in the insulating layer 80 attached on the surface of the substrate. In the peripheral contact region, the silicon nitride layer 76 exposed in the contact hole 81 is removed. Thus, the counter electrode 78 is exposed in the memory cell region, and the extraction electrode 75b is exposed in the peripheral contact region.

Thereafter, a wiring layer 82 of aluminum or the like is formed on the wiring layer 80, and is patterned to form an upper wiring layer. Note that 83 remains as a cavity.

If necessary, the upper wiring layer 82
The surface is flattened to form an interlayer insulating layer and an upper wiring layer.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
A Cu layer may be used as the wiring layer instead of the Al layer.
When a Cu layer is used, it is preferable to use a barrier metal serving as a Cu diffusion barrier as a lower layer. Since the side wall of the Cu wiring is isolated by the void, the problem of Cu diffusion in the side wall does not occur.

It will be obvious to those skilled in the art that various changes, improvements, combinations, and the like can be made.

[0078]

As described above, according to the present invention,
By isolating adjacent wirings with a cavity, the parasitic capacitance between the wirings can be reduced as compared with the case of dielectric isolation. For example, the parasitic capacitance is reduced to about 1/3 as compared with the case where a silicon oxide insulator is used.

By arranging an insulating layer having a flat surface on a large number of wiring structures whose upper surfaces are adjusted to the same level, formation of an upper wiring can be facilitated. Such a wiring layer can be formed by, for example, an auxiliary substrate bonding step and a support substrate removing step, so that the steps are simplified. Further, by bonding a flat insulating layer, extremely excellent flatness can be obtained.

The use of the versatile auxiliary base makes it possible to reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view and a bottom view schematically showing a configuration of a multilayer wiring semiconductor device according to an embodiment of the present invention.

FIGS. 3A and 3B are a plan view and a sectional view showing a configuration of a semiconductor wafer and each semiconductor chip therein according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the DRAM according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the DRAM according to the embodiment of the present invention.

FIG. 6 is a sectional view illustrating a manufacturing process of the DRAM according to the embodiment of the present invention;

FIG. 7 is a cross-sectional view for explaining an example of the related art.

FIG. 8 is a cross-sectional view for explaining an example of the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 first wiring structure 3 support substrate 4 insulating layer 5 adhesive layer 6 auxiliary base 7 cavity 11 semiconductor substrate 12 first wiring layer 21 interlayer insulating layer 22 second wiring layer 31 interlayer insulating layer 32 third wiring layer 41 insulation Layers 23, 33, 34 contact holes 53 scribe regions 54 scribe lines 61 semiconductor substrates 62 field insulating films 63 insulated gate electrodes 65, 66 impurity doped regions 67 insulating films 71 buried electrodes 72 bit lines 73 insulating films 75 first doped polycrystalline Silicon 77 Capacitor insulating film 78 Second doped polycrystalline silicon layer 80 Interlayer insulating layer 82 Upper wiring layer

Claims (9)

[Claims] A semiconductor chip having a device structure; a plurality of first wiring structures formed on the semiconductor chip, having upper surfaces at the same level, and separated from each other by a gap; An insulating film attached to the upper surface of the body and having a through hole on at least a part of the upper surface of the first wiring structure; and an insulating film formed on the insulating film and partially passing through the through hole. A plurality of second units electrically connected to one wiring structure
A semiconductor device having a wiring layer. 2. The method according to claim 1, wherein the plurality of second wiring layers have upper surfaces at the same level, are separated from each other by a gap, and further have another insulating film attached on the plurality of second wiring layers. Item 2. The semiconductor device according to item 1. 3. A sealing member formed in a loop around the semiconductor chip and having an upper surface at the same level as the plurality of first wiring structures, wherein the insulating film is formed on the entire upper surface of the sealing member. 3. The method according to claim 1, wherein the information is attached.
13. The semiconductor device according to claim 1. Forming a plurality of first wiring structures having an upper surface at the same level and separated by a gap on a semiconductor chip having a device structure; and upper surfaces of the plurality of first wiring structures. A method for manufacturing a semiconductor device, comprising: a flattening step of attaching an insulating film thereon to form a cavity between adjacent first wiring structures; and a wiring forming step of forming a second wiring on the insulating film. 5. The method according to claim 4, further comprising a step of forming a contact hole penetrating through the insulating film and reaching at least a part of the first wiring structure between the planarizing step and the wiring forming step. Of manufacturing a semiconductor device. 6. The step of preparing an auxiliary substrate having an insulating film on a supporting substrate, and the step of attaching the insulating film of the auxiliary substrate to an upper surface of a first wiring structure on the semiconductor chip. 6. The method according to claim 4, further comprising the step of: selectively removing the supporting substrate of the auxiliary base. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the auxiliary substrate has an adhesive layer on an insulating film, and the step of attaching the insulating film uses the adhesive layer. 8. The method according to claim 6, wherein the insulating film has an adhesive function. 9. Further, on the periphery of the semiconductor chip,
An upper surface at the same level as the plurality of first wiring structures;
9. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a sealing member having a loop-like planar shape, wherein said planarizing step includes attaching an insulating film also to the entire upper surface of said sealing member. Method.