JP4110776B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device formed using a planarization technique such as a CMP (Chemical Mechanical Polishing) method and a method for manufacturing the same.
[0002]
[Prior art]
In order to enable miniaturization of photolithography of a semiconductor wafer and to improve the reliability of a semiconductor device and to reduce variation in characteristics, it is necessary to remove irregularities on the element forming surface of the semiconductor wafer. As described above, various planarization techniques are used. As this planarization technique, a local or partial planarization technique is generally used, and specifically, there are methods such as an etch back method such as plasma etching, a film formation method, a fluidization method, and a selective growth method. is there.
[0003]
As a method for improving the flatness further than the flatness by the local or partial flattening technique, a CMP method which is a full flattening technique has recently attracted attention.
First, the case where planarization is performed using the etch back method will be described.
FIG. 8 is a cross-sectional view of a main part of a conventional semiconductor device flattened by an etch back method.
[0004]
A trench groove 52 is formed in the semiconductor substrate 51, an insulating film 53 (stopper) having a step 54 is formed on the surface of the semiconductor substrate 51, and the trench film 52 is covered with polysilicon 55. Filling and removing the polysilicon on the insulating film by the etch back method until the insulating film 53 as a stopper is exposed, the surface of the polysilicon 55 filling the trench groove 52 is flattened.
[0005]
[Problems to be solved by the invention]
However, in the planarization by the etch back method, the depth of the concave portion on the surface of the polysilicon 53 in the trench groove increases from several μm to several tens μm reflecting the depth of the trench groove 52. Therefore, when the metal electrode 56 is formed on the polysilicon 55, there is a problem that the accuracy of photolithography is not high. In addition, the bonding property between the polysilicon 55 and the metal electrode 56 is poor, and there is a problem that the contact is partially made and the electric resistance is increased, and electron migration due to current concentration is caused. Therefore, there is a problem of reducing reliability.
[0006]
A CMP method is known as a further planarization method than the etch back method.
FIG. 9 is a diagram illustrating the CMP method. Polysilicon formed on the semiconductor wafer 100 through an oxide film like a normal lapping machine while supplying a polishing liquid 64 in which silica is mixed with KOH to a buff 62 attached to a surface plate 61 (turn table). Is pressed against the buff 62, and the surface plate 61 and the support plate 63 on which the semiconductor wafer 100 is set are rotated together, and the polysilicon is planarized while mechanically and chemically removing it. The oxide film functions as a stopper film. In the CMP method, the polishing rate of polysilicon is about 500 times that of the oxide film and about 300 nm / min. In the following description, a portion where a semiconductor element is formed (a portion to be a semiconductor chip) in the semiconductor wafer 100 is referred to as a semiconductor substrate 51 and will be described here.
[0007]
This CMP method improves the flatness by an order of magnitude compared to the other methods described above, and is used to planarize polysilicon or the like that constitutes a trench capacitor of a DRAM that is a memory element.
FIG. 10 shows a method of manufacturing a semiconductor device flattened by the CMP method. FIGS. 10A to 10D are cross-sectional views of the main part shown in the order of steps.
[0008]
In FIG. 2A, a trench groove 52 is formed in a semiconductor substrate 51, an oxide film 53 (stopper) having a step 54 is formed thereon, and a polysilicon 55 is formed thereon.
In FIG. 6B, the polysilicon 55 is removed by CMP until the oxide film 53 in the second region 72 having a high elevation is exposed.
[0009]
In FIG. 6C, the CMP method is further continued, and the polysilicon 55 is removed until the oxide film 53 in the first region 71 having a low altitude is exposed. However, in the CMP method, the polysilicon 55a in the vicinity of the step 54 cannot be removed and remains. If the polysilicon 55a remains in this way, as shown in FIG. 11, the metal electrodes 61 and 62 in the first region 71 are electrically connected by the polysilicon 55a.
[0010]
In FIG. 4D, when the CMP method is further continued to remove the remaining polysilicon 55a, the surface of the oxide film 53 in the trench groove 52 formed in the first region 71 having a low elevation near the step 54 is obtained. As a result, the shape of the semiconductor substrate 51 may be lost, and the surface of the semiconductor substrate 51 may also be shaved. When the semiconductor substrate 51 is shaved, for example, there arises a disadvantage that the drain region of the MOSFET is missing.
[0011]
In other words, since the CMP method is originally an overall planarization technique, it is difficult to planarize each surface having the step 54. That is, without removing the stopper (oxide film 53), the polysilicon 55a in the vicinity of the stepped portion is removed, the surfaces having different elevations are flattened, and the polysilicon 55 of the trench groove 52 formed on each surface is obtained. It is difficult to planarize.
[0012]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and in a semiconductor device having a step on the surface and forming a trench groove, the surface of the polysilicon (conductive film) in the trench groove is planarized. Improves the reliability by improving the bondability between the metal and the metal wiring, preventing current concentration at this junction (current concentration of pulsed gate current that flows during switching), and remaining polysilicon near the step It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same that can prevent the occurrence of the problem and flatten the vicinity of the step and reliably form the unit element in the vicinity of the step.
[0013]
[Means for Solving the Problems]
To achieve the above object, a semiconductor substrate having at least two regions of a first region and a second region adjacent to the first region, a first trench groove formed in the first region, and the first region A second trench groove formed in two regions, a first insulating film formed in each of the first trench groove and on the first region, and a surface formed in each of the second trench groove and on the second region. A second insulating film having an elevation higher than the surface of the first insulating film; a first conductive film formed in the first trench groove; and a second conductive film formed in the second trench groove. In the semiconductor device, a step is formed at a connection portion between the first insulating film and the second insulating film, and the depth (flatness) of the concave portion on the surface of the conductive film is set to Y (nm). When the minimum width in the plane of the conductive film formed on the substrate is X (μm) , The depth Y of the recessed portion, a structure in the range of X ≦ Y ≦ 50X.
[0014]
The step is preferably 0.1 μm or more and 10 μm or less.
The conductive film may be formed of polysilicon or tungsten.
The depth of the trench is preferably 1 μm or more and 100 μm or less.
The step is preferably smaller than the distance from the surface to the bottom surface of the conductive film formed in the trench.
[0015]
Further, the first trench groove and the second trench groove are formed of one trench groove.
[0016]
Further, a semiconductor having at least first and second regions each having a first trench groove and a second trench groove, having a surface covered with an insulating film, a stepped portion at the boundary, and flat surfaces having different altitudes. Forming a filling film for filling the first trench groove and the second trench groove on the entire surface of the substrate, and exposing the first trench groove opening and the second trench groove opening on the first region; Until the filling film formed in the first trench groove and the second trench groove is flattened by CMP, and the height of the first and second regions is set using the insulating film as a stopper film. And a step of removing the filling film remaining on the insulating film in the stepped portion in a low region by etching.
[0017]
As described above, the conductive film remaining in the stepped portion can be removed by using the etching method that is the partial planarization method after using the CMP method that is the overall planarization method. The surface of the second region can be flattened.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
1 to 4 are block diagrams of a semiconductor device according to an embodiment of the present invention. FIG. 1 is a plan view of a main part, FIG. 2 is a cross-sectional view of a main part taken along line AB in FIG. FIG. 3 is a cross-sectional view of a main part cut along a line B-C in FIG. 1, and FIG. 3 is a cross-sectional view of a main part cut along a line C-D in FIG.
In FIG. 1, on a semiconductor substrate 1, a source metal wiring 12 connected to an n source region (not shown) by a contact hole 31, an n drain region formed at the bottom of a trench groove 23, a drain polysilicon 10 and a contact not shown. The drain metal wiring 13 connected through the hole and the gate metal wiring 14 connected to the gate polysilicon 7 through the contact hole 32 are formed.
[0019]
2 is a cross-sectional view of the main part of the main part of the semiconductor device in which the surface of FIG. 1 is formed in a first region 21 having a low elevation. A trench groove 23 is formed in the semiconductor substrate 1, an n drift region 2 is formed below the side surface and bottom surface of the trench groove 23, and an n drain region 3 is formed on the surface layer of the n drift region 2 below the bottom surface of the trench groove 23. Form. A p-well region 4 (sometimes referred to as a p-base region) is formed on the surface layer of the semiconductor substrate 1 and an n-source region 5 is formed on the surface layer of the p-region 4. An interlayer insulating film 8 is formed on the surface of the semiconductor substrate 1, and a gate oxide film 6, gate polysilicon 7, interlayer insulating film 9, and drain polysilicon are formed in the trench groove 31. An interlayer insulating film 11 is formed on the interlayer insulating films 8 and 9, a contact hole is opened, and a source metal wiring 12 and a drain metal wiring 13 are formed. The interlayer insulating film 8 is an oxide film and serves as a stopper when the drain polysilicon 10 is planarized.
[0020]
In FIG. 3, it is principal part sectional drawing just under the source metal wiring 12 of a semiconductor device. A p-well region 4 and an n-source region 5 are formed on the surface layer of the semiconductor substrate 1, and a gate oxide film 6, gate polysilicon 7, and interlayer insulating films 8 and 11 are formed on the n-source region 5. A contact hole is opened in 8 and 11 to form a source metal wiring 12. The left side is the first region 21 and the right side is the second region 22 with the stepped portion 26 of the interlayer insulating film 8 covering the gate polysilicon 7 as a boundary.
[0021]
4, this portion shows a portion where the gate polysilicon 7 in FIG. 2 and the gate metal wiring 14 in FIG. 1 are wired. This location is the second region 22 having a high surface elevation. A trench groove 23 is formed in the semiconductor substrate 1, and an n drift region 2 is formed below the side surface and the bottom surface of the trench groove 23. A gate oxide film 6, gate polysilicon 7, interlayer insulating film 8, interlayer insulating film 9, and drain polysilicon 10 are formed on the surface of the semiconductor substrate 1 and the side surfaces of the trench groove 23. An interlayer insulating film 11 is formed thereon, a contact hole is opened, and a drain metal wiring 13 and a gate metal wiring 14 are formed.
[0022]
As shown in FIG. 3, the connecting portion between the first region and the second region is a stepped portion 26. The step size Z is the sum of the thickness of the gate oxide film 6 formed in the second region and the thickness of the interlayer insulating film 8.
The depth Y (nm) of the concave portion on the surface of the drain polysilicon 10 filling the trench groove 23 shown in FIG. 2 is determined by the CMP method using the drain polysilicon filling the trench groove 23 via the interlayer insulating film. The range is Y ≧ X and Y ≦ 50X with respect to the minimum width X (μm) of the silicon 10.
[0023]
For example, when X is 3 μm, Y is in the range of 3 nm to 150 nm, and in the present example, it is about 50 nm.
Further, instead of the polysilicon described above, a metal used as a wiring or an electrode may be used. For example, tungsten, aluminum, copper, etc. are mentioned. In this case, it is preferable to form a barrier metal such as Ti, TiN, TaN, or WN in the trench groove and then fill it. In this way, when two or more layers are formed, it can be dealt with by returning the CMP etch-back conditions in the middle.
[0024]
Further, the step portion 26 needs to be smaller than the distance from the surface to the bottom surface of the drain polysilicon 10 formed in the trench groove 23. This is because, when the size of the stepped portion 26 is increased, the drain polysilicon 10 is completely removed when the polysilicon remaining in the stepped portion 26 is removed.
Normally, since the depth of the trench groove 23 is about 1 μm to 100 μm, the size Z of the stepped portion should be about one tenth, and preferably 0.1 μm to 10 μm.
[0025]
FIG. 5 shows a manufacturing method of the semiconductor device shown in FIGS. 1 to 4, and FIGS. 5A to 5D are cross-sectional views of essential parts shown in the order of processes. 5 collectively shows the gate oxide film 6, the gate polysilicon 7, and the interlayer insulating films 8 and 9 of the semiconductor device shown in FIGS. 1 to 4 as a thin film 24, and the surface layer of the thin film 24 is composed of an oxide film. Is done.
In FIG. 2A, a trench groove 23 and a thin film 24 having a stepped portion 26 are formed on a semiconductor substrate 1, and polysilicon 25 serving as drain polysilicon 10 is deposited thereon.
[0026]
In FIG. 6B, the polysilicon 25 is removed by CMP using the thin film 24 in the second region 22 having a high altitude as a stopper to expose the thin film 24 in the second region 22 having a high altitude, and the trench groove 23 is formed. The polysilicon 25b is planarized. At this time, the trench groove 23 in the first region 21 having a low elevation is filled with the polysilicon 25a, and the polysilicon 25c remains on the entire surface of the thin film 24 in the first region 21. At this time, the depth of the recess on the surface of the polysilicon 25c is the same as the depth of the recess on the surface of the polysilicon 25b.
[0027]
In FIG. 5C, the polysilicon 25c is removed by CMP using the thin film 24 in the first region 21 having a low elevation as a stopper, and the thin film in the first region 21 having a low elevation except for the step portion 26. 24 is exposed, and the polysilicon 25a in the trench 23 is flattened. At this stage, polysilicon remains as residual polysilicon 25d on the thin film 24 in the first region 21 where the elevation of the step portion 26 is low. At this time, the depth of the concave portion of the polysilicon 25a is the same as that of the polysilicon 25b and falls within the range of the previous formula.
[0028]
In FIG. 4D, the remaining polysilicon 25d is removed by an etching method such as dry etching such as plasma or wet etching immersed in a hydrofluoric acid solution. At this time, the surfaces of the polysilicons 25a and 25b are also removed by an amount corresponding to the level difference (its size is Z). At this time, the shape of the recess on the surface of the polysilicon 25a is almost unchanged before etching (FIG. 6A: this is an enlarged view of part a) and after etching (FIG. 6B: this is an enlarged view of part b). Accordingly, since the entire step is removed, the depth of the recesses in the polysilicon 25a and 25b is obtained by adding the size Z of the step portion to the Y value.
[0029]
As described above, the remaining polysilicon 25d remaining in the stepped portion 26 in the CMP process can be planarized including the stepped portion 26 by removing by etching. FIG. 7B is a cross-sectional view taken along line E-F in FIGS. 7A and 7A in order to remove the residual polysilicon 25d in the step portion 26 by this planarization. As described above, when there is the remaining polysilicon 25d, the source metal wiring 12 and the drain metal wiring 13 are short-circuited through the remaining polysilicon 25d, respectively, but this does not occur. Further, since the cross-sectional shape of the concave portion on the surface of the polysilicon does not change even by this etching, as described above, the depth Y of the concave portion on the surface of the polysilicon 25a, 25b (this becomes the drain polysilicon 10). (Nm) is in the range of Y ≧ X and Y ≦ 50X with respect to the minimum width W (μm) of the polysilicon 25a and 25b. On the other hand, the depth of the semiconductor substrate surface and the recess after etching is a value obtained by adding a step amount to this Y value.
[0030]
In this embodiment, the interlayer insulating films 8 and 9 constituting the thin film 24 used as the stopper film are oxide films such as HTO (thermal CVD film), and the film to be removed (film to be cut) is polysilicon. As an example. This is because the removal rate (polishing or etching rate) of the oxide film is as low as several tenths to one hundredth of that of polysilicon. Therefore, the stopper film may be selected from a material whose removal rate is significantly smaller than the film to be cut, and is not limited to the oxide film.
[0031]
In the above embodiment, the number of the step portions 26 is one, but even when there are a plurality of steps (three or more different flat surfaces), the same effect can be obtained by combining the CMP method and the etching method. .
[0032]
【The invention's effect】
According to the present invention, by planarizing by combining the CMP method and the etching method, even when there is a step on the surface, it is possible to planarize both a high altitude region and a low altitude region, and the conductive material remaining in the step portion. The film (polysilicon or tungsten) can be removed and planarized including the vicinity of the stepped portion.
[0033]
Further, by using the CMP method, the flatness Y (nm) of the surface of the polysilicon formed in the trench groove can be reduced to a range of X ≦ Y ≦ 50X. However, X is the minimum width X (μm) of the opening of the trench.
By planarizing the surface of the polysilicon, it is possible to improve the bonding property between the polysilicon and the metal wiring, to prevent current concentration at this bonding portion, and to improve the reliability.
[0034]
Further, by removing the remaining polysilicon in the vicinity of the step and flattening the vicinity of the step, a unit element (such as a MOSFET) can be reliably formed in the vicinity of the step.
[Brief description of the drawings]
1 is a plan view of an essential part of a semiconductor device according to an embodiment of the present invention; FIG. 2 is a sectional view of the essential portion of the semiconductor device according to an embodiment of the present invention, cut along line AB in FIG. 3 is a cross-sectional view of the main part of the semiconductor device according to one embodiment of the present invention, cut along line B-C in FIG. 1. FIG. 4 is a semiconductor device according to one embodiment of the present invention, taken along CD in FIG. FIG. 5 is a manufacturing method of the semiconductor device shown in FIGS. 1 to 4, and (a) to (d) are cross-sectional views of the main part shown in the order of the processes. FIG. 5C is an enlarged view of part a in FIG. 5C, FIG. 7C is an enlarged view of part a in FIG. 5C. FIG. 7A shows a case where there is residual polysilicon, and FIG. b) is a view corresponding to FIG. 2. FIG. 8 is a cross-sectional view of a main part of a conventional semiconductor device flattened by an etch back method. FIG. 9 is a view for explaining a CMP method. In the manufacturing method of the semiconductor device, (a) from (d) are EXPLANATION OF REFERENCE NUMERALS schematic plan view of the semiconductor device when the main part sectional views showing the process order [11] polysilicon remaining
1 semiconductor substrate 2 n drift region 3 n drain region 4 p well region 5 n source region 6 gate oxide film 7 gate polysilicon 8, 9, 11 interlayer insulating film 10 drain polysilicon 12 source metal wiring 13 drain metal wiring 14 Gate metal wiring 21 First region 22 Second region 23 Trench groove 24 Thin film 25, 25a, 25b, 25c Polysilicon 25d Residual polysilicon 31, 32 Contact hole X Minimum width Y of drain polysilicon The drain polysilicon Depth of recesses on the surface of

Claims (7)

A semiconductor substrate having at least two regions of a first region and a second region adjacent to the first region, a first trench groove formed in the first region, and a second trench formed in the second region The surface of the first insulating film is defined by the groove, the first insulating film formed in the first trench groove and on the first region, and the elevation of the surface formed in the second trench groove and on the second region, respectively. In the semiconductor device having a higher second insulating film, a first conductive film formed in the first trench groove, and a second conductive film formed in the second trench groove, the first insulating film And the second insulating film are stepped, the depth (flatness) of the concave portion on the surface of the conductive film is Y (nm), and the plane of the conductive film formed in the trench groove When the minimum width at X is X (μm), the depth Y of the recess is X ≦ Y ≦ Wherein a is in the range of 0X. The semiconductor device according to claim 1, wherein the step is 0.1 μm or more and 10 μm or less. The semiconductor device according to claim 1, wherein the conductive film is formed of polysilicon or tungsten. The semiconductor device according to claim 1, wherein a depth of the trench is 1 μm or more and 100 μm or less. The semiconductor device according to claim 1, wherein the step is smaller than a distance from a surface to a bottom surface of the conductive film formed in the trench groove. The semiconductor device according to claim 1, wherein the first trench groove and the second trench groove are formed of one trench groove. The entire surface of the semiconductor substrate having a first trench groove and a second trench groove respectively, the surface is covered with an insulating film, has a stepped portion at the boundary, and has at least first and second regions composed of flat surfaces with different elevations And forming a filling film for filling the first trench groove and the second trench groove until the first trench groove opening and the second trench groove opening on the first region are exposed. A step of flattening the filling film formed in the first trench groove and the second trench groove by a CMP method, and using the insulating film as a stopper film, the height of the first and second regions is low. And a step of removing the filling film remaining on the insulating film in the step portion of the region by etching.

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