JP3962443B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a highly integrated semiconductor device and a method for manufacturing the same, and more particularly to a high-integrated semiconductor device with high speed and low power consumption that can be manufactured at a low manufacturing cost and a method for manufacturing the same.
[0002]
[Prior art]
As the degree of integration of semiconductor integrated circuit devices increases, the area occupied by circuit elements such as transistors and capacitors formed on the semiconductor chip decreases. Reduction of the occupied area of the circuit element leads to reduction of the occupied area of the electrode structure and wiring pattern formed thereon.
[0003]
In the case where the same current is caused to flow by halving the width of the wiring, the height of the wiring is doubled to avoid deterioration of the wiring life due to an increase in current density. Even if the wiring interval after forming the wiring pattern is the same, the aspect ratio of the gap between the wirings is doubled. If the wiring interval is also halved, the aspect ratio of the gap is quadrupled.
[0004]
In highly integrated semiconductor devices, multilayer wiring is essential. When forming the upper wiring in the lower wiring layer, it is necessary to cover the lower wiring surface with an interlayer insulating film. If the irregularities on the surface of the interlayer insulating film are severe, not only lithography becomes difficult, but also when current is passed, the wiring in the irregularities is easily disconnected due to migration, and the reliability of the upper layer wiring is lowered. Therefore, various techniques for flattening the underlying surface of the wiring layer have been developed.
[0005]
An example of the prior art will be described with reference to FIGS. In FIG. 7A, it is assumed that a semiconductor device structure is already formed over the semiconductor substrate 101, an interlayer insulating film is provided thereon, and the surface is planarized. An electrode structure 102 is formed on the semiconductor substrate 101.
[0006]
As shown in FIG. 7B, an insulating film 103 is formed on the surface of the substrate 101 on which the electrode structure 102 is formed by, for example, CVD. At this time, if the aspect ratio of the gap between the electrode structures 102 is high, the gap cannot be completely filled with the insulating film 103, and a cavity 104 may be generated. Further, the insulating film 103 formed on the surface of the electrode structure 102 takes over the base shape, and unevenness is generated on the surface.
[0007]
As shown in FIG. 7C, a wiring layer 110 is formed over the insulating film 103. The wiring layer 110 grows following the shape of the underlying surface, a grain boundary is generated at a position corresponding to the boundary between the electrode structures 102, and a constricted portion 111 is easily generated on the surface.
[0008]
When such a wiring layer 110 is patterned to form a wiring pattern and a current is passed, resistance at the grain boundary portion is high and electromigration is likely to occur. If atoms in the wiring pattern 110 move due to electromigration, it may cause disconnection of the wiring. In order to eliminate such a failure, it is desirable to flatten the surface of the insulating layer 103 and form the wiring layer 110 on the flattened surface.
[0009]
There is a method of using a coating insulating film (such as SOG) instead of forming the CVD insulating film or together with the CVD insulating film. Since the coating insulating film is a liquid, a flat surface can be formed even if the coating insulating film is coated on a stepped surface. However, the quality of the oxide film formed by the coating insulating film does not reach that of the CVD insulating film. Further, when a thick coating insulating film is formed, cracks are likely to enter the insulating film. As described above, it is difficult to form a highly reliable insulating film using only the coated insulating film.
[0010]
FIG. 8 shows an example in which upper wiring is formed on an insulating film whose surface is planarized.
As shown in FIG. 7B, the surface of the semiconductor substrate on which the insulating film 103 is grown is polished by, for example, chemical mechanical polishing (CMP), the surface is flattened, and the surface of the electrode structure 102 is exposed.
[0011]
As shown in FIG. 8A, at this time, the upper end of the internal cavity 104 may be exposed on the upper surface.
[0012]
As shown in FIG. 8B, when the upper end of the cavity 104 is exposed, the interior of the cavity 104 is filled with SOG 106 or the like, and further polished as necessary to flatten the surface and the electrode structure 102 is formed. Expose.
[0013]
As shown in FIG. 8C, an insulating film 107 is formed over a substrate whose surface is planarized. The insulating film 107 can be formed flat over the flattened surface.
[0014]
As shown in FIG. 8D, the wiring layer 110 is formed over the insulating film 107 having a flat surface. Since the wiring layer 110 is formed on a flat base, it has a flat surface and can prevent grain boundaries from being generated inside. Thereafter, the wiring layer 110 is patterned to form a wiring pattern.
[0015]
Since the wiring layer 110 is formed on a flat surface, it is possible to prevent accidents such as a decrease in accuracy in photolithography and disconnection during use.
[0016]
Further, BPSG containing boron (B) and phosphorus (P) in the silicon oxide film can be reflowed by heat treatment. Even if the surface of the BPSG film immediately after deposition has irregularities, the irregularities can be reduced by performing a heat treatment for about 10 minutes or more at a temperature of 850 ° C. or higher. However, it is reported that boron contained in BPSG has radioactive isotopes, and neutrons are generated, causing soft errors similar to alpha rays. For this reason, BPSG including B is in a direction to avoid use. The use of BPSG is limited to wiring using a high melting point material, and a low melting point material such as Al cannot withstand the heat of 850 ° C. and cannot be used.
[0017]
As described above, by flattening the surface of the insulating layer, it becomes easy to form the upper layer wiring. However, as the width of the wiring pattern becomes narrower and the height becomes higher, another problem arises from the step on the surface. When the height of the wiring layer is doubled, the area of the side surface of the wiring layer is also doubled, and the parasitic capacitance between adjacent wirings is also increased. The increase in parasitic capacitance hinders the high speed operation and low power consumption of the integrated circuit.
[0018]
In order to reduce the wiring resistance, the use of Cu instead of Al has been studied. However, it is known that Cu easily diffuses in the silicon oxide film. When a silicon oxide film is used as the insulating film between the wirings, the insulation between the Cu wirings is likely to deteriorate. There is a demand for a technique that uses Cu wiring and realizes good insulation between wirings.
[0019]
[Problems to be solved by the invention]
Along with higher integration of semiconductor devices, it is required to flatten the surface of an insulating layer between wiring layers and to reduce parasitic capacitance between wirings.
[0020]
An object of the present invention is to provide a semiconductor device capable of flattening the surface of an insulating layer between wiring layers and reducing parasitic capacitance between wirings.
[0021]
Another object of the present invention is to provide a manufacturing method capable of efficiently manufacturing such a semiconductor device.
[0022]
[Means for Solving the Problems]
According to one aspect of the present invention,
A semiconductor chip having a device structure;
A plurality of wiring structures formed on the semiconductor chip, having an upper surface at the same level and separated from each other by a gap;
The reaching side surfaces of the semiconductor chip periphery in the semiconductor chip periphery are formed in a loop shape, and the seal member having a top surface of the plurality of wiring structure and the same level,
An insulating film affixed on the upper surface of the wiring structure and the entire upper surface of the seal member;
I have a,
A semiconductor device in which the outer periphery of the semiconductor chip is hermetically sealed by the seal member and the insulating film is provided.
[0023]
According to another aspect of the invention,
Forming a plurality of wiring structures having a top surface at the same level and separated by air gaps on a semiconductor chip having a device structure of a semiconductor substrate including a plurality of semiconductor chips;
A position included between a peripheral and on the scribe line of the semiconductor chip of the semiconductor substrate has a top surface of the plurality of interconnect structure and the same level, forming a seal member having a loop-like planar shape,
A planarization step of attaching an insulating film on the upper surface of the plurality of wiring structures and on the entire upper surface of the seal member, and forming a gap between adjacent wiring structures;
Cutting the semiconductor substrate along the scribe line on the seal member to form a semiconductor chip in which the outer periphery of the semiconductor chip is hermetically sealed by the seal member and the insulating film ;
A method for manufacturing a semiconductor device is provided.
[0024]
The surface of the insulating layer can be flattened by making the upper surfaces of many first wiring structures the same level and attaching an insulating film to the upper surfaces. Further, since the first wiring structures are separated by the air gap, the parasitic capacitance is reduced.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0026]
As shown in FIG. 1A, a first wiring structure 2 is formed on an insulating surface of a semiconductor substrate 1 on which a device structure is formed. The first wiring structure 2 is electrically connected to the semiconductor device in the semiconductor substrate 1 at a predetermined position. The width of each first wiring structure is, for example, 0.25 μm or less, and the height is 0.5 μm or more. In particular, in a highly integrated semiconductor device, the width of the first wiring structure 2 is 0.15 μm or less and the height is 0.45 μm. In these wiring structures, the aspect ratio is 2 or more, or 3 or more.
[0027]
As shown in FIG. 1B, an auxiliary substrate in which an insulating layer 4 and an adhesive layer 5 are formed on a supporting substrate 3 is prepared separately from the semiconductor substrate 1. The support substrate 3 is formed of a metal such as Al or stainless steel, or a semiconductor or insulator such as plastic such as silicon or polyimide. The insulating layer 4 is a silicon oxide film having a thickness of about 100 nm to 500 nm, for example, and can be formed by sputtering, CVD, SOG, or the like.
[0028]
The materials of the support substrate 3 and the insulating layer 4 are selected so that the support substrate 3 can be selectively removed by etching or the like. When the support substrate 3 is formed of a film such as plastic, the support substrate 3 may be peeled from the insulating layer 4. The adhesive layer 5 is provided as necessary, and is used for adhering the insulating layer 4 to the first wiring structure 2. The adhesive layer 5 is formed of an insulating material that is integrated with the insulating layer 4 after bonding.
[0029]
The first wiring structure 2 is a wiring pattern such as Al or Cu. Further, it may be a semiconductor material such as polycrystalline silicon such as a storage electrode of a DRAM capacitor. It is assumed that the first wiring structure 2 is flattened so that the upper surface thereof is at the same level. The planarization process can be performed by, for example, chemical mechanical polishing (CMP). Of course, as long as it has the same level upper surface, it is not necessary to perform the flattening process.
[0030]
As shown in FIG. 1C, the auxiliary base 6 is turned over and placed on the upper surface of the first wiring structure 2 on the semiconductor substrate 1. In this state, the auxiliary substrate 6 is bonded to the first wiring structure on the semiconductor substrate 1 (temporarily fixed). Bonding can be performed by an electrostatic adsorption method, a vacuum adsorption method, adhesion with an adhesive, or the like.
[0031]
For example, when using a metal substrate as the support substrate 3, a voltage is applied between the semiconductor substrate 1 and the support substrate 3, and both are electrostatically bonded. Note that strong adhesion can be obtained by subsequent heat treatment or the like.
[0032]
The support substrate 3 may be formed of an aluminum substrate having an oxide film formed on the surface, an SOG film may be applied to the surface, and the two substrates may be bonded using the SOG film as an adhesive layer.
[0033]
As another method, an aluminum substrate is used as the support substrate 3 and an SOG layer is used as the insulating layer 4 thereon, so that the substrate is semi-dry. A separate adhesive layer is not used. This semi-dry SOG layer has such a strength that it can maintain a planar shape even after being bonded, but has a softness that can be bonded by pressure. Such both substrates can also be bonded together.
[0034]
After stacking both substrates, the environment including both substrates is evacuated, the pressure in the internal space between the substrates is lowered, and then taken out into the outside air. Due to the difference between the internal low pressure and the external pressure, both substrates are strongly pressed and bonded together. Further, heat treatment may be performed to use the melt at the interface, or to strongly bond the two substrates by OH bonding or the like.
[0035]
Alternatively, after the two substrates are stacked, the two may be pressure-bonded by applying pressure from both sides.
[0036]
At the time of bonding, if both substrates are warped in a bow shape and gradually bonded from the center, the possibility of leaving bubbles near the center can be reduced.
[0037]
After the auxiliary substrate 6 is bonded to the semiconductor substrate, the support substrate 3 is removed as shown in FIG. When the support substrate is Al, if the Al is dissolved using an acid other than hydrofluoric acid, only the insulating layer 4 remains. When the insulating layer 4 is formed of a silicon oxide film, the silicon oxide film is not etched with an acid other than hydrofluoric acid.
[0038]
When a nitride film is used as the insulating layer 4, the silicon nitride film is resistant to hydrofluoric acid, so hydrofluoric acid can be used to remove the support substrate. Moreover, when using plastic etc. for a support substrate, it is preferable to produce the insulating layer 4 by SOG method, a sputtering method, etc. according to the heat resistance of a support substrate.
[0039]
It is also possible to use a relatively soft film such as vinyl as the support substrate 3, apply an SOG film on the surface, and bond the first substrate to the first wiring structure on the semiconductor substrate 1 while maintaining a flat surface by external force. . When an organic material such as plastic is used as the support substrate, the support substrate can be removed using an organic solvent or the like.
[0040]
Furthermore, an insulating film without a supporting substrate can be used as the auxiliary substrate 6. For example, a thin insulating film such as polyimide may be held on a support jig and softly bonded onto the wiring structure.
[0041]
Since the auxiliary substrate having the same structure can be used for various semiconductor devices, it can be mass-produced. If the cost is reduced by mass production, the cost increase due to the use of the auxiliary base will be small. On the other hand, since it is easy to form an interlayer insulating film having a flat surface, the manufacturing cost can be reduced.
[0042]
A cavity 7 is formed between the adjacent first wiring structures 2. Since this cavity is formed by a vacuum, a low-pressure gas atmosphere, air, or the like, the dielectric constant is equivalent to the dielectric constant of vacuum, which is about 1/3 of the silicon oxide film. Therefore, the parasitic capacitance between the wirings is about 1/3.
[0043]
The insulating layer 4 provides a flat insulating surface on the first wiring structure 2. For this reason, an upper wiring layer can be easily formed on the insulating layer 4.
[0044]
If necessary, a contact hole is formed through the insulating layer 4 (and the adhesive layer 5), and electrical contact between the upper wiring layer formed on the insulating layer 4 and the first wiring structure 2 is formed.
[0045]
FIG. 2 schematically shows a wiring structure of a semiconductor device in which a multilayer wiring is formed by the process as shown in FIG. 2A shows a cross-sectional view, and FIG. 2B schematically shows a partial planar structure of a one-layer wiring structure.
[0046]
In FIG. 2A, a first wiring layer 12 is formed on the surface of the semiconductor substrate 11. The first wiring layer 12 is formed by stacking a Ti layer 12a, a TiN layer 12b, and an Al alloy layer 12c. The first wiring layer 12 is electrically connected to the device structure on the surface of the semiconductor substrate 11 at a predetermined position.
[0047]
An interlayer insulating layer 21 is disposed on the first wiring layer 12 by the process described in FIG. The interlayer insulating layer 21 has a contact hole 23. A second wiring layer 22 is disposed on the interlayer insulating layer 21. A part of the second wiring is electrically connected to the first wiring layer 12 through the contact hole 23.
[0048]
An interlayer insulating layer 31 is disposed on the upper surface of the second wiring layer 22. Contact holes 33 and 34 are formed in the interlayer insulating layer 31.
[0049]
A third wiring layer 32 is formed on the interlayer insulating layer 31. A part of the second wiring layer 32 is electrically connected to the second wiring layer 22 through contact holes 33 and 34. An insulating layer 41 is disposed on the upper surface of the third wiring layer 32 so as to cover the whole. The insulating layer 41 can also be formed by the process shown in FIG.
[0050]
In this three-layer wiring structure, the wiring in each wiring layer is separated from the adjacent wiring by an air gap. Therefore, the parasitic capacitance between the wirings arranged at the same interval is reduced to 1/3 as compared with the case where the insulation is separated by silicon oxide.
[0051]
Since the surface of each interlayer insulating layer is flattened, the upper wiring layer can be easily formed.
[0052]
FIG. 2B schematically shows a planar structure of the first wiring layer under the contact hole. The wiring layer 12 is formed with a wide width at a portion disposed under the contact hole. A contact hole 23 is formed on the wide portion, and the upper layer wiring is electrically connected through the contact hole 23.
[0053]
FIG. 3 shows a configuration example of the peripheral portion of the chip. 3A shows a plan view of the wafer, FIG. 3B shows a plan view of chips in the wafer, and FIG. 3C shows a cross-sectional view at the end of the chip.
[0054]
As shown in FIG. 3A, the silicon wafer 51 includes a large number of semiconductor chips 52 in its surface.
[0055]
FIG. 3B shows an enlarged view of one semiconductor chip 52. A scribe region 53 is formed between the chips. Each chip 52 is separated by cutting the semiconductor wafer along the scribe line 54 in the scribe region 53.
[0056]
FIG. 3C shows a cross-sectional structure around the scribe region. A three-layer wiring structure as shown in FIG. 2 is formed on the surface of the semiconductor substrate 11. In the scribe region 53, the entire region is occupied by the wiring layers 12, 22, and 32. When the chip is cut along the scribe line 54, the side surfaces on the outer periphery of the chip are hermetically sealed by the wiring layers 12, 22, 32 and the interlayer insulating layers 21, 31, 41.
[0057]
Note that the wiring layers 12, 22, and 32 disposed in the scribe region 53 are not used as wiring, but are used as sealing members. Therefore, it may be formed of a material different from the wiring layer actually used as the wiring, for example, a dielectric material.
[0058]
Further, a dummy wiring layer having the same height as the wiring layer may be disposed in addition to a region where the wiring is actually disposed, and may serve to support the interlayer insulating layer.
[0059]
In FIG. 3C, the wiring layer of the scribe region 53 surrounds the entire periphery of the chip in a loop shape. As a result, the inside of the chip is hermetically sealed, but a plurality of loop dummy wiring layers may be formed further inside to form a multiple seal structure.
[0060]
As described above, the case where the upper surface of the wiring layer is adjusted to the same level and the interlayer insulating layer is arranged thereon has been described. However, an electrode structure can be used instead of the wiring layer on the semiconductor substrate. In this sense, in this specification, the wiring structure includes an electrode structure.
[0061]
FIG. 4 shows a case where the above-described air isolation multilayer wiring structure is applied to a DRAM.
[0062]
As shown in FIG. 4A, a field oxide film 62 is formed on the surface of the semiconductor substrate 61 to define an active region. In the drawing, the portion shown on the left side corresponds to the memory cell region, and the portion shown on the right side corresponds to the contact portion of the peripheral circuit.
[0063]
In the memory cell region, an insulated gate electrode structure 63 is formed on the active region surface. Side wall spacers 64 are formed on the side walls of the gate electrode 63 with an insulator or the like. Ion implantation is performed using the insulated gate electrode structure and the field oxide film 62 as a mask to form impurity doped regions 65 and 66. The impurity doped region 65 becomes a source / drain region of the memory cell region, and the impurity doped region 66 becomes a contact formation region in the peripheral contact portion.
[0064]
As shown in FIG. 4B, an insulating film 67 is formed on the surface of the semiconductor substrate 61, and the surface is planarized by CMP or the like.
[0065]
As shown in FIG. 4C, a resist pattern is formed on the surface of the insulating film 67 and a contact hole 70 penetrating the insulating film 67 is formed. Thereafter, the resist pattern is removed. By forming the contact hole, the impurity doped regions 65 and 66 are exposed in the contact hole.
[0066]
As shown in FIG. 4D, a buried electrode 71 is formed in the contact hole 70. For example, a metal layer or a semiconductor layer is deposited on the surface and polished by CMP or the like to form a flat surface with the insulating film 67 exposed.
[0067]
As shown in FIG. 4E, a bit line 72 is formed by forming a conductive layer such as metal on the planarized surface and patterning it using a resist pattern.
[0068]
As shown in FIG. 4F, an insulating layer 73 is formed to cover the bit line 72, and the surface is planarized by CMP or the like.
[0069]
As shown in FIG. 5G, a resist pattern is formed over the insulating layer 73 and a contact hole 74 exposing the embedded electrode 71 is formed. After the contact hole is formed, the resist pattern is removed.
[0070]
As shown in FIG. 5H, a first doped polycrystalline silicon layer 75 is formed on a semiconductor substrate, and a silicon nitride film 76 is further formed thereon by CVD. A resist pattern is formed on the surface of the silicon nitride film 76, the silicon nitride film 76 and the first doped polycrystalline silicon layer 75 are patterned, and a storage electrode 75a is formed in the memory cell region and an extraction electrode 75b is formed in the peripheral contact region. Thereafter, an insulating layer 77 to be a capacitor insulating film is deposited on the surface by CVD or the like. For example, the capacitor insulating film 77 is formed of a silicon nitride oxide film.
[0071]
As shown in FIG. 5I, a second doped polycrystalline silicon layer 78 is deposited thinly (on the order of 100 nm) on the substrate surface, anisotropic etching is performed, and the first doped polycrystalline silicon layers 75a and 75b are formed. Leave as a sidewall on the outer periphery. In the cell portion, since the interval between the first doped polycrystalline silicon layers 75a is narrow, the space between the first doped silicon layers 75a is completely filled with the second doped polycrystalline silicon as shown in FIG. In the peripheral contact region 75b, a sidewall is formed. Second doped polycrystalline silicon layer 78 serves as a counter electrode in the memory cell region.
[0072]
The steps up to here are described in the column of Examples in Japanese Patent Application No. 8-293593. Next, the auxiliary substrate described in the above embodiment is attached to the upper surface to form an interlayer insulating layer.
[0073]
As shown in FIG. 6J, a contact hole 81 is formed in the insulating layer 80 attached on the substrate surface. In the peripheral contact region, the silicon nitride layer 76 exposed in the contact hole 81 is removed. In this manner, the counter electrode 78 is exposed in the memory cell region, and the extraction electrode 75b is exposed in the peripheral contact region.
[0074]
Thereafter, a wiring layer 82 of aluminum or the like is formed on the wiring layer 80 and patterned to form an upper wiring layer. Note that 83 remains hollow.
[0075]
If necessary, the surface of the upper wiring layer 82 is further flattened to form an interlayer insulating layer and an upper wiring layer.
[0076]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, a Cu layer may be used as the wiring layer instead of the Al layer. When a Cu layer is used, it is preferable to use a barrier metal serving as a Cu diffusion barrier in the lower layer. Since the side wall of the Cu wiring is isolated by the air gap, the problem of Cu diffusion in the side wall portion does not occur.
[0077]
It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.
[0078]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the parasitic capacitance between wirings as compared with the case of dielectric separation by isolating adjacent wirings with a cavity. For example, the parasitic capacitance is about 1/3 as compared with the case where a silicon oxide insulator is used.
[0079]
By disposing an insulating layer having a flat surface on a large number of wiring structures whose upper surfaces are adjusted to the same level, formation of the upper layer wiring is facilitated. The formation of such a wiring layer can be realized by, for example, an auxiliary substrate laminating step and a supporting substrate removing step, which simplifies the process. In addition, extremely excellent flatness can be obtained by bonding a flat insulating layer.
[0080]
Manufacturing costs can be reduced by using a highly versatile auxiliary base.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.
2A and 2B are a cross-sectional view and a bottom view schematically showing a configuration of a multilayer wiring semiconductor device according to an embodiment of the present invention.
FIGS. 3A and 3B are a plan view and a cross-sectional view showing a configuration of a semiconductor wafer according to an embodiment of the present invention and semiconductor chips therein. FIGS.
FIG. 4 is a cross-sectional view for explaining a manufacturing process of a DRAM according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view for explaining a manufacturing process of a DRAM according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a DRAM according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view for explaining an example of the prior art.
FIG. 8 is a cross-sectional view for explaining an example of the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st wiring structure 3 Support substrate 4 Insulating layer 5 Adhesive layer 6 Auxiliary base 7 Cavity 11 Semiconductor substrate 12 1st wiring layer 21 Interlayer insulating layer 22 2nd wiring layer 31 Interlayer insulating layer 32 3rd wiring layer 41 Insulation Layers 23, 33, 34 Contact hole 53 Scribe region 54 Scribe line 61 Semiconductor substrate 62 Field insulating film 63 Insulated gate electrode 65, 66 Impurity doped region 67 Insulating film 71 Embedded electrode 72 Bit line 73 Insulating film 75 First doped polycrystal Silicon 77 Capacitor insulating film 78 Second doped polycrystalline silicon layer 80 Interlayer insulating layer 82 Upper wiring layer

Claims (5)

A semiconductor chip having a device structure;
A plurality of wiring structures formed on the semiconductor chip, having an upper surface at the same level and separated from each other by a gap;
The reaching side surfaces of the semiconductor chip periphery in the semiconductor chip periphery are formed in a loop shape, and the seal member having a top surface of the plurality of wiring structure and the same level,
An insulating film affixed on the upper surface of the wiring structure and the entire upper surface of the seal member;
I have a,
A semiconductor device in which an outer periphery of the semiconductor chip is hermetically sealed by the sealing member and the insulating film .   The semiconductor device according to claim 1, wherein a plurality of sets of the wiring structure, the seal member, and the insulating film are laminated. Forming a plurality of wiring structures having a top surface at the same level and separated by air gaps on a semiconductor chip having a device structure of a semiconductor substrate including a plurality of semiconductor chips;
Forming a sealing member having a loop-like planar shape on the periphery of the semiconductor chip of the semiconductor substrate and including a scribe line between the upper surface of the multiple wiring structures at the same level;
A planarization step of attaching an insulating film on the upper surface of the plurality of wiring structures and on the entire upper surface of the seal member, and forming a gap between adjacent wiring structures;
Cutting the semiconductor substrate along the scribe line on the seal member to form a semiconductor chip in which the outer periphery of the semiconductor chip is hermetically sealed by the seal member and the insulating film ;
A method of manufacturing a semiconductor device including: The planarization step comprises:
Preparing an auxiliary substrate having an insulating film on a support substrate;
Pasting the auxiliary base insulating film on the upper surface of the first wiring structure on the semiconductor substrate;
The method for manufacturing a semiconductor device according to claim 3, further comprising a step of selectively removing the support substrate of the auxiliary base.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the auxiliary substrate has an adhesive layer on the insulating film, and the step of attaching the insulating film uses the adhesive layer.

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