JPH11195764A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent separation of an attached pattern and to improve manufacturing yield rate by forming a stacked-type capacitor, which is not used in the constitution of an integrated circuit, on the surface of an insulating film on a semiconductor substrate, and connecting the capacitor to the lower-layer material formed at the lower layer than the capacitor through a contact hole provided at the insulating film. SOLUTION: A field oxide film 2 is selectively formed on the surface of a P-conducting type silicon substrate 1. On the silicon substrate 1, a gate electrode 3 is formed via a gate oxide film. On this field oxide film 2 and the gate electrode 3, N-conducting type diffused layers, that is to say, a capacity diffusing layer 4 and a diffusing layer 5 for a bit line, are formed in self- alignedly. Then, the entire surface is covered with an insulating film between silicon oxide layers, and a contact hole 7 for capacity is formed. A lower electrode 8 of a stacked-type capacitor fills a hole 7 for capacity and is connected to the diffused layer 4 for capacity. A part of an attaching pattern 10 fills an attaching contact hole 9 so as to be formed, in contact with the surface of the silicon substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a structure of an accessory pattern formed together with a capacitor having a stack structure.

[0002]

2. Description of the Related Art Among semiconductor memory devices, there is a DRAM capable of arbitrarily inputting and outputting stored information. Where D
The memory cell of the RAM, which includes one transfer transistor and one capacitor, is structurally simple, and is widely used as the most suitable for high integration of a semiconductor memory device.

In such a memory cell capacitor,
With further increase in the degree of integration of semiconductor devices, those having a three-dimensional structure have been developed and used. The three-dimensional structure of the capacitor is based on the following reasons. 2. Description of the Related Art With miniaturization and higher density of semiconductor elements, it is essential to reduce the area occupied by capacitors. However, in order to ensure stable operation and reliability of the DRAM, a capacitance value equal to or more than a certain value is required.
Therefore, it is necessary to change the electrode of the capacitor from a planar structure to a three-dimensional structure, and to increase the surface area of the capacitor electrode within the reduced occupied area.

As a capacitor having a three-dimensional structure of a memory cell of the DRAM, a stack type capacitor is widely used. The stack type has high resistance to the incidence of alpha rays or noise from circuits and the like, and operates stably even when the capacitance value is relatively small. For this reason, a 4 gigabit D, in which the design standard of the semiconductor element is about
This stacked capacitor (hereinafter, referred to as a stacked capacitor) is considered to be effective also in the RAM.

In order to further increase the effective surface area of the capacitor electrode, this stacked capacitor has a fin structure, a cylinder structure or an HSG (Hem).
A device using an isotropical grained (Si) technology (hereinafter, referred to as an HSG structure) has been proposed.

When actually manufacturing a semiconductor device in which such a stacked capacitor is arranged, it is necessary to form other patterns on the semiconductor substrate in addition to the electrode pattern of the capacitor in the same manufacturing process. become. Such patterns include, for example, transfer patterns such as alignment marks of a wafer, calipers for overlay measurement, box marks for automatic overlay measurement, or marks for mask dimension measurement required in a photolithography process. Hereinafter, the pattern of the alignment mark or the like as described above is referred to as an attached pattern or particularly a structure. Such a structure does not constitute an integrated circuit of a semiconductor device.

[0007] Hereinafter, in the case where the stacked capacitor has a fin structure, formation of the capacitor electrode and the attached pattern in the prior art will be outlined in the order of the manufacturing process. 10 and 11 are cross-sectional views of a memory cell and an attached pattern in a semiconductor device in the order of the manufacturing process.

As shown in FIG. 10A, for example, a field oxide film 102 is selectively formed on a surface of a silicon substrate 101 having a P-type conductivity. And the silicon substrate 1
A gate electrode 103 is formed on gate oxide film 01 via gate oxide film.
At 03, a diffusion layer of N-type conductivity is formed in a self-aligned manner (self-aligned). In this manner, the capacitance diffusion layer 1
04 and the bit line diffusion layer 105 are formed. Then, the entire surface is covered with the interlayer insulating film 106. Here, the interlayer insulating film 106 is a silicon oxide film.

Next, as shown in FIG. 10B, a spacer 107 is formed by laminating on the interlayer insulating film 106. Here, the spacer 107 is formed of a BPSG film (a silicon oxide film containing boron glass and phosphorus glass). Then, as shown in FIG. 10C, a capacitor contact hole 108 is formed in the interlayer insulating film 106 and the spacer 107 by a photolithography technique and a dry etching technique. Here, the capacity contact hole 108 is formed in the capacity diffusion layer 1.
04 has been reached.

Next, as shown in FIG. 11A, a lower electrode 109 of the stacked capacitor is formed on the spacer 107. Here, this lower electrode 109 is made of polycrystalline silicon containing phosphorus or arsenic impurities. A part thereof is formed in the above-mentioned capacity contact hole 10.
8 and connected to the capacity diffusion layer 104.

In this step, the accessory patterns 110 such as alignment marks are formed on the spacers 107 in the same manner as described above. Here, the attached pattern 110 is an isolated pattern.

Next, in order to form the lower electrode 109 into a fin structure, the spacer 107 is selectively etched away. Here, for example, anhydrous hydrogen fluoride gas is used as the etchant. Thus, FIG.
As shown in FIG. 7, a gap is formed between the lower electrode 109 of the capacitor and the interlayer insulating film 106. However, in this process,
The attached pattern 110 is peeled off from the interlayer insulating film 106.

Then, as shown in FIG. 11C, a capacitance insulating film 111 is formed on the exposed surface of the lower electrode 109, and the upper electrode 1 is formed so as to cover the capacitance insulating film 111.
12 are formed. The upper electrode 112 is formed on the entire surface and serves as a cell plate of a capacitor.

[0014]

In the prior art as described above, in the process of forming the lower electrode of the stacked capacitor, for example, a registration mark of a wafer, a vernier caliper for overlay measurement, a box mark for automatic overlay measurement. Alternatively, an attached pattern which is a transfer pattern such as a mask dimension measurement mark is peeled off from the interlayer insulating film 106.

Then, the attached pattern cannot be removed in the cleaning step or the like in the manufacturing process of the semiconductor device, and as shown in FIG. 11C, it comes into contact with the lower electrode 109 of the stacked capacitor. Such contact is made with the lower electrode 1
09 short circuit. In addition, the attached pattern that peels off in this manner also serves as a particle source. Then, the production yield of the semiconductor device is significantly reduced.

In the case of forming a stacked capacitor, such a phenomenon is not limited to the fin structure, but occurs to some extent not only in the cylinder structure or the HSG structure.

An object of the present invention is to completely prevent the attached pattern from peeling off in the step of forming a pattern for an integrated circuit such as a stacked capacitor, and to greatly improve the production yield of semiconductor devices.

[0018]

For this purpose, in the semiconductor device of the present invention, the surface of an insulating film formed on a semiconductor substrate is
A structure not used in the configuration of the integrated circuit of the semiconductor device is formed, and the structure is connected to a lower layer material formed below the structure through a contact hole provided in the insulating film. The structure is made of the same material as the lower electrode of the stacked capacitor and in the same process.

Here, the structure and the lower electrode of the stacked capacitor are formed in a fin structure, a cylinder structure or an HSG structure. Alternatively, the lower electrode of the stacked capacitor is formed in a cylinder structure, and the structure serves as an inner box mark pattern for automatic overlay measurement. The lower layer material is the semiconductor substrate.

Alternatively, the structure is a transfer pattern such as a registration mark of a wafer, a caliper for overlay measurement, a box mark for automatic overlay measurement, or a mark for mask dimension measurement.

Thus, the alignment mark of the wafer
Attached patterns such as patterns, calipers for overlay measurement, box marks for automatic overlay measurement or marks for mask dimension measurement are firmly connected to the underlying material,
In the manufacturing process of the semiconductor device, such an attached pattern does not peel off at all.

[0022]

Next, a first embodiment of the present invention will be described with reference to FIG. Here, FIG. 1 is a sectional view of a memory cell and an attached pattern of the present invention.

As shown in FIG. 1, a field oxide film 2 is selectively formed on the surface of a silicon substrate 1 having a P-type conductivity. Then, a gate electrode 3 is formed on the silicon substrate 1 via a gate oxide film.
In addition, a diffusion layer of N-type conductivity is formed in the gate electrode 3 in a self-aligned manner. That is, the diffusion layer 4 for the capacitor and the diffusion layer 5 for the bit line are formed.

The entire surface is covered with an interlayer insulating film 6. Here, the interlayer insulating film 6 is a silicon oxide film.
Then, a capacity contact hole 7 is formed in the interlayer insulating film 6, and the lower electrode 8 of the stacked capacitor is formed so as to fill the capacity contact hole 7 and connect to the capacity diffusion layer 4. Here, the lower electrode 8 is made of polycrystalline silicon containing phosphorus or arsenic impurities.

The interlayer insulating film 6 and the field oxide film 2
Is formed so as to penetrate through the hole and reach the surface of the silicon substrate 1, and the auxiliary pattern 10 is formed so as to fill the auxiliary contact hole 9 with a part thereof and further contact the surface of the silicon substrate 1 as a lower layer material. ing.

Then, the lower electrode 8 and the attached pattern 1
The capacitor insulating film 11 is formed on the exposed surface of the zero, and the upper electrode 12 is formed so as to cover the capacitor insulating film 11. The upper electrode 12 is formed on the entire surface and serves as a cell plate of a stacked capacitor.

As described above, the present invention is characterized in that, for example, a wafer alignment mark, an overlay measurement vernier caliper, an automatic overlay measurement box mark, or a mask formed simultaneously in the process of forming the lower electrode of the capacitor. An additional pattern, which is a transfer pattern such as a mark for dimension measurement, is formed so as to fill the above-mentioned additional contact hole 9 formed simultaneously with the contact hole for capacitance.

Due to such a structure, there is no peeling of the attached pattern as occurred in the prior art.

Next, an attached pattern formed as described above with reference to FIG. 2, specifically, a pattern of a registration mark of a wafer will be described with a plan view. Here, FIG. 2A is a plan view of the present invention, and FIG. 2B is a plan view of a conventional technique for comparison.

As shown in FIG. 2A, in the present invention, a plurality of registration mark patterns 13 are arranged at a constant interval. Here, this registration mark pattern 1
3 is formed simultaneously with the lower electrode 8 of the capacitor described with reference to FIG. And this alignment mark pattern 1
As described with reference to FIG. 1, reference numeral 3 is connected to the pile pillar (filler) 14 filled in the interlayer insulating film. Thus, the registration mark pattern 13 is firmly fixed. And in the manufacturing process,
The pattern 13 does not peel off at all.

On the other hand, in the prior art, FIG.
As shown in (b), the registration mark pattern 13a
Is merely formed on the interlayer insulating film. That is, it is not fixed by the pillar as in the present invention. For this reason, it is easily peeled off in a cleaning step or the like.

Next, a method of forming the lower electrode and the auxiliary pattern of the capacitor having the structure described with reference to FIG. 3 and 4 are cross-sectional views of the memory cell and the attached pattern in the semiconductor device in the order of the manufacturing process.

As shown in FIG. 3A, a field oxide film 2 is selectively formed on the surface of a silicon substrate 1 having a P-type conductivity, for example, as described in the prior art. Then, a gate electrode 3 is formed on the silicon substrate 1 with a gate oxide film interposed therebetween, and a diffusion layer 4 for capacitance and a diffusion layer 5 for bit lines having N-type conductivity are formed. Then, the entire surface is covered with the interlayer insulating film 6. Here, the interlayer insulating film 6 is a laminated film of a BPSG film having a thickness of about 1 μm and a silicon oxide film.

Next, as shown in FIG. 3B, a spacer 15 is formed by laminating the interlayer insulating film 6. Here, the spacer 7 is formed of a BPSG film having a thickness of about 300 nm. Then, as shown in FIG. 3C, the interlayer insulating film 6 is formed by photolithography and dry etching.
Then, the capacitor contact hole 7 is formed in the spacer 15.
Here, the capacity contact hole 7 reaches the upper part of the capacity diffusion layer 4.

In the step of forming the capacitor contact hole 7, the contact hole 9 for attachment is formed in the spacer 15, the interlayer insulating film 6, and the field oxide film 2 at the same time. Here, the accessory contact hole 9 reaches the surface of the silicon substrate 1.

Next, as shown in FIG. 4A, the lower electrode 8 of the stacked capacitor is formed on the spacer 15. Here, the lower electrode 8 is made of polycrystalline silicon containing phosphorus or arsenic impurities. And
A part thereof is filled in the capacitor contact hole 7 and connected to the capacitor diffusion layer 4.

In this step, the accessory pattern 10 is similarly formed on the spacer 15. Here, the attached pattern 10 is an isolated pattern. The accessory pattern 10 is also made of polycrystalline silicon containing phosphorus or arsenic impurities, and part of the accessory pattern 10 is filled in the accessory contact hole 9 and connected to the silicon substrate 1. The portion of the accessory pattern 10 filled in the accessory contact hole 9 corresponds to the pillar 14 described in FIG.

Next, in order to form the lower electrode 8 into a fin structure, the spacer 15 is selectively etched away. Here, anhydrous hydrogen fluoride gas is used for the etchant as described in the related art. In this manner, as shown in FIG.
A gap is formed between the semiconductor device and the interlayer insulating film 6. Similarly, in this step, a gap is generated between the attached pattern 10 and the interlayer insulating film 6.

Thereafter, as described with reference to FIG.
And a capacitor insulating film 1 on the exposed surface of the attached pattern 10.
1 is formed, and an upper electrode 12 is formed so as to cover the capacitance insulating film 11. Then, the upper electrode 12 is formed on the entire surface to form a cell plate of the capacitor.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the attachment pattern 10 is fixed to a lower layer material different from that described in the first embodiment. However, the rest is the same as the first embodiment. Hereinafter, the points different from the first embodiment will be mainly described. Here, FIG. 5 is a sectional view of the memory cell and the attached pattern of the present invention.

As shown in FIG. 5, the lower electrode 8 of the memory cell portion is formed so as to be connected to the capacitor diffusion layer 4. And
The attached pattern 10 is connected to a word wiring 16 which is a lower layer material formed on the field oxide film 2. here,
The word wiring 16 is a pattern formed simultaneously with the gate electrode 3. Then, as shown in FIG. 5, the accessory pattern 10 of the present invention is formed so that the accessory contact hole 9a which is the word wiring 16 and is formed in the interlayer insulating film 6 is partially filled. Become.

Next, a third embodiment of the present invention will be described with reference to FIG. In this embodiment, the lower electrode of the stacked capacitor is formed in a normal stacked type. Hereinafter, the same components described in the first embodiment will be described with the same reference numerals. Here, FIG. 6A is a cross-sectional view of one memory cell and the attached pattern of the present invention. FIG. 6B is a cross-sectional view of a conventional technique for comparison. As shown in FIG. 6A, a field oxide film 2 is selectively formed on the surface of a silicon substrate 1. And
A gate electrode 3 is formed on a silicon substrate 1 with a gate oxide film 17 interposed therebetween. A diffusion layer 4 for a capacitor and a diffusion layer 5 for a bit line are formed on the field oxide film 2 and the gate electrode 3 in a self-aligned manner. I have.

Then, the entire surface is covered with the interlayer insulating film 6. Here, the interlayer insulating film 6 is an insulating film in which a BPSG film and a silicon oxide film are laminated. Then, a protective insulating film 18 is formed on the interlayer insulating film 6. Here, the protective insulating film 18 is a silicon oxide film having a thickness of about 200 nm.

Then, the interlayer insulating film 6 and the protective insulating film 1
And a lower electrode 8 of the stacked capacitor connected to the capacitance diffusion layer 4 through the capacitance contact hole 7 provided in the capacitor 8.
a is formed.

An auxiliary contact hole 9 is formed through the protective insulating film 18, the interlayer insulating film 6 and the field oxide film 2 to reach the surface of the silicon substrate 1.
0a is formed so as to fill the contact hole 9 for attachment with a part thereof and further contact the surface of the silicon substrate 1.

On the other hand, in the prior art, as shown in FIG. 6B, the lower electrode 8a of the stacked capacitor is formed on the protective insulating film 18 and at the same time,
The attached pattern 20 is formed on the upper surface 8. However, in this case, the accessory contact hole 9 is not formed unlike the present invention. That is, the attached pattern 20 is not connected to the silicon substrate 1 and remains deposited on the protective insulating film 18.

In the manufacturing process of such a laminated lower electrode, a side etch portion 19 is formed on the protective insulating film 18 at the bottom of the lower electrode 8a or the attached patterns 10a and 20. In the conventional technique, the side pattern 19 formed in such a manufacturing process causes the attached pattern 20 to be peeled in a subsequent cleaning process or the like. In particular, when the semiconductor device is miniaturized, the lateral dimension of the lower electrode 8a or the attached pattern 20 becomes fine, and the height dimension becomes large. Then, the lower electrode 8a or the attached pattern 20
Is increased. For this reason, peeling due to the formation of the side etch portions 19 frequently occurs.

On the other hand, in the present invention, since the attached pattern 10a is firmly fixed as shown in FIG. 6 (a), there is no peeling of the attached pattern 10a as described above. Become.

Thereafter, in the formation of the stacked capacitor,
As described in the first embodiment, the capacitance insulating film 11 is formed on the exposed surfaces of the lower electrode 8a and the attached pattern 10a.
Is formed, and an upper electrode 12 is formed so as to cover this capacitance insulating film 11. Then, the upper electrode 12 is formed on the entire surface to form a cell plate of the capacitor.

Next, a fourth embodiment of the present invention will be described with reference to FIG. This embodiment is the same as that described in the third embodiment except that the lower electrode of the stacked capacitor is formed in a normal cylinder structure. Hereinafter, differences from the third embodiment will be mainly described.

As shown in FIG. 7A, a lower electrode 8b having a cylinder structure is formed, which is connected to the capacitance diffusion layer 4 through a capacitance contact hole provided in the interlayer insulating film 6 and the protective insulating film 18. I have. Further, an auxiliary pattern 10b having a cylinder structure is formed so as to be in contact with the surface of the silicon substrate 1 through an auxiliary contact hole penetrating through the protective insulating film 18, the interlayer insulating film 6, and the field oxide film 2 and reaching the surface of the silicon substrate 1. .

On the other hand, in the prior art, as shown in FIG. 7B, a lower electrode 8b having a cylinder structure is formed on the protective insulating film 18, and at the same time, a cylinder-structured lower electrode 8b is formed on the protective insulating film 18. The pattern 20a is formed.

Also in this case, in the conventional technique, the side-etched portion 19 is formed in the manufacturing process, so that the attached pattern 20a is formed.
However, in the present invention, since the attached pattern 10a is firmly fixed as shown in FIG. 7A, there is no detachment of the attached pattern 10b.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. The fifth embodiment is a case where the present invention is applied to pattern formation of a box mark for automatic overlay measurement. Here, FIG.
It is a top view of the pattern of the box mark for automatic overlay measurement, and FIG. 9 is sectional drawing of the pattern of the box mark for automatic overlay measurement in order of the manufacturing process. Here, FIG. 9 is a cross section cut along AB shown in FIG.

As shown in FIG. 8, an outer box mark pattern 21 for automatic overlay measurement is formed. An inner box mark pattern 22 for automatic overlay measurement is formed inside the outer box mark pattern 21. Here, the inner box mark pattern 22 is constituted by a large number of divided patterns.

That is, the cylinder pattern 24 is formed on the side wall of the slit-like groove 23 provided in the insulating film. Then, the same pile column 25 as described in FIG.
It is formed connected to each of the cylinder patterns 24. The inner box mark pattern 22 for automatic overlay measurement is formed by such a cylinder pattern.

Such a pattern of the box mark for automatic overlay measurement is formed as shown in FIG.

As shown in FIG. 9A, the silicon substrate 2
An interlayer insulating film 27 made of a silicon oxide film is formed on 6. Then, an outer box mark pattern 21 is formed in a predetermined region of the interlayer insulating film 27. Then, similarly, a pillar 25 is formed in a region located inside the outer box mark pattern 21. Here, the outer box mark pattern 21 and the pillar 25 are made of polycrystalline silicon filled in a predetermined region of the interlayer insulating film 27.

Next, a protective insulating film 28 and a pattern forming insulating film 29 are stacked and deposited. Here, the protective insulating film 2
Reference numeral 8 denotes a silicon nitride film having a thickness of about 50 nm, and the pattern forming insulating film 29 is a silicon oxide film having a thickness of about 500 nm. Then, the slit-shaped groove 23 is formed in the pattern forming insulating film 29 and the protective insulating film 28. Here, the pattern width of the slit-like groove 23 is about 400 nm.

Next, as shown in FIG. 9B, a polycrystalline silicon thin film 30 is deposited on the entire surface. And SOG
A (spin-on-glass) film 31 is filled in the slit-like groove 23.

Next, as shown in FIG. 9C, the polycrystalline silicon thin film 30 on the surface of the pattern forming insulating film 29 is polished and removed by a chemical mechanical polishing (CMP) method. Thus, the cylinder pattern 24 is formed. Then, the pattern forming insulating film 29 and the SOG film 31 are removed by etching.

In this way, as shown in FIG. 9D, the outer box mark pattern 21 for automatic overlay measurement is formed in a predetermined region of the interlayer insulating film 27 on the silicon substrate 26, and , Cylinder pattern 24
Are formed inside the outer box mark pattern 21 and connected to the pillar 25.

In this manner, the inner box mark pattern 22 for automatic overlay measurement is divided into cylinder patterns 24, and the divided cylinder patterns 24 are fixed to the silicon substrate 26 by the pillars 25. .

Then, the inner box mark pattern 22 for automatic overlay measurement does not peel off in the manufacturing process.

In the above embodiment, the case where the attached pattern, that is, the structure is formed in the same step as the formation of the base electrode of the stacked capacitor has been described. The present invention is not limited to this. The present invention can be similarly applied to accessory patterns formed in the same step as the other circuit pattern formation of the semiconductor device.

In the above embodiment, the case where the attached pattern is fixed to the silicon substrate or the word wiring as the base material through the pillar is described. The present invention is not limited to this, and may be any solid lower layer material formed below the accessory pattern. For example, it may be connected to a lower layer material such as a bit wiring.

The present invention is similarly applicable to the case where such an attached pattern is various test patterns such as a resolution check pattern or a short circuit check pattern.

[0068]

According to the semiconductor device of the present invention, on the surface of an insulating film formed on a semiconductor substrate, a structure not used for forming an integrated circuit of the semiconductor device, that is, a registration mark / pattern of a wafer and overlay measurement. Attached patterns such as calipers, box marks for automatic overlay measurement or marks for mask dimension measurement are connected to a lower layer material formed below this structure through a strong pile pillar provided in the insulating film. I have. Here, a semiconductor substrate, wiring, or the like is used as such a lower layer material. Such a structure is formed of a fin structure, a cylinder structure, or an HSG structure using the same material as the lower electrode of the stacked capacitor and in the same process.

In this way, in the manufacturing process of the semiconductor device, an attached pattern such as a wafer alignment mark, an overlay measurement caliper, an automatic overlay measurement box mark or a mask dimension measurement mark is transferred from the semiconductor substrate. There will be no peeling. As described above, the attached pattern does not become a particle source unlike the related art, and the manufacturing yield of the semiconductor device is greatly improved.

As described above, the present invention further promotes ultra-high integration and high density of a semiconductor device such as a DRAM.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a memory cell portion and an attached pattern for describing a first embodiment of the present invention.

FIG. 2 is a plan view of an attached pattern for explaining the first embodiment of the present invention.

FIG. 3 is a sectional view in the order of the manufacturing process for describing the embodiment.

FIG. 4 is a cross-sectional view in the order of manufacturing steps for describing the embodiment.

FIG. 5 is a cross-sectional view of a memory cell part and an attached pattern for describing a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a memory cell portion and an attached pattern for explaining a third embodiment of the present invention.

FIG. 7 is a cross-sectional view of a memory cell part and an attached pattern for explaining a fourth embodiment of the present invention.

FIG. 8 is a plan view of an attached pattern for explaining a fifth embodiment of the present invention.

FIG. 9 is a cross-sectional view of the accessory pattern in the order of manufacturing steps.

FIG. 10 is a cross-sectional view of a memory cell portion and an attached pattern in order of a manufacturing process for explaining a conventional technique.

FIG. 11 is a sectional view of a memory cell portion and an attached pattern in order of a manufacturing process for explaining a conventional technique.

[Explanation of symbols]

1,26,101 Silicon substrate 2,102 Field oxide film 3,103 Gate electrode 4,104 Diffusion layer for capacitor 5,105 Diffusion layer for bit line 6,27,106 Interlayer insulating film 7,108 Capacitance contact hole 8, 8a, 8b, 109 Lower electrode 9, 9a Attachment contact hole 10, 10a, 10b, 20, 20a, 110 Attachment pattern 11, 111 Capacitive insulating film 12, 112 Upper electrode 13, 13a Registration mark pattern 14, 25 Pile Pillar 15, 107 Spacer 16 Word line 17 Gate oxide film 18, 28 Protective insulating film 19 Side etch portion 21 Outer box mark pattern 22 Inner box mark pattern 23 Slit groove 24 Cylinder pattern 29 Pattern forming insulating film 30 Polycrystalline Silicon thin film 31 SOG film

Claims (6)

[Claims] A structure not used for forming an integrated circuit of a semiconductor device is formed on a surface of an insulating film formed on a semiconductor substrate, and the structure is formed through a contact hole provided in the insulating film. A semiconductor device which is connected to a lower layer material formed below a structure. 2. The semiconductor device according to claim 1, wherein the structure is made of the same material as the lower electrode of the stacked capacitor and formed in the same step. 3. The structure and the lower electrode of the stack type capacitor have a fin structure, a cylinder structure, or an H type.
3. The semiconductor device according to claim 2, wherein the semiconductor device is formed in an SG structure. 4. The semiconductor device according to claim 2, wherein the lower electrode of the stacked capacitor is formed in a cylinder structure, and the structure has an inner box mark pattern for automatic overlay measurement. . 5. The semiconductor device according to claim 1, wherein said lower layer material is said semiconductor substrate. 6. The structure according to claim 1, wherein the structure is a transfer pattern such as a wafer alignment mark, an overlay measurement caliper, an automatic overlay measurement box mark, or a mask dimension measurement mark. Claim 2,
The semiconductor device according to claim 3.