JPH10247638A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device by preventing an electrification damage due to plasma. SOLUTION: In a manufacturing method, a conductive material layer 13 is formed on a substrate 10 where a conductive part (gate insulation film) 11 is formed to have a continuity with a conductive part, an insulation film 14 is formed on the conductive material layer 13, a resist pattern 15 is formed on the insulation film 14, a resist pattern 15 is formed on the insulation film 14, the insulation film 14 is etched by the resist pattern 15, and at the same time the conductive material layer 13 is etched and an insulation pattern 16 and a conductive pattern (gate electrode) 17 are formed. Then, with the insulation pattern and the conductive pattern left, the resist pattern 15 is subjected to ashing elimination by the plasma method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device, which prevents the occurrence of charge damage due to plasma when ashing a resist pattern.

[0002]

2. Description of the Related Art In the manufacturing process of semiconductor devices, there are many processes using plasma. For example, in manufacturing a MOS transistor, when the gate electrode 1 is processed as shown in FIG. 4, oxygen plasma P is used for ashing the resist pattern 2 used as a mask at the time of etching. At this time, in the field region F of the silicon substrate 3, when the area of the gate electrode 1 on the field oxide film 4 is significantly larger than the area of the gate electrode 1 on the active region A, charging by plasma causes an arrow in FIG. A current flows through the gate insulating film 5 as shown by.

[0003] Then, dielectric breakdown, generation of fixed charges in the gate insulating film 5, and the like, which are called plasma damage, are caused. As a result, device yield and reliability are reduced. Such a phenomenon occurs because charged particles are incident on the entire area exposed to the plasma, and the current is concentrated on a place where the current flows most easily, here, the gate insulating film 5. Therefore, as a countermeasure in the related art, a design is made so that the ratio, which is called an antenna ratio, between the area of the gate electrode 1 on the field region F and the area of the gate electrode 1 on the active region A does not increase. And so on.

[0004] A similar problem occurs in other processes using plasma. For example, as shown in FIG. 5, when processing the Al wiring 6, when this is electrically connected to the gate electrode 8 through the contact 7, A
If the area of the l-wiring 6 is large, when the resist pattern (not shown) used for forming the Al wiring 6 is ashed with oxygen plasma, charged particles from the plasma damage the gate electrode 8 and the gate insulating film 9 by plasma. It will be done. Such a phenomenon occurs not only when processing the Al wiring 6 connected to the gate electrode 8 but also when processing the wiring connected to the well, source, and drain.
Again, when the area of the wiring is large, it is similarly affected by the charging, and plasma damage is caused.

However, the wiring is often long because it is used for propagation delay and connection with other elements, and it is practically difficult to design a pattern in which the antenna ratio is kept within a constant value for all transistors. For this reason, in the prior art, the transistor is actually manufactured while allowing a certain degree of plasma damage.

[0006]

However, since the antenna ratio depends on the process to be employed and the gate film thickness during the processing of the gate electrode, the antenna ratio is designed so as not to cause plasma damage. There is a problem that cannot be done. Also, during processing of a wiring connected to a gate electrode, a well, a source, and a drain, the threshold voltage (Vth) varies due to plasma damage, and this is particularly applied to the manufacture of a MOS analog circuit. In such a case, the fixed pattern noise increases, which also causes a reduction in the operating power supply voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which charging damage due to plasma is prevented.

[0008]

Means for Solving the Problems Claim 1 of the present invention
The method of manufacturing a semiconductor device according to the above, further comprising: forming a conductive material layer on the base on which the conductive portion is formed, in a state of being electrically connected to the conductive portion; forming an insulating film on the conductive material layer; A step of forming a resist pattern on the insulating film, a step of etching the insulating film using the resist pattern, and a step of etching the conductive material layer to form an insulating pattern and a conductive pattern; Ashing and removing the resist pattern by a plasma method while leaving the conductive pattern,
The present invention is a means for solving the above problem.

According to this manufacturing method, after the insulating film and the conductive material layer are etched, the resist pattern is removed by ashing with the plasma method in a state where the insulating pattern is left on the conductive pattern. The charged particles hardly flow through the conductive pattern only by staying on the surface of the insulating pattern and charging the insulating pattern positively or negatively. Therefore, the amount of current flowing through the conductive pattern is extremely small as compared with the related art, so that damage to a conductive portion, for example, a gate insulating film can be minimized.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a conductive material layer on a base on which a conductive portion is formed so as to be electrically connected to the conductive portion; and forming a resist pattern on the conductive material layer. Forming, etching the conductive material layer using the resist pattern, a first conductive pattern that is not conductive to the conductive portion, and conductive to the conductive portion, and an area smaller than the first conductive pattern A step of forming a second conductive pattern, a step of removing the resist pattern by ashing by a plasma method, and a step of forming an insulating film covering the first conductive pattern and the second conductive pattern, Forming a conductive pattern for electrically connecting the first conductive pattern and the second conductive pattern on the insulating film.

According to this manufacturing method, the conductive material layer is etched, and the first conductive pattern which does not conduct to the conductive portion;
After forming a second conductive pattern having an area smaller than the first conductive pattern, the resist pattern is removed by ashing by a plasma method, so that the first conductive pattern is removed from the plasma during ashing. Although charged particles are incident on the second conductive pattern, respectively, the first conductive pattern having a large area is not electrically connected to the conductive part, so that the conductive part is not damaged by plasma, and the second conductive pattern is electrically connected to the conductive part. In the conductive pattern (2), since the area is small, plasma damage can be suppressed low. Then, after the ashing, the first conductive pattern and the second conductive pattern are brought into conduction, so that the conductive pattern obtained therefrom has a sufficient area (length).

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail. FIGS. 1A to 1C show a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 2 is a diagram showing an example of an embodiment when applied to processing of a gate electrode in a transistor.
Is a substrate. The base 10 is made of a semiconductor substrate such as a wafer, and has various semiconductor components formed thereon, for example, a gate insulating film 11 serving as a conductive portion in the present invention, a field oxide film 12, and the like.

In this embodiment, first, an impurity-containing polysilicon film is formed on a substrate 10 by a CVD method or the like, and a conductive material layer 13 electrically connected to a gate insulating film 11 as shown in FIG. To form Subsequently, an insulating material, for example, SiO ₂ is formed to a thickness of about 50 nm by LP-CVD, and an insulating film 14 is formed so as to cover the conductive material layer 13.

Next, a resist is applied on the insulating film 14 to form a resist layer (not shown), and the resist layer is patterned by a known lithography method, and a resist pattern 15 is formed as shown in FIG. Form. Then
Using the resist pattern 15 as a mask, the insulating film 1 is used.
4 is etched under normal conditions, and then the conductive material layer 13 is also etched under normal conditions using the same resist pattern 15 as a mask to form an insulating pattern 16 comprising an insulating film 14 and a gate electrode comprising the conductive material layer 13. (Conductive pattern) 17 is formed. Thereafter, while the insulating pattern 16 and the gate electrode 17 are left, the resist pattern 15 is ashed by a plasma method using oxygen plasma P, and the resist pattern 15 is entirely removed as shown in FIG. I do.

When ashing is performed using oxygen plasma as described above, in the conventional example shown in FIG. 4, a plasma current flows into the entire area of the gate electrode 1 and concentrates on the gate electrode 1 on the active region A as described above. Then, the potential rises and a current flows between the silicon substrate 3 and the gate insulating film 5.
Was damaged, but in the present embodiment, FIG.
Since the insulating pattern 16 covers the upper surface of the gate electrode 17 as shown in FIG. 1, charged particles from the plasma hardly flow into the gate insulating film 11 as shown by the arrow in FIG. That is, charged particles incident from the plasma are applied to the insulating pattern 1 covering the upper surface of the gate electrode 17.
6 and only charges the insulating pattern 16 positively or negatively, and flows through the gate electrode 17 only when it enters from the side surface of the gate electrode 17 exposed without being covered with the insulating pattern 16. As a result, the amount of current flowing is extremely small as compared with the conventional case.

Therefore, in the manufacturing method of the present embodiment, the gate electrode 17 during plasma ashing is different from the conventional method.
Since the current flowing to the gate insulating film 11 can be minimized, the damage to the gate insulating film 11, that is, the charging damage due to plasma can be minimized, thereby eliminating the need to keep the antenna ratio within a certain range. The above flexibility can be increased.

In this example, the insulating film 14 is made of Si.
Although O ₂ was used, the material of the insulating film 14 is not particularly limited as long as it is an insulator. For example, a thermal oxide film obtained by thermally oxidizing polysilicon, a silicon nitride film, a silicon nitride oxide A film or the like may be used. Although the required film thickness of the insulating film 14 varies depending on the plasma conditions, when the insulating pattern 16 is charged, a current flows through the underlying gate electrode 17 to the gate insulating film 11 at that voltage, Thereby, the gate insulating film 1
It is only necessary that the thickness is such that no dielectric breakdown occurs. For example, if plasma conditions are low damage, 10
nm, and 1 if the plasma is highly damaged.
It is preferably at least 00 nm.

FIGS. 2A to 2C show an embodiment in which the method of manufacturing a semiconductor device according to claim 1 of the present invention is applied to processing of a wiring connected to a gate electrode of a MOS transistor. FIG.
Is a substrate. The base 20 is made of a semiconductor substrate such as a wafer, and includes various semiconductor components such as a gate insulating film 21 serving as a conductive portion in the present invention, a field oxide film 22, a gate electrode 23, and an interlayer covering the gate electrode 23. The insulating film 24 has a contact 25 formed in the interlayer insulating film 24 and connected to the gate electrode 23. In this example, the gate electrode 23 is made of polysilicon having a low antenna ratio.

In this embodiment, first, Al (aluminum) is formed on the interlayer insulating film 24 of the base 20 by a sputtering method or the like, and the contact 2 is formed as shown in FIG.
Then, a conductive material layer 26 electrically connected to the gate electrode 23 via the gate electrode 5 is formed. Subsequently, the P-
An insulating film 27 made of a TEOS (plasma TEOS) film is formed.

Next, in the same manner as in the example shown in FIG.
As shown in (b), a resist pattern 2 is formed on the insulating film 27.
Then, the insulating film 27 is etched using the resist pattern 28 as a mask, and the conductive material layer 26 is etched using the same resist pattern 28 as a mask. Wiring pattern (conductive pattern) composed of material layer 26
And 30 are formed. Thereafter, while the insulating pattern 29 and the wiring pattern 30 are left, the resist pattern 28 is ashed by a plasma method using oxygen plasma, and as shown in FIG.
Are all removed.

When ashing is performed using oxygen plasma as described above, the insulating pattern 29 covers the upper surface of the wiring pattern 30 as in the previous example shown in FIG.
(C) Charged particles from the plasma hardly flow into the gate insulating film 21 via the wiring pattern 30, the contact 25, and the gate electrode 23 as shown by the middle arrow.
Therefore, even in the manufacturing method according to the present embodiment, damage to the gate insulating film 21, that is, charging damage due to plasma can be suppressed to a minimum as compared with the conventional method.

In this example, after the conductive material layer 26 is formed, the insulating film 27 is formed by a P-TEOS (plasma TEOS) film. However, in this example, the gate electrode 23 is formed with a low antenna ratio. In addition, the influence of charged particles from the plasma during the film formation is also suppressed.

FIG. 3 is a diagram showing an embodiment in which the method of manufacturing a semiconductor device according to claim 2 of the present invention is applied to processing of a wiring connected to a gate electrode of a MOS transistor. Reference numeral 40 denotes a substrate.
This base 40 is also made of a semiconductor substrate such as a wafer, and like the base 20 shown in FIG.
A field oxide film 42, a gate electrode 43, an interlayer insulating film 44 covering the gate electrode 43,
Contact 4 connected to gate electrode 43 formed therein
5 and the like. Note that, also in this example, the gate electrode 43 is made of polysilicon formed with a low antenna ratio.

In this embodiment, first, Al is formed on the interlayer insulating film 44 of the base 40 by sputtering or the like.
A conductive material layer (not shown) that is electrically connected to the gate electrode 43 via the contact 45 is formed. Next, a resist pattern (not shown) is formed on the conductive material layer. Subsequently, the conductive material layer is etched using this resist pattern as a mask, and is not connected to the contact 45 as shown in FIG.
A first wiring pattern (first conductive pattern) 46 that does not conduct to 1 and a second wiring pattern (conductive to the gate electrode 43 and the gate insulating film 41 that is connected to the contact 45 and thus becomes a conductive part in the present invention) (Second conductive pattern) 47 are formed. Here, the second wiring pattern 4
7 has a sufficiently smaller area than the first wiring pattern 46, so that charged particles hardly enter from the plasma during the plasma processing described later.

Thus, the first wiring pattern 46,
After the second wiring pattern 47 is formed, the resist pattern used for patterning is ashed by a plasma method using oxygen plasma, and the resist pattern is entirely removed. When ashing is performed using oxygen plasma, the gate electrode 43 and the gate insulating film 41 are formed as described above.
Since the area of the second wiring pattern 47 that conducts to the gate electrode 41 is sufficiently reduced, almost no charged particles are incident from the plasma on the second wiring pattern 47, so that damage to the gate insulating film 41 is hardly affected.

Next, an interlayer insulating film 48 is formed so as to cover the first wiring pattern 46 and the second wiring pattern 47, and after this is flattened, the interlayer insulating film 48 is opened and the first wiring is formed. A contact hole (not shown) leading to the pattern 46 and a contact hole (not shown) leading to the second wiring pattern 47 are opened. Then, an Al film is formed on the interlayer insulating film 48, which is then buried in the contact hole by a reflow method or the like, and is electrically connected to the first wiring pattern 46 and the second wiring pattern 47, respectively.

Thereafter, a resist pattern is formed on the Al film (not shown) obtained in this manner, and etching is performed using the resist pattern as a mask.
A conductive pattern 49 for conducting between the second wiring pattern 47 and the conductive pattern 49 is formed. Then, the resist pattern used for patterning the conductive pattern 49 is ashed by a plasma method using oxygen plasma to remove all the resist pattern. The conductive pattern 49 has a sufficiently small area as in the case of the second wiring pattern 47 so that almost no charged particles from plasma enter the conductive pattern 49 during ashing of the resist pattern. I do.

In such a manufacturing method, since the area of the second wiring pattern 47 which is electrically connected to the gate electrode 43 and the gate insulating film 41 is sufficiently reduced, the second wiring pattern 47 is charged from plasma. Particles hardly enter, and therefore, damage to the gate insulating film 41 can be suppressed to such an extent that there is almost no effect. After the ashing, the first wiring pattern 46 and the second wiring pattern 4
6 is made conductive by the conductive pattern 49, so that the wiring pattern obtained from the first wiring pattern 46, the conductive pattern 49, and the second wiring pattern 46 has a sufficient area (length) similar to the wiring formed normally. ).

In the above embodiment, the present invention is applied to the case where the present invention is applied to the gate electrode 43 and the wiring contacting it (the first wiring pattern 46, the conductive pattern 49, and the second wiring pattern 4).
6 has been described, the present invention is not limited to this, and plasma damage is a problem in processing of wiring for contacting a source or drain or a well. It is applicable when it becomes. For example, when the area of the wiring made of Al or the like that is in contact with the source, drain, or well is very large and the wiring that is in contact with the gate electrode is small, the plasma current flows through the source, drain, or well, and the potential of each increases. Alternatively, the gate electrode is lowered, and as a result, the potential difference between the gate electrode and the gate electrode is increased, which also causes damage. Especially,
If the area of the wiring in contact with the drain or the source is large, the MOS transistor is turned on, a channel current flows, hot carriers are generated, and the gate insulating film may be damaged. Then
By applying the manufacturing method according to the second aspect of the present invention to such a configuration as well, charging damage due to plasma can be effectively avoided.

[0030]

As described above, in the method of manufacturing a semiconductor device according to the first aspect of the present invention, after the insulating film and the conductive material layer are etched, the resist pattern is left in a state where the insulating pattern is left on the conductive pattern. Is a method of removing ashing by a plasma method, and the charged particles incident from the plasma at the time of ashing are kept on the surface of the insulating pattern so that they hardly flow through the conductive pattern. Damage to a conductive portion, for example, a gate insulating film, can be minimized, which eliminates the need to keep the antenna ratio within a certain range and increases design flexibility.

According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor device.
After etching the conductive material layer, a first conductive pattern that is not conductive to the conductive part, and a second conductive pattern that is conductive to the conductive part, and has an area smaller than the first conductive pattern, and then forms a resist pattern Since it is a method of removing ashing by a plasma method, charged particles are incident on the first conductive pattern and the second conductive pattern from the plasma at the time of ashing, but are electrically connected to the conductive portion in the first conductive pattern having a large area. Since there is no plasma damage, plasma damage can be suppressed to a low level without receiving plasma damage and because the area of the second conductive pattern that is electrically connected to the conductive portion is small. Then, after the ashing, the first conductive pattern and the second conductive pattern are conducted, so that the conductive pattern obtained from these can have a sufficient area (length). Therefore, if this manufacturing method is applied to, for example, processing of a wiring connected to a gate electrode, a source, a drain, and a well in the manufacture of a MOS transistor, variation in threshold voltage (Vth) is reduced, and fixing in an analog circuit is performed. Pattern noise can be reduced, thereby making it possible to design a circuit with a low power supply voltage.

[Brief description of the drawings]

FIGS. 1 (a) to 1 (c) are cross-sectional views of essential parts for describing an embodiment of a manufacturing method according to the present invention in the order of steps.

2 (a) to 2 (c) are cross-sectional side views of a main part for describing an embodiment of the manufacturing method of the present invention in the order of steps.

FIG. 3 is a side sectional view of an essential part for explaining an embodiment of the manufacturing method of the present invention.

FIG. 4 is a side sectional view of a main part for describing an example of a conventional manufacturing method.

FIG. 5 is a side sectional view of a main part for describing another example of a conventional manufacturing method.

[Explanation of symbols]

10, 20, 40 Base 11, 21, 41 Gate insulating film 13, 26 Conductive material layer 14, 27 Insulating film 15, 28 Resist pattern 16, 29 Insulating pattern 17 Gate electrode (conductive pattern) 23, 43 Gate electrode 30 Wiring pattern (Conductive pattern) 46 First wiring pattern (First conductive pattern) 47 Second wiring pattern (Second conductive pattern)
48 interlayer insulating film 49 conduction pattern

Claims (2)

[Claims] A step of forming a conductive material layer on the base on which the conductive portion is formed in a state of being electrically connected to the conductive portion; a step of forming an insulating film on the conductive material layer; Forming a resist pattern, etching the insulating film using the resist pattern, further etching the conductive material layer to form an insulating pattern and a conductive pattern, and forming the insulating pattern and the conductive pattern. With it left
Ashing and removing the resist pattern by a plasma method. 2. A step of forming a conductive material layer on the substrate on which the conductive portion is formed so as to be electrically connected to the conductive portion, a step of forming a resist pattern on the conductive material layer, and using the resist pattern. Forming a first conductive pattern that is not conductive to the conductive part and a second conductive pattern that is conductive to the conductive part and has an area smaller than the first conductive pattern. Ashing the resist pattern by a plasma method; forming an insulating film covering the first conductive pattern and the second conductive pattern; and forming the first conductive film on the insulating film. Forming a conductive pattern for conducting the pattern and the second conductive pattern. A method for manufacturing a semiconductor device, comprising: