JPH10247166A - Error corrector and error correcting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error corrector which improves the reliability by detecting a defect of a memory element before executing an error correction. SOLUTION: In a memory test mode, a switching signal 102 is made active, a test signal 106 is outputted to a memory element 5 by a test mode switching device 4 to conduct a memory test of the memory element 5, when it is confirmed that the memory function of the whole addresses of the memory element 5 is normal, an operation mode becomes normal, the switching signal 102 is made inactive and a normal operation signal 104 is outputted to the memory element 5 to correct an error of a reproduction signal 108 stored in the memory element 5. Consequently, the defect of the memory element 5 can be detected before executing the error correction and the reliability of the error correction is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error corrector using a storage device or a storage element for temporarily storing input data when correcting an error in digital data, and more particularly to an error corrector using a product code. .

[0002]

2. Description of the Related Art In recent years, various types of optical disks such as a compact disk (CD) and a laser disk (LD) have been commercialized, and large-capacity optical disks such as digital video disks (DVD) have appeared. ing. A large-capacity disc such as a DVD has information recorded at a higher density than a conventional CD or the like, so that an error easily occurs in a reproduced signal. For example, narrowing the track pitch increases crosstalk between tracks, and shortening the pit length (highing the linear density) increases intersymbol interference and increases the probability of erroneously reproducing a signal. . Therefore, a high-density optical disk employs an error correction code having a higher performance and a higher correction capability than an error correction code used in a conventional CD or the like.

FIG. 4 is a block diagram of a conventional memory corrector as described above.

In this conventional memory corrector, a reproduced signal 108 from a reproducing device (not shown) is temporarily stored in a memory element 45, and an error correcting device 108 is instructed by a control command 101 from a control microcomputer (not shown). 41 is the normal operation signal 1
The error correction is performed on the reproduction signal 108 stored in the memory element 45 through the memory element 45.

The error corrector 41 includes a control microcomputer interface 46 and an error correction circuit 43.

When the control microcomputer interface 46 receives the instruction of the normal operation mode by the control command 101 output from the control microcomputer, the control operation
An instruction to start the normal operation is transmitted to the error correction circuit 43 via the control circuit 03.

The error correction circuit 43 receives the normal operation control instruction 1
When an instruction for normal operation is received via 03, a normal operation signal 104 is output to the memory element 45, and the reproduction signal 108 stored in the memory element 45 is read and error correction is performed.

Next, the operation of the conventional error corrector 41 will be described.

First, a control command 10 from the control microcomputer
When the instruction of the normal operation mode is transmitted by 1, the control microcomputer interface 46 sets the normal operation control
The instruction to start the normal operation is transmitted to the error correction circuit 43 via the. The error correction circuit 43 outputs the normal operation signal 104
Is transmitted to the memory element 45,
The error correction of the reproduction signal 108 stored in is performed.

In the DVD, as shown in FIG. 5, 16 rows of PO parity and 10 columns of PI parity are generated and added to 16 data sectors (172 bytes × 192 rows).
A Reed-Solomon product code of 182 bytes × 208 rows is constructed. The error correction method shown in FIG.
Solomon Product Code)
Reference ("O plus E", 1996-6, No. 1)
99, p93-97, DVD physical format and modulation method). As described above, when a product code is used as an error correction code, it is necessary to temporarily store input data in a memory. The reproduced signal data is stored in the memory in order from address 0 in FIG. Error correction (PI correction) in the row direction (horizontal direction in the figure) can be executed if data is input up to the rightmost address (182 × n-1: n = 1 to 208) in FIG. , The column direction (vertical direction in the figure) cannot be executed unless the input is completed in the memory up to the last row. Therefore, R
The SPC method requires a memory capable of recording data of at least 182 × 208 bytes or more.
When data is continuously input, for example, 1
A memory for 82 × 208 × 2 pages is prepared, and while data is being input to one page, error correction processing of data stored in the other page is performed.

[0011]

In the conventional error corrector described above, when error correction is performed using a memory element, if the memory element itself has a defect, not only error correction cannot be performed, but also a normal error correction cannot be performed. However, there is a problem that an incorrect reproduction signal is erroneously output.

An object of the present invention is to provide an error corrector with improved reliability by detecting a defect in a memory element before performing error correction.

[0013]

In order to achieve the above object, an error correction method according to the present invention is to store a reproduced signal once reproduced by a reproducing apparatus in a memory element and to control the stored reproduced signal by a control microcomputer. In the error correction method of performing error correction in accordance with an instruction from the control microcomputer, when an instruction to start a memory test operation is input from the control microcomputer, arbitrary write data is stored in the memory element, and the stored write data is read to read the read data. Comparing the write data with the read data, confirming that the memory functions of all addresses of the memory element are normal, and correcting the error of the reproduction signal stored in the memory element. It is characterized by.

According to an embodiment of the present invention, the control microcomputer outputs an instruction to start a memory test operation during initialization after power-on.

According to the present invention, an arbitrary write data is stored in a memory element, the stored write data is read out as read data, and the write data is compared with the read data. After confirming that the function is normal, the error correction of the reproduction signal stored in the memory element is performed.

Therefore, a defect of the memory element can be detected before the error correction is performed, and the reliability of the error correction can be improved.

Further, according to the embodiment of the present invention, the write data is composed of all bits "1" and all bits "0".
As two types of data, a memory test is performed using the two types of write data for the memory function of all addresses of the memory element.

According to the present invention, all bits of the memory element are set to "1".
A memory test is performed using the write data of all bits and the write data of all bits “0”.

Therefore, in all addresses of the memory element, both the case where the bit changes from "0" to "1" and the case where the bit changes from "1" to "0" are checked. And a reliable memory test can be performed.

Further, when the error corrector of the present invention receives the instruction of the normal operation mode by the control command output from the control microcomputer, it makes the switching signal inactive and sends the switching signal to the error correction circuit through the normal operation control instruction. When an instruction to start a normal operation is transmitted and an instruction to start a memory test operation is received by the control command, the switch signal is activated and an instruction to start a memory test operation is transmitted to the memory test circuit via a test circuit control instruction. When a normal operation start instruction is received by the control microcomputer interface and the normal operation control command, a normal operation signal is output to the memory element as a memory signal via the test mode switch, and the reproduction stored in the memory element is performed. An error correction circuit for reading a signal and performing error correction; When a memory test operation start instruction is received according to the instruction, a test signal is output as a memory signal to the memory element via the test mode switch, and after arbitrary write data is stored at a certain address of the memory element. The stored write data is used as read / read data, the write data and the read data are compared to determine whether the memory function of all addresses of the memory element is normal / abnormal, and the determination result is transmitted to the test circuit control instruction. A memory test circuit that transmits to the control microcomputer interface via the control microcomputer interface, the normal operation signal and the memory signal are connected when the switching signal is inactive, and the test signal and the memory are connected when the switching signal is active. And a test mode switch for connecting a signal.

According to an embodiment of the present invention, when the memory test circuit inputs an instruction to start a memory test operation via the test circuit control instruction, the memory test circuit outputs a test address increment signal and outputs the test address increment signal by an OK / NG signal. A memory test control circuit for transmitting a new test address increment signal after transmitting a determination result of normal / abnormal of a memory function of a memory element to the control microcomputer interface via the test circuit control instruction. When the test address increment signal is input, a WR signal is output through the write data generation circuit and the test signal, a memory address increment signal is output to the memory address generation circuit, and after a certain period of time, the RD signal is read data. R which is output via a latch and the test signal A W signal generator outputs one of the addresses of the memory element as a memory address via the test signal, and when the memory address increment signal is input, increments the output memory address by one. A memory address generation circuit for outputting, a write data generation circuit for receiving the WR signal, generating arbitrary data, outputting the write data as the write data via the test signal, and continuously outputting the write data, and a RD signal. Then, a read data latch that continuously outputs read data read from the memory element via the test signal as read data, and compares all bits of the write data with the read data to determine a match / mismatch, and The result is OK /
And a comparator for outputting as an NG signal.

According to the present invention, in the memory test mode, a switching signal is activated, a test signal is output to a memory element by a test mode switch, a memory test of the memory element is performed, and a normal memory function of all addresses of the memory element is performed. Is confirmed, the normal operation mode is set, the switching signal is made inactive, the normal operation signal is output to the memory element, and error correction of the reproduction signal stored in the memory element is performed.

Therefore, a defect of the memory element can be detected before the error correction is performed, and the reliability of the error correction can be improved.

According to another embodiment of the present invention, the write data output from the write data generation circuit is composed of data of all bits “1” and data of all bits “0”.

According to the present invention, all bits of the memory element are set to "1".
A memory test is performed using the write data of all bits and the write data of all bits “0”.

Therefore, in all the addresses of the memory element, both the case where the bit changes from "0" to "1" and the case where the bit changes from "1" to "0" are checked. And a reliable memory test can be performed.

[0027]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an error corrector according to an embodiment of the present invention, FIG. 2 is a block diagram of a memory test circuit 2 in FIG. 1, and FIG. 3 shows an operation of the memory test circuit 2 in FIG. It is a timing chart.

In the present embodiment, a reproduced signal 108 from a reproducing device (not shown) is temporarily stored in the memory element 5, and the error corrector 1 stores the reproduced signal 108 in accordance with an instruction of a control command 101 from a control microcomputer (not shown). The error correction of the reproduction signal 108 stored in the memory element 5 via the signal 107 is performed.

The error corrector 1 includes a control microcomputer interface 6, an error correction circuit 3, and a memory test circuit 2.
And a test mode switch 4.

When the control microcomputer interface 6 receives the instruction of the normal operation mode by the control command 101 output from the control microcomputer, it makes the switching signal 102 inactive and sends it to the error correction circuit 3 via the normal operation control instruction 103. When the instruction to start the operation is transmitted and the instruction to start the memory test operation is received by the control command 101, the switching signal 102 is activated and the instruction to start the memory test operation is sent to the memory test circuit 2 via the test circuit control instruction 105. introduce.

The error correction circuit 3 receives the normal operation control instruction 10
3 receives an instruction to start normal operation, the normal operation signal 104 is transmitted to the memory signal 1 via the test mode switch 4.
The read signal 108 is output to the memory element 5 as 07, and the reproduction signal 108 stored in the memory element 5 is read and error correction is performed.

When the memory test circuit 2 receives a memory test instruction according to the instruction of the test circuit control instruction 105, it outputs a test signal 106 to the memory element 5 as a memory signal 107 via the test mode switch 4, and After the write data is stored at a certain address of the memory element 5, the stored content is read, the write data is compared with the read read data to determine whether the memory function is normal or abnormal, and the result of the determination is used as a test circuit control instruction 105 Via the control microcomputer interface 6.

The test mode switch 4 outputs a switch signal 102
Is inactive, the normal operation signal 104 and the memory signal 107 are connected. When the switching signal 102 is active, the test signal 106 and the memory signal 107 are connected.

As shown in FIG. 2, when a memory test operation start instruction is input by a test circuit control instruction 105, the memory test circuit 2 outputs a test address increment signal 109, and a memory element is output by an OK / NG signal 118. 5 is transmitted to the control microcomputer interface 6 via the test circuit control instruction 105 when the judgment of normal / abnormal of the memory function of No. 5 is transmitted, and then outputs a new test address increment signal 109. 7, a test address increment signal 109 is input, a WR signal 112 is output via the write data generation circuit 11 and the test signal 106, and a memory address increment signal 110 is output to the memory address generation circuit 10, and after a certain period of time, Read RD signal 111 Data latch 12 and the test signal 106
R / W signal generator 8 for outputting through
And a memory address generation circuit 10 that outputs one of the addresses as the memory address 113 via the test signal 106 and, when the memory address increment signal 110 is input, increments the output memory address 113 by one and outputs it. , WR signal 112, the write data generation circuit 11 generates arbitrary data and outputs it as write data 114 via the test signal 106 and continues to output it as write data 115
And the RD signal 111, the read data 11 read from the memory element 5 via the test signal 106
6 is continuously output as read data 117, the write data 115 and the read data 1
A comparator 9 that compares all 17 bits to determine a match / mismatch and outputs the result as an OK / NG signal 118
It is composed of

In this embodiment, the error corrector 1 switches between a normal operation mode and a test mode for performing a memory test by receiving a control command 101 from a control microcomputer.

Next, the operation of the error corrector 1 according to this embodiment will be described.

First, the operation in the normal operation mode will be described.

When the instruction of the normal operation mode is transmitted by the control command 101 from the control microcomputer, the control microcomputer interface 6 makes the switching signal 102 inactive and sends the normal signal to the error correction circuit 3 via the normal operation control instruction 103. An operation start instruction is transmitted. In the test mode switch 4, the normal operation signal 104 and the memory signal 10
7 is connected.

The error correction circuit 3 outputs the normal operation signal 1
04 is transmitted to the memory element 5 as the memory signal 107 so that the reproduction signal 10 stored in the memory element 5 is transmitted.
8 error correction.

Next, the operation of the error corrector 1 in the test mode will be described with reference to FIG.

First, the control command 10 from the control microcomputer
When the instruction to start the memory test operation is transmitted by 1, the control microcomputer interface 6 activates the switching signal 102 and transmits the instruction to start the memory test operation to the memory test circuit 2 via the test circuit control instruction 105. In the test mode switch 4, the switching signal 10
When the signal 2 becomes active, the test signal 106 and the memory signal 107 are connected.

Next, in the memory test control circuit 7, the test circuit control instruction 10
When an instruction to start the memory test operation is input through the terminal 5,
The test address increment signal 109 is output to the R / W signal generator 8. When the test address increment signal 109 is input to the R / W signal generator 8, the WR
Signal 112 and memory address increment signal 110
Is output. The memory address generation circuit 10 increments the memory address 113 to be output by inputting the memory address increment signal 110 by one.
Then, the write data generation circuit 11 outputs the WR signal 112
Is input, arbitrary data is generated, output as write data 114, and continue to be output as write data 115. The WR signal 112, the memory address 113, and the write data 114 are transmitted to the test mode switch 4 via the test signal 106, and further transmitted to the memory element 5 via the memory signal 107. Then, in the memory element 5, the write data 114 is stored at the address indicated by the memory address 113.

Next, the R / W signal generator 8 outputs an RD signal 111. The RD signal 111 is the test signal 1
The test signal is transmitted to the test mode switcher 4 via the reference numeral 06 and further transmitted to the memory element 5 via the memory signal 107.
Therefore, the memory element 5 reads the data stored at the address indicated by the memory address 113 and reads out the data 1
Output as 16. Read data 116 is transmitted to test mode switch 4 via memory signal 107 and further input to read data latch 12 via test signal 106. In the read data latch 12, the RD signal 1
Since 11 is input, the read data 116 is latched and output as read data 117.

In the comparator 9, the write data 115
And all bits of read data 117 are compared, and the comparison result is output to memory test control circuit 7 as OK / NG signal 118. In the memory test control circuit 7, O
Based on the result of the K / NG signal 118, the normal / abnormal judgment of the memory function is performed, and the result is transmitted to the control microcomputer interface 6 via the test circuit control instruction 105, and further controlled by the control microcomputer interface 6 via the control command 101. It is transmitted to the microcomputer.

The operation up to this point is the operation of one memory test cycle in the memory test operation. When this one memory test cycle is completed, the memory test control circuit 7
Outputs a new test address increment signal 109 to repeat the same memory test operation.

Such a memory test is performed, for example, after the power supply of the error corrector 1 which is a higher-level device of the error correction circuit 3 or the memory test circuit 2 or a reproducing device such as a DVD which is a higher-level device is turned on. This can be done at any time during the time when the device is assembled and in operation. Of course, the memory element used does not require any special element, and the conventional dynamic RAM (D
RAM) and static RAM (SRAM) can be used, so that the cost does not increase.

When a memory test is performed by the memory test circuit 2 of the error corrector 1, the data 114 to be written into the memory element 5 is divided into all bits "1" and all bits "0".
As a kind, when all the memory addresses of the memory element 5 are inspected, both the case where the bit changes from “0” to “1” and the case where the bit changes from “1” to “0” Can be inspected, so that a reliable memory test can be performed.

[0049]

As described above, according to the error corrector and the error correction method of the present invention, the reliability of error correction can be improved with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of an error corrector according to an embodiment of the present invention.

FIG. 2 is a block diagram of a memory test circuit 2 in FIG.

FIG. 3 is a timing chart showing an operation of the memory test circuit 2 of FIG. 2;

FIG. 4 is a block diagram of a conventional error corrector.

FIG. 5 is a diagram illustrating an RSPC error correction method for DVD.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Error corrector 2 Memory test circuit 3 Error correction circuit 4 Test mode switch 5 Memory element 6 Control microcomputer interface 7 Memory test control circuit 8 R / W signal generator 9 Comparator 10 Memory address generation circuit 11 Write data generation circuit 12 Read Data latch 41 Error corrector 43 Error correction circuit 45 Memory element 46 Control microcomputer interface 101 Control command 102 Switching signal 103 Normal operation control instruction 104 Normal operation signal 105 Test circuit control instruction 106 Test signal 107 Memory signal 108 Reproduction signal 109 Test address increment Signal 110 Memory address increment signal 111 RD signal 112 WR signal 113 Memory address 114 Write data 115 Write data 116 Read data Data 117 read data 118 OK / NG signal

Claims (6)

[Claims] 1. An error correction method for temporarily storing a reproduced signal reproduced by a reproducing device in a memory element and correcting an error of the stored reproduced signal in accordance with an instruction from a control microcomputer. When a start instruction is input, arbitrary write data is stored in the memory element, the stored write data is read out as read data, the write data is compared with the read data, and all addresses of the memory element are compared. An error correction method for performing error correction of the reproduction signal stored in the memory device after confirming that the memory function of the memory device is normal. 2. The control microcomputer outputs an instruction to start a memory test operation during initialization after power-on.
Error correction method described. 3. A memory test is performed using two types of write data, wherein the write data is two types of data of all bits "1" and data of all bits "0", and a memory function of all addresses of the memory element is used. The error correction method according to claim 1. 4. When a normal operation mode instruction is received by a control command output from the control microcomputer, the switching signal is made inactive and a normal operation start instruction is transmitted to the error correction circuit via the normal operation control instruction. Receiving a memory test operation start instruction by the control command, activating the switching signal and transmitting a memory test operation start instruction to the memory test circuit via a test circuit control instruction; When an instruction to start normal operation is received by the operation control command, the normal operation signal is output to the memory element as a memory signal via the test mode switch, and the reproduction signal stored in the memory element is read and error correction is performed. A correction circuit, and a memory test according to the instruction of the test circuit control instruction. Upon receiving an operation start instruction, a test signal is output as a memory signal to the memory element via the test mode switch, and any write data is stored at a certain address of the memory element, and then the write is stored. Data is read and read data, the write data and the read data are compared to determine whether the memory function of all addresses of the memory element is normal or abnormal, and the result of the determination is transmitted to the control microcomputer via the test circuit control instruction. A memory test circuit for transmitting to the interface; connecting the normal operation signal and the memory signal when the switching signal is inactive; connecting the test signal and the memory signal when the switching signal is active An error corrector comprising a test mode switch. 5. When the memory test circuit inputs a memory test operation start instruction via the test circuit control command, the memory test circuit outputs a test address increment signal, and the memory function of the memory element operates normally by an OK / NG signal. A memory test control circuit that outputs a new test address increment signal after transmitting the result of the determination to the control microcomputer interface via the test circuit control command when the determination of the abnormality is transmitted; and the test address increment signal. When you enter
R outputs a WR signal via a write data generation circuit and the test signal, outputs a memory address increment signal to the memory address generation circuit, and outputs a RD signal after a lapse of a predetermined period via the read data latch and the test signal. / W signal generator, outputs one of the addresses of the memory element as a memory address via the test signal, and when the memory address increment signal is input, increments the output memory address by one. A memory data generation circuit for outputting the RD signal; a write data generation circuit for generating arbitrary data and outputting it as write data via the test signal and continuing to output the same as write data; When input, the memory device transmits the test signal A read data latch for continuously outputting read data read as read data, and a comparator for comparing all bits of the write data with the read data to determine a match / mismatch and outputting the result as the OK / NG signal Claim 4 comprising:
The error corrector described. 6. The error corrector according to claim 4, wherein the write data output from the write data generation circuit includes data of all bits “1” and data of all bits “0”.