JPH10242783A - Voltage limit circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the voltage limit circuit that limits an output voltage of a signal amplifier that amplifies an input signal to a prescribed setting limit voltage accurately while suppressing power consumption. SOLUTION: An operational amplifier A1 of a lower limit voltage limit circuit 10 amplifier an input voltage Vin being an input signal to provide an output of an output voltage Vout , an operational amplifier A2 amplifies a difference voltage of the output voltage Vout and a lower limit setting voltage VLL and provides an output of it to a diode D1 of an input limit circuit 11. When the output voltage Vout of the operational amplifier A1 is higher than the lower limit setting voltage VLL, the diode D1 is made nonconductive, the input voltage Vin is fed to the noninverting input terminal of the operational amplifier A1 as it is, and when the output voltage Vout of the operational amplifier A1 is lower than the lower limit setting voltage VLL and the output voltage of the operational amplifier A2 is higher than the forward voltage of the diode D1 more than the input voltage Vin , the diode D1 is made conductive and the output voltage Vout of the operational amplifier A1 is limited nearly to the lower limit setting voltage VLL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage limiting circuit, and more particularly, to a voltage limiting circuit for accurately limiting an output of a signal amplifier for amplifying an input signal to a predetermined set limiting voltage.

[0002]

2. Description of the Related Art An input signal is amplified in an analog signal processing circuit such as an image input device in a digital (color) PPC, an image data input device in a DTP (or computer), a document reading device in a facsimile, and an imaging device such as a VTR. There is provided a signal amplifying circuit which employs various voltage limiting circuits for limiting the output voltage of such a signal amplifying circuit.

[0003] As such a voltage limiting circuit, conventionally,
In the lower limit voltage limiting circuit, for example, a circuit as shown in FIG. 22 is used. In the lower limit voltage limiting circuit 1, a current limiting resistor RL is connected to the output of the amplifier 2, and a clamp diode DL connected to an output limiting set voltage V _LL is connected. Amplify and output output voltage. The output voltage of the amplifier 2 is higher than the output limit setting voltage _VLL by the clamp diode D
When the voltage drops below the forward voltage drop of L (about 0.7 V) or more, the clamp diode DL becomes conductive, and the output voltage is limited by the voltage drop by the current limiting resistor RL. According to the lower limit voltage limiting circuit 1, the output voltage is substantially limited to the output limit setting voltage V _LL -0.7V or more.

Conventionally, in an upper limit voltage limiting circuit, FIG.
The one shown in FIG. 3 is used. In the upper limit voltage limiting circuit 3, a current limiting resistor RL is connected to an output of the amplifier 2, and a clamp diode DU connected to an output limit setting voltage V _LU is connected. When the output voltage exceeds the output limiting voltage V _{LU by} more than the forward voltage drop (about 0.7 V) of the clamp diode DU, the clamp diode DU conducts and the output voltage is limited by the voltage drop by the current limiting resistor RL. According to the upper limit voltage limiting circuit 3, the output voltage is V _LU + 0.7V by the clamp diode DU and the current limiting resistor RL.
Limited to:

Further, conventionally, in the upper and lower limit voltage limiting circuit,
The one shown in FIG. 24 is used. The upper and lower limit voltage limiting circuit 5 supplies a current limiting resistor RL to the output of the amplifier 2.
_Are connected, the clamp diode DL connected to the output limit setting voltage V _LL and the output limit setting voltage V
_The clamp diode DU connected to _LU is connected. The upper / lower limit voltage limiting circuit 5 determines that the output voltage of the amplifier 2 is
When the output voltage drops below the output limit setting voltage _{VLL by} more than the forward voltage drop (about 0.7 V) of the clamp diode DL, the clamp diode DL conducts, and the output voltage is limited by the voltage drop by the current limiting resistor RL. 2, the output voltage is
When the output voltage exceeds the output limiting voltage V _{LU by} more than the forward voltage drop (about 0.7 V) of the clamp diode DU, the clamp diode DU conducts, and the output voltage is limited by the voltage drop by the current limiting resistor RL. Therefore, according to the upper / lower limit voltage limiting circuit 5, the output voltage is substantially limited to the output limit setting voltage V _LL -0.7V or more,
V is determined by the clamp diode DU and the current limiting resistor RL.
_LU + 0.7V or less.

[0006]

However, in such a conventional voltage limiting circuit, the output voltage is limited to the set limiting voltage by using the clamp diodes DU and DL and the current limiting resistor RL. There was such a problem.

[0007] 1. The upper and lower limit voltages have a deviation of about 0.7 V from the set voltage, change with the input voltage to the voltage limit circuit, and cannot accurately limit the output voltage to the set limit voltage.

[0008] 2. When the current limiting resistor RL can be increased, there is not much problem. However, when the current limiting resistor RL must be decreased, that is, when a high-speed signal is output when the load resistance is small or the load capacity is large. Since the current flowing for voltage limitation is supplied from the output of the amplifier, the power consumption increases when the voltage of the amplifier is limited. Further, the output limit setting voltage also requires a current driving capability equivalent to that of the amplifier, and it is difficult to reduce power consumption.

Therefore, according to the present invention, a difference voltage between an output voltage of a signal amplifier for amplifying and outputting an input signal and a predetermined set limiting voltage is amplified by the amplifier, and the output voltage of the amplifier becomes a predetermined value. If it exceeds, the output voltage of the signal amplifier is accurately and stably limited to the set limit voltage while suppressing power consumption by limiting the magnitude of the input signal of the signal amplifier by the input limiting circuit. It is intended to provide a voltage limiting circuit.

According to a second aspect of the present invention, a first amplifier amplifies a difference voltage between an output voltage of a signal amplifier for amplifying and outputting an input signal and a predetermined first set limiting voltage. When the output voltage of the signal amplifier exceeds the predetermined value, the magnitude of the input signal of the signal amplifier is limited by the first input limiting circuit, and the difference voltage between the output voltage of the signal amplifier and the predetermined second set limiting voltage is reduced by the second input limiting circuit. When the output voltage of the second amplifier exceeds a predetermined value, the magnitude of the input signal of the signal amplifier is limited by the second input limiting circuit, thereby reducing the output voltage of the signal amplifier. It is an object of the present invention to provide a voltage limiting circuit that accurately and stably limits the voltage between a first set limit voltage and a second set limit voltage while suppressing the voltage.

According to a third aspect of the present invention, an output voltage of a signal amplifier for amplifying and outputting an input signal, an output voltage of an amplifier for amplifying a difference voltage between an output voltage of an analog multiplier and a predetermined set limit voltage, and , Into the analog multiplier,
An analog multiplier multiplies the two input voltages by a predetermined multiplication and outputs the output voltage as an output voltage. The output voltage of the analog multiplier is input to an amplifier, and the output of the signal amplifier output through the analog multiplier is output. By limiting the voltage to the set limit voltage, the output voltage of the signal amplifier output via the analog multiplier can be reduced while suppressing power consumption.
It is an object of the present invention to provide a voltage limiting circuit that accurately and stably limits a set limit voltage.

According to a fourth aspect of the present invention, an output voltage of a signal amplifier for amplifying and outputting an input signal is input to a first analog multiplier, and an output of the first analog multiplier is output to a second analog multiplier. And an output voltage of a first amplifier for amplifying a difference voltage between an output voltage of a second analog multiplier and a predetermined first set limit voltage, and an output voltage of the second analog multiplier and a predetermined voltage. And an output voltage of a second amplifier for amplifying a difference voltage between the second set limit voltage and the first and second analog multipliers. By performing a predetermined multiplication between the voltages, the output of the signal amplifier output via the first analog multiplier and the second analog multiplier is set between the first set limit voltage and the second set limit voltage. Output via the first and second analog multipliers by limiting To provide a voltage limiting circuit that accurately and stably limits the output voltage of a signal amplifier to be controlled between a first set limit voltage and a second set limit voltage while suppressing power consumption. The purpose is.

[0013]

According to a first aspect of the present invention, there is provided a voltage limiting circuit for amplifying an input signal and outputting the amplified signal, and a difference voltage between an output voltage of the signal amplifier and a predetermined set limiting voltage. An amplifier for amplifying, and an input limiting circuit for limiting the magnitude of the input signal input to the signal amplifier when an output voltage of the amplifier exceeds a predetermined value, wherein the output voltage of the signal amplifier is limited by the setting. The above purpose is achieved by limiting the voltage.

According to the above configuration, the difference voltage between the output voltage of the signal amplifier for amplifying and outputting the input signal and the predetermined set limiting voltage is amplified by the amplifier, and when the output voltage of the amplifier exceeds the predetermined value, the signal is amplified. Since the magnitude of the input signal of the amplifier is limited by the input limiting circuit, the output voltage of the signal amplifier can be accurately and stably limited to the set limiting voltage while suppressing power consumption.

According to a second aspect of the present invention, there is provided a voltage limiting circuit for amplifying an input signal and outputting the amplified signal, and amplifying a difference voltage between an output voltage of the signal amplifier and a predetermined first set limiting voltage. One amplifier, a first input limiting circuit that limits the magnitude of the input signal input to the signal amplifier when the output voltage of the first amplifier exceeds a predetermined value, and an output voltage of the signal amplifier. A second amplifier that amplifies a difference voltage between a predetermined second set limit voltage different from the first set limit voltage, and an input to the signal amplifier when an output voltage of the second amplifier exceeds a certain value. A second input limiting circuit for limiting the magnitude of the input signal to be applied, and limiting the output voltage of the signal amplifier between the first set limiting voltage and the second set limiting voltage. Achieves the above objectives

According to the above configuration, the difference voltage between the output voltage of the signal amplifier for amplifying and outputting the input signal and the predetermined first set limiting voltage is amplified by the first amplifier, and the output of the first amplifier is amplified. When the voltage exceeds a predetermined value, the magnitude of the input signal of the signal amplifier is limited by the first input limiting circuit, and the difference voltage between the output voltage of the signal amplifier and the predetermined second set limiting voltage is determined by the second amplifier. When the output voltage of the second amplifier exceeds a predetermined value, the magnitude of the input signal of the signal amplifier is limited by the second input limiting circuit, so that the output voltage of the signal amplifier is reduced in power consumption. In addition, it is possible to accurately and stably limit the voltage between the first set limit voltage and the second set limit voltage.

According to a third aspect of the present invention, there is provided a voltage limiting circuit comprising: a signal amplifier for amplifying and outputting an input signal; and two input terminals, wherein a predetermined voltage is applied between input voltages input to the two input terminals. An analog multiplier that performs multiplication and outputs the amplified signal, and an amplifier that amplifies a difference voltage between an output voltage of the analog multiplier and a predetermined set limit voltage, wherein the output voltage of the signal amplifier is one of the analog multipliers. And inputting the output voltage of the amplifier to the other input terminal of the analog multiplier, and limiting the output of the signal amplifier output via the analog multiplier to the set limiting voltage. Achieves the above object.

According to the above configuration, the output voltage of the signal amplifier that amplifies and outputs the input signal and the output voltage of the amplifier that amplifies the difference voltage between the output voltage of the analog multiplier and the predetermined set limit voltage are calculated. Input to the analog multiplier, the analog multiplier multiplies the two input voltages by a predetermined multiplication, and outputs the output voltage, and the output voltage of the analog multiplier is input to the amplifier, and the analog multiplier is operated. The output voltage of the signal amplifier output through the analog multiplier is limited to the set limit voltage, so that the output voltage of the signal amplifier output through the analog multiplier can be controlled with high accuracy while suppressing power consumption.
In addition, the voltage can be stably limited to the set limit voltage.

According to a fourth aspect of the present invention, there is provided a voltage limiting circuit comprising: a signal amplifier for amplifying and outputting an input signal; and two input terminals, wherein a predetermined voltage is applied between input voltages input to the two input terminals. A first analog multiplier that performs multiplication and outputs, and a second analog multiplier that has two input terminals and performs predetermined multiplication between input voltages input to the two input terminals and outputs the result. A first amplifier for amplifying a difference voltage between an output voltage of the second analog multiplier and a predetermined first set limit voltage, and an output voltage of the second analog multiplier and the first set limit A second amplifier that amplifies a difference voltage between the voltage and a predetermined second set limit voltage,
An output voltage of the signal amplifier is input to one input terminal of the first analog multiplier, an output of the first analog multiplier is input to one input terminal of the second analog multiplier, An output voltage of a first amplifier and an output voltage of the second amplifier are input to the other input terminals of the first analog multiplier and the second analog multiplier, respectively.
By limiting the output of the signal amplifier output via the first analog multiplier and the second analog multiplier between the first set limit voltage and the second set voltage, The above objective has been achieved.

According to the above configuration, the output voltage of the signal amplifier that amplifies and outputs the input signal is input to the first analog multiplier, and the output of the first analog multiplier is input to the second analog multiplier. Then, the output voltage of the first amplifier for amplifying the difference voltage between the output voltage of the second analog multiplier and the predetermined first set limit voltage, the output voltage of the second analog multiplier and the predetermined second And the output voltage of the second amplifier for amplifying the difference voltage between the set limit voltage and the first and second analog multipliers. To limit the output of the signal amplifier output via the first analog multiplier and the second analog multiplier between the first set limit voltage and the second set limit voltage. So the signal output through the first and second analog multipliers The output voltage of the width units, while suppressing power consumption, high precision, and can be limited during the stable first setting limit voltage and a second set limit voltage.

[0021]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. It should be noted that the embodiments described below are preferred embodiments of the present invention, and therefore, various technically preferable limitations are added. However, the scope of the present invention is not limited to the following description. The embodiments are not limited to these embodiments unless otherwise specified.

FIG. 1 is a diagram showing a first embodiment of a voltage limiting circuit according to the present invention. This embodiment is a lower limit voltage limiting circuit using a non-inverting amplifier and a diode. This corresponds to 1.

FIG. 1 is a circuit diagram of a lower limit voltage limiting circuit 10 to which the first embodiment of the voltage limiting circuit of the present invention is applied. In FIG. 1, the lower-limit voltage limiting circuit 10 includes an operational amplifier A1, an operational amplifier A2, a non-inverting amplifier, a resistor R _in , a resistor Rf, a resistor Rs, a diode D1, and the like.

The operational amplifier (signal amplifier) A1, the non-inverted through the resistor R _in the input terminal the input voltage V _in is input, the inverting input terminal is grounded via a resistor Rs. The output of the operational amplifier A1 is connected to the inverting input terminal of the operational amplifier A1 via a resistor Rf.
It is connected to the inverting input terminal of the operational amplifier A2, the operational amplifier A1 amplifies the input voltage V _in the output voltage V _OUT
Is output.

The operational amplifier (amplifier) A2 has an inverting input terminal connected to the output of the operational amplifier A1, and a non-inverting input terminal to which the lower limit setting voltage _VLL is input. The output of the operational amplifier A2 is connected to the non-inverting input terminal of the operational amplifier A1 via the diode D1, and the operational amplifier A2 calculates the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the lower limit setting voltage _VLL. The signal is amplified and output to the diode D1.

The diode D1 and the resistor R _in constitutes an input limiting circuit 11, the input limiting circuit 11 includes a diode D than the output voltage is the input voltage V _in of the operational amplifier A2
If only 1 forward voltage (about 0.7 V) increases, the diode D1 is turned on, the input voltage V _in of the operational amplifier A1
Limit the size of

That is, the lower limit voltage limiting circuit 10 uses the operational amplifier A1 which is a non-inverting amplifier as a signal amplifier, and amplifies a difference voltage between the output voltage V _OUT and the lower limit setting voltage _VLL which is a setting limiting voltage. Operational amplifier A2 for amplifier
, A resistor R _in and a diode D
1 is a lower-limit voltage limiting circuit using the circuit of FIG.

According to the lower limit voltage limiting circuit 10 of the present embodiment amplifies the input voltage V _in operational amplifier A1 is input signal is output as the output voltage V _OUT, the output voltage V
_OUT is input to the inverting input terminal of the operational amplifier A2. The lower limit setting voltage V _LL is input to the non-inverting input terminal of the operational amplifier A2, and the operational amplifier A2 amplifies the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the lower limit setting voltage V _LL, and Operational amplifier A1 via diode D1
Output to the non-inverting input terminal. When the output voltage V _OUT of the operational amplifier A1 is higher than the lower limit set voltage V _LL , the lower limit voltage limiting circuit 10 changes the output voltage of the operational amplifier A2 to the negative side and turns the diode D1
Is off. Therefore, the input limiting circuit 11
Does not limit the input voltage V _in of the operational amplifier A1, the non-inverting input terminal of the operational amplifier A1, the input voltage V _in is input as it is. When the output voltage V _OUT of the operational amplifier A1 falls below the lower limit set voltage V _LL , the lower limit voltage limiting circuit 10 increases the output voltage of the operational amplifier A2 in the positive direction. Output voltage is input voltage V
becomes larger by the forward voltage of the diode D1 (about 0.7 V) than _in, the diode D1 is turned on, the input limiting circuit 11 limits the input voltage V _in of the operational amplifier A1, the output voltage V of the operational amplifier A1 _OUT is almost the lower limit setting voltage V
Limited to _LL .

As described above, the lower limit voltage limiting circuit 10 limits the output voltage V _OUT of the operational amplifier A1 as a signal amplifier to a voltage higher than the lower limit set voltage V _{LL and} operates as a lower limit voltage limiting circuit. The output voltage V _OUT of the operational amplifier A1 is higher than the lower limit set voltage _VLL by the operational amplifier A2.
Deviation only without the offset voltage, almost no change due to the input voltage V _in. Therefore, the output voltage V _OUT can be limited to the lower limit set voltage V _LL with higher accuracy as compared with the conventional lower limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 2 is a diagram showing a second embodiment of the voltage limiting circuit of the present invention. This embodiment is a lower limit voltage limiting circuit using an inverting amplifier and a diode. It corresponds to. In the description of the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

FIG. 2 is a circuit diagram of a lower limit voltage limiting circuit 20 to which the second embodiment of the voltage limiting circuit of the present invention is applied. 2, the lower limit voltage limiting circuit 20 includes an operational amplifier A1, an operational amplifier A2, an inverting amplifier, a resistor R _in ,
A resistor Rf and a diode D1 are provided.

The operational amplifier (signal amplifier) A1 has its inverting input via a resistor R _in the terminal input voltage V _in is input, the non-inverting input terminal is grounded. The output terminal of the operational amplifier A1 is connected to the operational amplifier A1 via a resistor Rf.
Of the operational amplifier A2
Of the operational amplifier A1
Amplifies the input voltage V _in to an output voltage V _OUT.

The operational amplifier (amplifier) A2 has an output terminal connected to an inverting input terminal of the operational amplifier A1 via a diode D1, and a lower limit setting voltage _VLL is input to the inverting input terminal. I have. The operational amplifier A2 amplifies the difference voltage between the upper limit voltage V _LU and the lower limit set voltage V _LL input from the operational amplifier A1, and outputs the amplified voltage to the diode D1.

The diode D1 and the resistor R _in constitutes an input limiting circuit 21, the input limiting circuit 21 is input the output voltage of the operational amplifier A2 is a voltage V _in the diode than D1
Forward voltage when only smaller (about -0.7 V) of the diode D1 is turned on, the input voltage V _in of the operational amplifier A1
Limit the size of

That is, the lower limit voltage limiting circuit 20 outputs the signal
Operational amplifier A1, which is an inverting amplifier, is used.
The output voltage V_OUTAnd lower limit setting which is the set limit voltage
Voltage V _LLOperational amplifier A2 as an amplifier that amplifies the differential voltage
The input limiting circuit 21 uses a resistor R_inAnd diode D1
This is the lower limit voltage limiting circuit used.

According to the lower limit voltage limiting circuit 20 of this embodiment, the operation is the same as that of the lower limit voltage limiting circuit 10 of the first embodiment, but the operational amplifier A1 is used as a signal amplifier.
, A resistor R _in , and a resistor Rf. The resistor R _in is connected to an operational amplifier A1 which is an inverting amplifier.
Of the input limiting circuit 21 formed by the resistor _Rin and the diode D1.

[0037] That is, the operational amplifier A1 amplifies the input voltage V _in is the input signal and outputs, the output voltage V
_OUT is input to the non-inverting input terminal of the operational amplifier A2. The lower limit setting voltage _VLL is input to the inverting input terminal of the operational amplifier A2, and the output voltage VLL of the operational amplifier A1 is
The difference voltage between _OUT and the lower limit setting voltage _VLL is amplified and output to the inverting input terminal of the operational amplifier A1 via the diode D1. The lower limit voltage limiting circuit 20 includes an operational amplifier A1
When the output voltage V _OUT of higher than the lower limit set voltage V _LL, the output voltage of the operational amplifier A2 is provided in a state of shaking off the positive side, the diode D1 is turned off. Therefore, the input limiting circuit 21 includes the operational amplifier A1
Does not limit the input voltage V _in to, to the inverting input terminal of the operational amplifier A1, the input voltage V _in is input as it is. When the output voltage V _OUT of the operational amplifier A1 falls below the lower limit set voltage V _LL , the lower limit voltage limiting circuit 20 decreases the output voltage of the operational amplifier A2 in the negative direction. When the output voltage decreases by the forward voltage of the diode D1 than the input voltage V _in (about -0.7 V), the diode D1 is turned on, the input limiting circuit 21 limits the input voltage V _in of the operational amplifier A1, Operational amplifier A1
Output voltage V _OUT of is limited substantially to the lower limit set voltage V _LL.

As described above, the lower limit voltage limiting circuit 20 limits the output voltage V _OUT of the operational amplifier A1 as a signal amplifier to a voltage higher than the lower limit set voltage V _{LL and} operates as a lower limit voltage limiting circuit. Then, the output voltage V _OUT of the operational amplifier A1, as in the first embodiment, there is only the offset voltage of the offset of the operational amplifier A2 with respect to the lower limit set voltage V _LL, almost change with the input voltage V _in Absent. Therefore, the output voltage V _OUT can be limited to the lower limit set voltage V _LL with higher accuracy as compared with the conventional lower limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 3 is a diagram showing a third embodiment of the voltage limiting circuit of the present invention. This embodiment is a lower limit voltage limiting circuit using a non-inverting amplifier and a transistor.
This corresponds to claim 1. In the description of the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

FIG. 3 is a circuit diagram of a lower limit voltage limiting circuit 30 to which the third embodiment of the voltage limiting circuit of the present invention is applied. 3, the lower limit voltage limiting circuit 30 includes an operational amplifier A1, which is a non-inverting amplifier, an operational amplifier A2, resistors R _in , resistors Rf, Rs, a transistor Tr1, and the like.

The operational amplifier (signal amplifier) A1, the non-inverted through the resistor R _in the input terminal the input voltage V _in is input, the inverting input terminal is grounded through a resistor Rs. The output terminal of the operational amplifier A1 is connected to the inverting input terminal of the operational amplifier A1 via a resistor Rf.
Is connected to the non-inverting input terminal of the operational amplifier A2, the operational amplifier A1 amplifies the input voltage V _in the output voltage V
Output _OUT .

The operational amplifier (amplifier) A2 has an inverting input terminal to which the lower limit setting voltage _VLL is input, and an output terminal connected to the base of an NPN transistor Tr1. The operational amplifier A2 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the lower limit set voltage V _LL and outputs it to the base of the transistor Tr1.

The transistor Tr1 has its emitter connected to the power supply _Vcc and its collector connected to the non-inverting input terminal of the operational amplifier A1.

The transistor Tr 1 and the resistor R _in constitute an input limiting circuit 31.
Operational amplifier A input to the base of transistor Tr1
2 is higher than the power supply _Vcc by V
If only smaller be voltage (about 0.7 V), the transistor Tr1 is turned on, limits the magnitude of the input voltage V _in input to the operational amplifier A1.

That is, the lower limit voltage limiting circuit 30 uses the operational amplifier A1 which is a non-inverting amplifier as a signal amplifier, and amplifies the difference voltage between its output voltage V _OUT and the lower limit set voltage _VLL which is a set limit voltage. the operational amplifier A2 used, the resistance to the input limiting circuit 31 R _in the transistor Tr
1 is a lower-limit voltage limiting circuit using the circuit of FIG.

[0046] According to the lower limit voltage limiting circuit 30 of the present embodiment, the operational amplifier A1 is, the input voltage is an input signal V _in
Is amplified and output, and this output voltage V _OUT is
2 non-inverting input terminals. Operational amplifier A2
_{Has a} lower limit voltage V _LL input to its inverting input terminal, amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the lower limit voltage V _LL , and amplifies the difference voltage between the base voltage of the transistor Tr1 of the input limiting circuit 31. Output. Then, the lower limit voltage limiting circuit 30, when the output voltage V _{OU T} of the operational amplifier A1 is higher than the lower limit set voltage V _LL, the output voltage of the operational amplifier A2 is provided in a state of shaking off the positive side, the transistor Tr1 is off. Therefore, the input limiting circuit 31 outputs the input voltage V input to the operational amplifier A1.
Without limiting _in , the non-inverting input terminal of the operational amplifier A1
Input voltage V _in is input as it is. When the output voltage V _OUT of the operational amplifier A1 falls below the lower limit set voltage V _LL , the output voltage of the operational amplifier A2 decreases in the negative direction. The output voltage is higher than the power supply _Vcc by Vbe of the transistor Tr1.
When the voltage drops only, the transistor Tr1 turns on,
The input limiting circuit 31 limits the magnitude of the input voltage V _in input to the operational amplifier A1, the output voltage V _OUT of the operational amplifier A1 is limited substantially to the lower limit set voltage V _LL.

As described above, the lower limit voltage limiting circuit 30 limits the output voltage V _OUT of the operational amplifier A1 as a signal amplifier to a voltage higher than the lower limit set voltage V _{LL and} operates as a lower limit voltage limiting circuit. The output voltage V _OUT of the operational amplifier A1 is higher than the lower limit set voltage _VLL by the operational amplifier A2.
Deviation only without the offset voltage, almost no change due to the input voltage V _in. Therefore, the output voltage V _OUT can be limited to the lower limit set voltage V _LL with higher accuracy as compared with the conventional lower limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 4 is a diagram showing a fourth embodiment of a voltage limiting circuit according to the present invention. This embodiment is a lower limit voltage limiting circuit using an inverting amplifier and a transistor. It corresponds to. In the description of the present embodiment, the same components as those of the third embodiment are denoted by the same reference numerals.

FIG. 4 is a circuit diagram of a lower limit voltage limiting circuit 40 to which the fourth embodiment of the voltage limiting circuit of the present invention is applied. In FIG. 4, the lower limit voltage limiting circuit 40 includes an operational amplifier A1, an operational amplifier A2, an inverting amplifier, a resistor R _in ,
A resistor Rf and a transistor Tr1 are provided.

The operational amplifier (signal amplifier) A1 has its inverting input terminal to the resistor R _in the input signal through the input voltage V _in is input, the non-inverting input terminal is grounded. An output terminal of the operational amplifier A1 is connected to an inverting input terminal of the operational amplifier A1 via a resistor Rf, and is connected to an inverting input terminal of the operational amplifier A2.
Operational amplifier A1, resistor R _in amplifying the input voltage V _in that is input through the output of the output voltage V _OUT.

The operational amplifier (amplifier) A2 has a lower limit setting voltage _VLL input to the non-inverting input terminal of the operational amplifier A2, and the output terminal thereof is connected to an NPN type transistor Tr1.
Connected to the base. Operational amplifier A2 amplifies the voltage difference between the output voltage V _{OU T} and the lower limit setting voltage V _LL from the operational amplifier A1, and outputs to the base of the transistor Tr1.

The transistor Tr1 has its emitter connected to the power supply _Vee and its collector connected to the inverting input terminal of the operational amplifier A1. This transistor Tr1
And the resistor R _in constitute an input limiting circuit 41. The input limiting circuit 41 controls the output voltage of the operational amplifier A2 from the power supply V _ee
Vbe voltage of transistor Tr1 (about 0.7V)
If only increased, the transistor Tr1 is turned on, limits the magnitude of the input voltage V _in input to the operational amplifier A1.

That is, the lower limit voltage limiting circuit 40 uses an operational amplifier A1, which is an inverting amplifier as a signal amplifier, and amplifies the difference voltage between its output voltage V _OUT and the lower limit set voltage _VLL which is a set limit voltage. using an operational amplifier A2, the input limiting circuit 41 resistance R _in the transistor Tr
1 is a lower-limit voltage limiting circuit using the circuit of FIG.

[0054] According to the lower limit voltage limiting circuit 40 of the present embodiment, the operational amplifier A1 is, the input voltage is an input signal V _in
Is amplified and output, and this output voltage V _OUT is
2 inverting input terminals. Operational amplifier A2
_{Receives the} lower limit voltage V _{LL at} its non-inverting input terminal, and outputs the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the lower limit voltage V _LL to the base of the transistor Tr1. The lower-limit voltage limiting circuit 40 includes an operational amplifier A1
When the output voltage V _OUT of higher than the lower limit set voltage V _LL, the output voltage of the operational amplifier A2 is provided in a state of shaking off the negative side, the transistor Tr1 is in the OFF state. Therefore, the input limiting circuit 41
Does not limit the input voltage V _in is input to 1, the operational amplifier A
The first inverting input terminal, the input voltage V _in is input as it is. The lower-limit voltage limiting circuit 40 includes an operational amplifier A1
When the output voltage V _OUT of the falls below the lower limit set voltage V _LL, the output voltage of the operational amplifier A2 is increased in the positive direction, the transistor Tr1 than the output voltage supply V _ee of the operational amplifier A2 Vbe When the voltage only increases, the transistor Tr1 is turned on, the input limiting circuit 41 limits the magnitude of the input voltage V _in input to the operational amplifier A1, the output voltage V _OUT of the operational amplifier A1 is approximately the lower limit setting voltage V _LL .

As described above, the lower limit voltage limiting circuit 40 limits the output voltage V _OUT of the operational amplifier A1 as a signal amplifier to a voltage higher than the lower limit set voltage V _{LL and} operates as a lower limit voltage limiting circuit. Then, the output voltage V _OUT of the operational amplifier A1, as in the first embodiment, there is only the offset voltage of the offset of the operational amplifier A2 with respect to the lower limit set voltage V _LL, almost change with the input voltage V _in Absent. Therefore, the output voltage V _OUT can be limited to the lower limit set voltage V _LL with higher accuracy as compared with the conventional lower limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 5 is a diagram showing a fifth embodiment of the voltage limiting circuit of the present invention. This embodiment is an upper limit voltage limiting circuit using a non-inverting amplifier and a diode. This corresponds to 1. In the description of the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals.

FIG. 5 is a circuit diagram of an upper limit voltage limiting circuit 50 to which the fifth embodiment of the voltage limiting circuit of the present invention is applied. 5, the upper limit voltage limiting circuit 50 includes an operational amplifier A1, an operational amplifier A3, a resistor R _in , a resistor Rf, a resistor Rs, a diode D2, and the like, which are non-inverting amplifiers.

[0058] The operational amplifier (signal amplifier) A1, the non-inverted through the resistor R _in the input terminal the input voltage V _in is input, the inverting input terminal is grounded through a resistor Rs. An output terminal of the operational amplifier A1 is connected to an inverting input terminal of the operational amplifier A1 via a resistor Rf, and is connected to an inverting input terminal of the operational amplifier A3.
Operational amplifier A1, an input voltage V _in is input via the resistor R _in and amplifies and outputs the output voltage V _OUT.

The operational amplifier (amplifier) A3 has its non-inverting input terminal supplied with the upper limit voltage V _LU, and the output terminal of the operational amplifier A3 is connected to the non-inverting input terminal of the operational amplifier A1 via the diode D2. It is connected. The operational amplifier A3 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the upper limit voltage V _LU and outputs the amplified voltage to the diode D2.

[0060] Diodes D2 and the resistor R _in constitutes an input limiting circuit 51, the input limiting circuit 51, an input output voltage of the operational amplifier A3 the voltage V _in the diode than D2
If only smaller forward voltage of the diode D2 is turned on, via a resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1.

That is, the upper limit voltage limiting circuit 50 uses an operational amplifier A1 which is a non-inverting amplifier as a signal amplifier and amplifies the difference voltage between its output voltage V _OUT and the upper limit voltage V _LU which is a set limit voltage. The operational amplifier A3 is used for the input limiting circuit 51 and the resistor _Rin and the diode D2
Is an upper-limit voltage limiting circuit using the same.

[0062] According to the upper limit voltage limiting circuit 50 of the present embodiment amplifies the input voltage V _in operational amplifier A1 is input signal is output as the output voltage V _OUT, the output voltage V
_OUT is input to the inverting input terminal of the operational amplifier A3. The operational amplifier A3 receives the upper limit voltage V _{LU at} its non-inverting input terminal, amplifies the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the upper limit voltage V _LU , and outputs the amplified voltage to the diode D2. Then, the upper limit voltage limiting circuit 50
Means that the output voltage V _OUT of the operational amplifier A1 is equal to the upper limit voltage V
If it is smaller than _LU, the output voltage of the operational amplifier A3 becomes
It is in a state of swinging out to the positive side, and the diode D2
Is off. Therefore, the input limiting circuit 51
It does not limit the input voltage V _in input to the operational amplifier A1, the non-inverting input terminal of the operational amplifier A1, the input voltage V
_in is input as is. The upper limit voltage limiting circuit 50
Means that the output voltage V _OUT of the operational amplifier A1 is equal to the upper limit voltage V
When raised from _LU is calculated output voltage of the amplifier A3 is increased in the negative direction, than the forward voltage of the output voltage is the input voltage V _in from the diode D2 of the operational amplifier A3 (about 0.7 V) becomes smaller, the diode D2 is turned on, the input limiting circuit 51 limits the magnitude of the input voltage V _in input to the operational amplifier A1, the output voltage V _OUT of the operational amplifier A1 is approximately the upper limit limit voltage V _LU Is limited to

As described above, the upper limit voltage limiting circuit 50 limits the output voltage V _OUT of the operational amplifier A1 as a signal amplifier to a voltage lower than the upper limit voltage V _LU , and operates as an upper limit voltage limiting circuit. The output voltage V _OUT of the operational amplifier A1 is higher than the upper limit voltage V _LU by the operational amplifier A3.
Deviation only without the offset voltage, almost no change due to the input voltage V _in. Therefore, the output voltage V _OUT can be more accurately limited to the upper limit voltage V _LU than a conventional upper limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 6 is a diagram showing a sixth embodiment of the voltage limiting circuit according to the present invention. This embodiment is an upper limit voltage limiting circuit using an inverting amplifier and a diode. It corresponds to. In the description of this embodiment, the same components as those of the fifth embodiment are denoted by the same reference numerals.

FIG. 6 is a circuit diagram of an upper limit voltage limiting circuit 60 to which a sixth embodiment of the voltage limiting circuit according to the present invention is applied. 6, an upper limit voltage limiting circuit 60 includes an operational amplifier A1, an operational amplifier A3, an inverting amplifier, a resistor R _in ,
A resistor Rf and a diode D2 are provided.

[0066] The operational amplifier (signal amplifier) A1 has its inverting input via a resistor R _in the terminal input voltage V _in is input, the non-inverting input terminal is grounded. The output of the operational amplifier A1 is fed back to the inverting input terminal of the operational amplifier A1 via a resistor Rf.
Connected to the non-inverting input terminal of Operational amplifier A1
The input voltage V _in is input via the resistor R _in and amplifies and outputs the output voltage V _OUT.

The operational amplifier (amplifier) A3 has its upper limit voltage V _LU input to its inverting input terminal.
1 inverting input terminal. Operational amplifier A3
Amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the upper limit voltage V _LU and outputs it to the diode D2.

[0068] The diode D2 and the resistor R _in constitutes an input limiting circuit 61, the input limiting circuit 61, a forward voltage (approximately 0 of the output voltage is the input voltage V _in the diode than D2 of operational amplifier A3 .7V)
Diode D2 is turned on, limits the magnitude of the input voltage V _in input to the operational amplifier A1.

That is, the upper limit voltage limiting circuit 60 uses an operational amplifier A1 which is an inverting amplifier as a signal amplifier and amplifies the difference voltage between the output voltage V _OUT and the upper limit voltage V _LU which is a set limit voltage. Using an operational amplifier A3, a resistor _Rin and a diode D2 are connected to the input limiting circuit 61.
Is an upper-limit voltage limiting circuit using the same.

[0070] According to the upper limit voltage limiting circuit 60 of the present embodiment amplifies the input voltage V _in operational amplifier A1 is input signal is output as the output voltage V _OUT, the output voltage V
_OUT is input to the non-inverting input terminal of the operational amplifier A3. The upper limit voltage V _LU is input to the inverting input terminal of the operational amplifier A3, and the output voltage V _LU of the operational amplifier A1 is
_The voltage difference between _OUT and the upper limit voltage V _LU is amplified and output to the diode D2. Then, the upper limit voltage limiting circuit 60
When the output voltage V _OUT of the operational amplifier A1 is lower than the upper limit voltage V _LU , the output voltage of the operational amplifier A3 is turned to the negative side, and the diode D2 is off. Accordingly, the input limiting circuit 61 does not limit the input voltage V _in input to the operational amplifier A1, the inverting input terminal of the operational amplifier A1, the input voltage V _in is input as it is. When the output voltage V _OUT of the operational amplifier A1 rises above the upper limit voltage V _LU , the output voltage of the operational amplifier A3 increases in the positive direction. forward voltage of the diode D2 than the output voltage is the input voltage V _in (about 0.7 V)
If only increases, the diode D2 is turned on, the input voltage V _in by the input limiting circuit 61 is input to the operational amplifier A1
And the output voltage V of the operational amplifier A1 is limited.
_OUT is substantially limited to the upper limit voltage _VLU .

As described above, the upper limit voltage limiting circuit 60 limits the output voltage V _OUT of the operational amplifier A1 which is a signal amplifier to a voltage lower than the upper limit voltage V _LU , and operates as an upper limit voltage limiting circuit. The output voltage V _OUT of the operational amplifier A1 is higher than the upper limit voltage V _LU by the operational amplifier A3.
Deviation only without the offset voltage, almost no change due to the input voltage V _in. Therefore, the output voltage V _OUT can be more accurately limited to the upper limit voltage V _LU than a conventional upper limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 7 is a diagram showing a seventh embodiment of the voltage limiting circuit according to the present invention. This embodiment is an upper limit voltage limiting circuit using a non-inverting amplifier and a diode. This corresponds to 1. In the description of this embodiment, the same components as those of the fifth embodiment are denoted by the same reference numerals.

FIG. 7 is a circuit diagram of an upper limit voltage limiting circuit 70 to which the seventh embodiment of the voltage limiting circuit of the present invention is applied. 7, the upper-limit voltage limiting circuit 70 includes an operational amplifier A1, an operational amplifier A3, a resistor R _in , a resistor Rf, a resistor Rs, a transistor Tr2, and the like, which are non-inverting amplifiers.

[0074] The operational amplifier (signal amplifier) A1, the non-inverted through the resistor R _in the input terminal the input voltage V _in is input, an inverting input terminal is grounded through a resistor Rs. The output of the operational amplifier A1, with is connected to the inverting input terminal of the operational amplifier A1 through a resistor Rf, it is connected to the non-inverting input terminal of the operational amplifier A3, operational amplifier A1, via a resistor R _in Input voltage V
_a is amplified and output as an output voltage V _OUT .

The operational amplifier (amplifier) A3 has its upper limit voltage V _LU input at its inverting input terminal, and its output connected to the base of a PNP transistor Tr2. The transistor Tr2 has a power supply V
_ee is input, and its collector is connected to the non-inverting input terminal of the operational amplifier A1. The operational amplifier A3 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the upper limit voltage V _LU and outputs the amplified voltage to the base of the transistor Tr2.

The transistor Tr 2 and the resistor R _in constitute an input limiting circuit 71.
Limit the output voltage of the operational amplifier A3 is increased by Vbe voltage of transistor Tr2 than the power supply V _ee, the transistor Tr2 is turned on, the magnitude of the input voltage V _in via the resistor R _in is input to the operational amplifier A1 I do.

That is, the upper limit voltage limiting circuit 70 uses the operational amplifier A1 which is a non-inverting amplifier as a signal amplifier, and amplifies the difference voltage between the output voltage V _OUT and the upper limit voltage V _LU which is a set limit voltage. The operational amplifier A3 is used for the input limiting circuit 71 and the resistor _Rin and the transistor T
This is an upper limit voltage limiting circuit using r2.

[0078] According to the upper limit voltage limiting circuit 70 of the present embodiment amplifies the input voltage V _in operational amplifier A1 is input signal is output as the output voltage V _OUT, the output voltage V
_OUT is input to the non-inverting input terminal of the operational amplifier A3. The upper limit voltage V _LU is input to the inverting input terminal of the operational amplifier A3, and the output voltage V _LU of the operational amplifier A1 is
The difference voltage between _OUT and the upper limit voltage V _LU is amplified and output to the non-inverting input terminal of the operational amplifier A1 via the transistor Tr2. When the output voltage V _OUT of the operational amplifier A1 is lower than the upper limit voltage V _LU , the upper limit voltage limiting circuit 70 turns off the output voltage of the operational amplifier A3 to the negative side. Is off. Accordingly, the input limiting circuit 71 does not limit the input voltage V _in input to the operational amplifier A1, the non-inverting input terminal of the operational amplifier A1, the input voltage V _in is input as it is. When the output voltage V _OUT of the operational amplifier A1 rises above the upper limit voltage V _LU , the output voltage of the operational amplifier A3 increases in the positive direction. When the output voltage increases by Vbe voltage of transistor Tr2 than the power supply V _ee, the transistor Tr2 is turned on, the input limiting circuit 71
There limits the magnitude of the input voltage V _in input to the operational amplifier A1, the output voltage V _OUT of the operational amplifier A1 is limited to approximately the upper limit limit voltage V _LU.

As described above, the upper limit voltage limiting circuit 70 limits the output voltage V _OUT of the operational amplifier A1 as a signal amplifier to a voltage lower than the upper limit voltage V _LU , and operates as an upper limit voltage limiting circuit. The output voltage V _OUT of the operational amplifier A1 is higher than the upper limit voltage V _LU by the operational amplifier A3.
Deviation only without the offset voltage, almost no change due to the input voltage V _in. Therefore, the output voltage V _OUT can be more accurately limited to the upper limit voltage V _LU than a conventional upper limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 8 is a diagram showing an eighth embodiment of the voltage limiting circuit according to the present invention. This embodiment is an upper limit voltage limiting circuit using an inverting amplifier and a diode. It corresponds to. In the description of this embodiment, the same components as those of the seventh embodiment are denoted by the same reference numerals.

FIG. 8 is a circuit diagram of an upper limit voltage limiting circuit 80 to which the eighth embodiment of the voltage limiting circuit of the present invention is applied. In FIG. 8, the upper limit voltage limiting circuit 80 includes an operational amplifier A1, an operational amplifier A3, an inverting amplifier, a resistor R _in ,
A resistor Rf and a transistor Tr2 are provided.

[0082] The operational amplifier (signal amplifier) A1 has its inverting input via a resistor R _in the terminal input voltage V _in is input, the non-inverting input terminal is grounded. The output of the operational amplifier A1 is fed back to the inverting input terminal of the operational amplifier A1 via a resistor Rf.
The operational amplifier A1 is connected to the inverting input terminal of
The input voltage V _in via the resistor R _in is input to the amplifier,
Output as output voltage V _OUT .

The operational amplifier (amplifier) A3 has its non-inverting input terminal supplied with the upper limit voltage V _LU, and the output of the operational amplifier A3 is connected to the base of a PNP transistor Tr2. The power supply _Vcc is input to the emitter of the transistor Tr2, and the collector is connected to the inverting input terminal of the operational amplifier A1. Operational amplifier A
3 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the upper limit voltage V _LU and outputs the amplified voltage to the base of the transistor Tr2.

The transistor Tr 2 and the resistor R _in constitute an input limiting circuit 81.
When the output voltage of the operational amplifier A3 becomes lower than the power supply _Vcc by Vbe of the transistor Tr2, the transistor Tr
2 is turned on through the resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1.

That is, the upper limit voltage limiting circuit 80 uses an operational amplifier A1 which is an inverting amplifier as a signal amplifier, and amplifies the difference voltage between its output voltage V _OUT and the upper limit voltage V _LU which is a set limit voltage. Using an operational amplifier A3, a resistor R _in and a transistor T
This is an upper limit voltage limiting circuit using r2.

[0086] According to the upper limit voltage limiting circuit 80 of the present embodiment amplifies the input voltage V _in operational amplifier A1 is input signal is output as the output voltage V _OUT, the output voltage V
_OUT is input to the inverting input terminal of the operational amplifier A3. The operational amplifier A3 has its non-inverting input terminal _supplied with the upper limit voltage V _LU , amplifies the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the upper limit voltage V _{LU, and} performs an operation via the transistor Tr2. Output to the inverting input terminal of the amplifier A1. When the output voltage V _OUT of the operational amplifier A1 is smaller than the upper limit voltage V _LU , the upper limit voltage limiting circuit 80 turns off the output voltage of the operational amplifier A2 to the positive side. Is off. Therefore, the input limiting circuit 81 does not limit the input voltage V _in input to the operational amplifier A1, the inverting input terminal of the operational amplifier A1, the input voltage V _in is input as it is. When the output voltage V _OUT of the operational amplifier A1 rises above the upper limit voltage V _LU , the output voltage of the operational amplifier A3 increases in the negative direction. When the output voltage becomes lower than the power supply _Vcc by Vbe of the transistor Tr2, the transistor Tr2 turns on and the input limiting circuit 81 sets the resistance R
via _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1, the output voltage V _OUT of the operational amplifier A1,
It is almost limited to the upper limit voltage _VLU .

As described above, the upper limit voltage limiting circuit 80 limits the output voltage V _OUT of the operational amplifier A1 as a signal amplifier to a voltage lower than the upper limit voltage V _{LU and} operates as an upper limit voltage limiting circuit. The output voltage V _OUT of the operational amplifier A1 is higher than the upper limit voltage V _LU by the operational amplifier A3.
Deviation only without the offset voltage, almost no change due to the input voltage V _in. Therefore, the output voltage V _OUT can be more accurately limited to the upper limit voltage V _LU than a conventional upper limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 9 is a diagram showing a specific example of the third embodiment shown in FIG. 3, and shows a lower limit voltage limiting circuit using a non-inverting amplifier, an input limiting circuit using a transistor and an input resistor. 90.

In FIG. 9, the lower limit voltage limiting circuit 90
Transistors Q1-Q9, transistor Q10, transistors Q20-Q29, resistor R _in , resistor Rs, resistor R
f, resistors R10, R20, R21 and a capacitor C1.

The transistors Q1 to Q9 and the capacitor C1
The non-inverting operational amplifier 91 is composed of the operational amplifier as the operational amplifier A1 in FIG. 3 and the resistors Rs and Rf.
An operational amplifier 92 as the operational amplifier A2 in FIG. 3 is constituted by 20, R21. The resistor R10 and the transistor Q10 are connected to a non-inverting operational amplifier 91 and an operational amplifier 92.
The input limiting circuit 93 as the input limiting circuit 31 in FIG. 3 is configured by the resistor R _in , the transistor Tr1, and the transistor Q29. The transistor R1 of the non-inverting operational amplifier 91 has a resistor R _in
Input voltage V _in through a is input, the non-inverting operational amplifier 9
1 amplifies the input voltage V _in to an output voltage V _OUT.

The operational amplifier 92 receives the output voltage V _OUT of the non-inverting operational amplifier 91 and the lower limit setting voltage V _LL . The operational amplifier 92 outputs the output of the non-inverting operational amplifier 91. The difference voltage between the output voltage V _OUT and the lower limit set voltage V _LL is amplified and output to the base of the transistor Tr1. Note that the transistor Q25, the transistor Q26, and the transistor Q29 are
The resistor R20, the transistor Q21, and the transistor Q24 prevent the transistor Q22 and the transistor Q23 from being damaged due to an excessive voltage applied between the base and the emitter of the transistor Q22. It is an element for preventing.

That is, the lower limit voltage limiting circuit 90 uses an operational amplifier 91 which is a non-inverting amplifier as a signal amplifier, and amplifies the difference voltage between its output voltage V _OUT and the lower limit set voltage _VLL which is a set limit voltage. An operational amplifier 92 is used for the input limiting circuit 93 and a resistor R _in and a transistor Tr are used for the input limiting circuit 93.
1 is a lower limit voltage limiting circuit using a transistor Q29 and a transistor Q29.

[0093] According to the lower limit voltage limiting circuit 90 of the present embodiment, the non-inverting operational amplifier 91 amplifies the input voltage V _in is the input signal and outputs, the output voltage V _OUT is input to the operational amplifier 92 ing. The operational amplifier 92, the lower limit setting voltage V _LL is input, the operational amplifier 92, the output voltage V _OUT and the lower limit setting voltage V _LL of the non-inverting operational amplifier 91
Is output to the base of the transistor Tr1.
When the output voltage V _OUT of the operational amplifier 91 is higher than the lower-limit set voltage V _LL , the lower-limit voltage limiting circuit 90 sets the output voltage of the operational amplifier 92 to the positive side, and the transistor Tr1 Is off.
Therefore, the input limiting circuit 93 includes the non-inverting operational amplifier 9
Does not limit the input voltage V _in is input to 1, the non-inverting operational amplifier 91, the input voltage V _in is input as it is. When the output voltage V _OUT of the non-inverting operational amplifier 91 falls below the lower limit setting voltage V _LL , the lower limit voltage limiting circuit 90 decreases the output voltage of the operational amplifier 92 in the negative direction,
When the output voltage of the operational amplifier 92 becomes lower than the power supply _Vcc by the Vbe voltage of the transistor Tr1, the transistor Tr1 turns on, amplifies the output of the operational amplifier 92, and outputs it to the non-inverting operational amplifier 91. Therefore, to limit the magnitude of the input voltage V _in the input limiting circuit 93 is input to the non-inverting operational amplifier 91, the output voltage V _OUT of the operational amplifier 91 is limited approximately to the lower limit set voltage V _LL.

As described above, the lower limit voltage limiting circuit 90 controls the output voltage V _OUT of the non-inverting operational amplifier 91 which is a signal amplifier.
To a voltage higher than the lower limit setting voltage _VLL , and operates as a lower limit voltage limiting circuit. The output voltage V _OUT of the operational amplifier A1 is only shifted from the lower limit set voltage V _LL by the offset voltage of the operational amplifier A2.
There is almost no change due to _in . Therefore, the output voltage V _OUT can be limited to the lower limit set voltage V _LL with higher accuracy as compared with the conventional lower limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 10 is a diagram showing a specific example of the seventh embodiment shown in FIG. 7, and shows an upper limit voltage limiting circuit using a non-inverting amplifier, and an input limiting circuit using transistors and input resistors. 100. In the description of this embodiment, the same components as those shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 10, upper limit voltage limiting circuit 100
Are transistors Q1 to Q9, transistor Q10, transistors Q30 to Q39, resistor R _in , resistor Rs, resistor Rf, resistors R10, R30, R31, and capacitor C1.
Etc. are provided.

The transistors Q1 to Q9 and the capacitor C1
A non-inverting operational amplifier 101 is constituted by the operational amplifier as the operational amplifier A1 in FIG. 7 and the resistors Rs and Rf, and the transistors Q30 to Q38 and the resistors R30 and R31 form the operational amplifier A3 in FIG. An operational amplifier 102 is configured. Resistor R10 and the transistor Q10 and the transistor Q11 is a common bias circuit of the non-inverting operational amplifier 101 and operational amplifier 102, resistor R _in, an input limiting circuit 103 as an input limiting circuit 71 in FIG. 7 by the transistor Tr2 and the transistor Q39 Is configured. The transistor Q1 of the non-inverting operational amplifier 91, input via the resistor R _in the voltage V _in
There are input, a non-inverting operational amplifier 91 amplifies the input voltage V _in to an output voltage V _OUT. Operational amplifier 101
, The output voltage V _OUT of the non-inverting operational amplifier 91 and the upper limit voltage V _LU are input, and the operational amplifier 101 is connected to the output voltage V _OUT output from the non-inverting operational amplifier 91 by the upper limit. The difference voltage from the limit voltage V _LU is amplified and output to the base of the transistor Tr2. The transistor Q35, the transistor Q36, and the transistor Q39 are elements for avoiding the saturation of the transistor Q38, and the resistor R30, the transistor Q31, and the transistor Q34 receive an excessive voltage between the base and the emitter of the transistor Q32 and the transistor Q33. This is an element for preventing the transistors Q32 and Q33 from being destroyed.

That is, the upper limit voltage limiting circuit 100 uses an operational amplifier 91 which is a non-inverting amplifier as a signal amplifier, and amplifies the difference voltage between its output voltage V _OUT and the set upper limit voltage V _LU. Operational amplifier 10
Using 1 is an upper limit voltage limiting circuit using a resistor R _in the transistor Tr2 and the transistor Q39 to the input limiting circuit 102.

[0099] According to the upper limit voltage limiting circuit 100 of this embodiment, the non-inverting operational amplifier 91 amplifies the input voltage V _in is the input signal and outputs, the output voltage V _OUT is input to the operational amplifier 101 ing. The operational amplifier 101 is inputted upper limit voltage V _LU, amplifies the output voltage V _OUT and the differential voltage between the upper limit voltage V _LU of the operational amplifier 91,
The signal is output to the operational amplifier 91 via the transistor Tr2. The upper-limit voltage limiting circuit 100 includes the operational amplifier 9
When the output voltage V _{OUT of} No. 1 is smaller than the upper limit voltage V _LU , the output voltage of the operational amplifier 101 is in a state of swinging to the positive side, and the transistor Tr2 is in an off state. Accordingly, the input limiting circuit 102 does not limit the input voltage V _in input to the non-inverting operational amplifier 91,
The operational amplifier 91, the input voltage V _in is input as it is. The upper limit voltage limiting circuit 100 includes an operational amplifier 91
When the output voltage V _OUT of rose than the upper limit voltage limit V _LU, the output voltage of the operational amplifier 101, increases in the negative direction, the transistor Tr2 than the output voltage supply V _ee of the operational amplifier 101 Vbe When the voltage only decreases, the transistor Tr2 is turned on to limit the magnitude of the input voltage V _in the input limiting circuit 102 is input to the non-inverting operational amplifier 91, the output voltage V _OUT of the operational amplifier 91 is approximately the upper limit restriction Limited to voltage V _LU .

As described above, the upper limit voltage limiting circuit 100
The output voltage V _OUT of the operational amplifier 91 which is a signal amplifier is
The voltage is restricted to a voltage lower than the upper limit voltage V _{LU, and the} circuit operates as an upper voltage limit circuit. The output voltage V _OUT of the operational amplifier A1 is higher than the upper limit voltage V _LU by the operational amplifier A1.
Deviation only without the offset voltage of 3, almost no change due to the input voltage V _in. Therefore, the output voltage V _OUT can be more accurately limited to the upper limit voltage V _LU than a conventional upper limit voltage limiting circuit including a resistor and a diode. In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 11 is a diagram showing a ninth embodiment of a voltage limiting circuit according to the present invention. This embodiment is an upper / lower limit voltage limiting circuit using a non-inverting amplifier and a diode. This corresponds to item 2.

FIG. 11 is a circuit diagram of an upper / lower limit voltage limiting circuit 110 to which the ninth embodiment of the voltage limiting circuit of the present invention is applied. In FIG. 11, upper and lower limit voltage limiting circuit 110
Are operational amplifiers A1 and A, which are non-inverting amplifiers.
2, A3, a resistor R _in , a resistor Rf, a resistor Rs, diodes D1 and D2, and the like.

[0103] The operational amplifier (signal amplifier) A1, the non-inverted through the resistor R _in the input terminal the input voltage V _in is input, the inverting input terminal is grounded through a resistor Rs. The output of the operational amplifier A1 is connected to the inverting input terminal of the operational amplifier A1 via a resistor Rf.
It is connected to the inverting input terminal and the inverting input terminal of the operational amplifier A3 of the operational amplifier A2, the operational amplifier A1 amplifies the input voltage V _in is input via the resistor R _in, an output as the output voltage V _OUT I do.

An operational amplifier (first amplifier) A2 has a lower limit voltage V _LL input to its non-inverting input terminal,
Its output terminal is connected to an operational amplifier A via a diode D1.
1 non-inverting input terminal. Operational amplifier A2
Amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the lower limit setting voltage V _LL and outputs it to the diode D1.

The operational amplifier (second amplifier) A3 has an upper limit voltage V _LU input to its non-inverting input terminal,
Its output terminal is connected to an operational amplifier A via a diode D2.
1 non-inverting input terminal. Operational amplifier A3
Amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the upper limit voltage V _LU and outputs it to the diode D2.

[0106] The diode D1 and the resistor R _in constitutes an input limiting circuit (first input limiting circuit) 111,
The input limiting circuit 111 determines that the output voltage of the operational amplifier A2 is V
_When the forward voltage (about 0.7 V) of the diode D1 becomes larger than _LL / (1 + Rf / Rs), the diode D1
There is turned on through the resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1.

The diode D2 and the resistor R _in constitute an input limiting circuit (second input limiting circuit) 112.
The input limiting circuit 112 determines that the output voltage of the operational amplifier A3 is V
_When the forward voltage (about 0.7 V) of the diode D2 becomes smaller than _LU / (1 + Rf / Rs), the diode D2
There is turned on through the resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1.

That is, the upper and lower limit voltage limiting circuit 110
Operational amplifier A1 which is a non-inverting amplifier as a signal amplifier
The first amplifier that amplifies the difference voltage between the output voltage V _OUT and the lower limit set voltage V _{LL as} the set limit voltage is connected to the operational amplifier A2 and the output voltage V _OUT and the upper limit voltage V _{LU as the} set limit voltage. Using an operational amplifier A3 as a second amplifier for amplifying the difference voltage between the first and second input limiting circuits 1
This is an upper / lower limit voltage limiting circuit using resistors R _in and diodes D 1 and D 2 for 11 and 112.

Upper / lower limit voltage limiting circuit 110 of the present embodiment
According to the above, the operational amplifier A1 outputs the input voltage V
amplifying the _in output as the output voltage V _OUT, the output voltage V _OUT is input to the inverting input terminal of the inverting input terminal and an operational amplifier A3 of the operational amplifier A2. Operational amplifier A
Reference numeral 2 denotes a non-inverting input terminal to which the lower limit setting voltage V _LL is input, amplifies the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the lower limit setting voltage V _LL , and amplifies the operational amplifier A1 via the diode D1. Output to the non-inverting input terminal. The operational amplifier A3 has an upper limit voltage V at its non-inverting input terminal.
_LU is input and the output voltage V _{OUT of the} operational amplifier A1
And the upper limit voltage V _LU and the diode D
2 to the non-inverting input terminal of the operational amplifier A1. When the output voltage V _OUT of the operational amplifier A1 is higher than the lower limit set voltage V _{LL and} lower than the upper limit voltage V _LU , the output voltage of the operational amplifier A2 becomes lower. To the operational amplifier A3
Is in a state of swinging to the positive side, and the diodes D1 and D2 are both off. Accordingly, the input limiting circuit 111 and the input limiting circuit 112 does not limit the input voltage V _in input to the operational amplifier A1, the non-inverting input terminal of the operational amplifier A1, the input voltage V _in is input as it is. When the output voltage V _OUT of the operational amplifier A1 falls below the lower limit set voltage V _LL , the output voltage of the operational amplifier A3 does not change while being swung to the positive side. When the output voltage of the amplifier A2 increases in the positive direction and the output voltage of the operational amplifier A2 becomes larger than V _LL / (1 + Rf / Rs) by the forward voltage of the diode D1 (about 0.7 V), the diode D1 Turns on and the input limiting circuit 1
11 through a resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1, the output voltage V _OUT is limited to be approximately the lower limit set voltage V _LL. Further, when the output voltage V _OUT of the operational amplifier A1 rises above the upper limit voltage V _LU , the output voltage of the operational amplifier A2 does not change while being swung to the negative side. The output voltage of the amplifier A3 decreases in the negative direction, and the output voltage of the operational amplifier A3 becomes _VLU / (1 + Rf).
/ Rs) rather than the forward voltage of the diode D2 (about 0.7
If only V) decreases, the diode D2 is turned on, to limit the magnitude of the input voltage V _in the input limiting circuit 112 is input via the resistor R _in the operational amplifier A1, the output voltage V
_OUT is limited to approximately the upper limit voltage _VLU .

As described above, the upper and lower limit voltage limiting circuit 110
Is the output voltage V _OUT of the operational amplifier A1, which is a signal amplifier.
To a voltage between the upper limit voltage V _LU and the lower limit voltage V _LL , and operates as an upper / lower voltage limit circuit. And
The output voltage V _{OU T} of the operational amplifier A1, the lower limit setting voltage V _LL
With respect to the upper limit voltage V _LU only by the offset voltage of the operational amplifier A2.
Deviation only without the offset voltage, further, almost no change due to the input voltage V _in. Therefore, compared to the conventional upper and lower limit voltage limiting circuit using resistors and diodes,
The output voltage V _OUT can be accurately restricted between the lower limit set voltage _VLL and the upper limit voltage _VLU . In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 12 is a circuit diagram showing a tenth embodiment of the voltage limiting circuit according to the present invention.
FIG. 3 is a diagram showing an embodiment of the present invention, and this embodiment is an upper / lower limit voltage limiting circuit using an inverting amplifier and a diode, and corresponds to claim 2.

FIG. 12 is a circuit diagram showing a tenth embodiment of the voltage limiting circuit according to the present invention.
10 is a circuit diagram of an upper / lower limit voltage limiting circuit 120 to which the embodiment of FIG. In FIG. 12, upper and lower limit voltage limiting circuit 12
0 is an operational amplifier A1, which is an inverting amplifier, and an operational amplifier A
2, A3, resistance R _in , resistance Rf, and diodes D1, D
2 and so on.

[0113] The operational amplifier (signal amplifier) A1 has its inverting input via a resistor R _in the terminal input voltage V _in is input, the non-inverting input terminal is grounded. The output of the operational amplifier A1 is fed back to the inverting input terminal via the resistor Rf, and is connected to the non-inverting input terminal of the operational amplifier A2 and the non-inverting input terminal of the operational amplifier A3. Inverted amplifier constituted by an operational amplifier A1 and resistor R _in and resistor Rf, operational amplifier A1, an input voltage V _in
And outputs the output voltage V _OUT .

The operational amplifier (first amplifier) A2 has its inverting input terminal supplied with the lower limit set voltage _VLL , and its output connected to the inverting input terminal of the operational amplifier A1 via a diode D1. I have. The operational amplifier A2 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the lower limit set voltage V _LL and outputs it to the diode D1.

The operational amplifier (second amplifier) A3 has its upper limit voltage V _LU input at its inverting input terminal, and its output connected to the inverting input terminal of the operational amplifier A1 via a diode D2. I have. The operational amplifier A3 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the upper limit voltage V _LU and outputs the amplified voltage to the diode D2. The resistor R _in determines the closed-loop gain of the inverting amplifier constituted by the operational amplifier A1, the resistor R _in and the resistor Rf, and also functions as a part of the input limiting circuits 121 and 122. That is, the diode D1 and the resistor R _in the input limiting circuit constitute a (first input limiting circuit) 121, an input limiting circuit 121, the output voltage of the operational amplifier A2 is the input voltage V _in the diode D1 than If only smaller forward voltage (about 0.7 V), the diode D1 is turned on, via a resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1. The diode D2 and the resistor _Rin are connected to an input limiting circuit (second input limiting circuit) 122.
The input limiting circuit 122 includes an operational amplifier A
When third output voltage increases by the forward voltage of the diode D2 (about 0.7 V) than the input voltage V _in, the diode D2 is turned on, the input voltage V through a resistor R _in is input to the operational amplifier A1 to limit the size of the _in.

That is, the upper / lower limit voltage limiting circuit 120
An operational amplifier A1 which is an inverting amplifier as a signal amplifier is
Used and its output voltage V_OUTAnd the lower limit setting
Constant voltage V_LLOperational amplification in the first amplifier that amplifies the differential voltage
A2 and its output voltage V_{OU T}And set limit voltage
Limit voltage V_LUCalculated by the second amplifier that amplifies the differential voltage
Using the amplifier A3, the first and second input limiting circuits 12
1 and 122 have resistors R_inAnd diode D1 and diode
This is an upper and lower limit voltage limiting circuit using D2.

Upper / lower limit voltage limiting circuit 120 of the present embodiment
According to the above, the operational amplifier A1 outputs the input voltage V
amplifying the _in output as the output voltage V _OUT, the output voltage V _OUT is input to the non-inverting input terminal of the non-inverting input terminal and an operational amplifier A3 of the operational amplifier A2. The operational amplifier A2 has a lower limit set voltage V _LL input to its inverting input terminal, amplifies the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the lower limit set voltage V _LL , and outputs the operational amplifier via a diode D1. Output to the inverting input terminal of A1. The operational amplifier A3 has an inverting input terminal connected to the upper limit voltage V _LU.
, And amplifies the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the upper limit voltage V _LU , and
To the inverting input terminal of the operational amplifier A1. When the output voltage V _OUT of the operational amplifier A1 is higher than the lower limit set voltage V _{LL and} lower than the upper limit voltage V _LU , the output voltage of the operational amplifier A2 becomes higher. And the output voltage of the operational amplifier A3 is shifted to the negative side.
1 and the diode D2 are both off. Therefore, the input limiting circuit 121 and the input limiting circuit 122
It does not limit the input voltage V _in input to the operational amplifier A1,
The operational amplifier A1 is input the input voltage V _in is intact, the resistor Rf, only current determined by the input voltage V _in and the resistor R _in flows. Consequently, for an input voltage V _in, it is amplified by the gain provisions. When the output voltage V _OUT of the operational amplifier A1 falls below the lower limit set voltage V _LL , the upper / lower limit voltage limiting circuit 120 operates the operational amplifier A3.
Output voltage of the operational amplifier A2 decreases in the negative direction, while the output voltage of the operational amplifier A2 decreases in the negative direction. 7V), the diode D1 is turned on, and a current flows through the diode D1 and the resistor Rf so that the output voltage V _OUT of the operational amplifier A1 becomes the lower limit set voltage _VLL. The input terminal is limited so as to be almost equal to the lower limit set voltage _VLL . Further, when the output voltage V _OUT of the operational amplifier A1 rises above the upper limit voltage V _LU , the output voltage of the operational amplifier A2 does not change while being swung to the positive side. The output voltage of the amplifier A3 increases in the positive direction.
V) When it becomes larger, the diode D2 turns on, and a current flows through the diode D2 and the resistor Rf so that the output voltage V _OUT of the operational amplifier A1 becomes the upper limit voltage V _LU, and the non-inverting input of the operational amplifier A1 , Output voltage V
_OUT is limited to approximately the upper limit voltage _VLU .

As described above, the upper and lower limit voltage limiting circuit 120
Is the output voltage V _OUT of the operational amplifier A1, which is a signal amplifier.
To a voltage between the upper limit voltage V _LU and the lower limit voltage V _LL , and operates as an upper / lower voltage limit circuit. And
The output voltage V _{OU T} of the operational amplifier A1, the lower limit setting voltage V _LL
With respect to the upper limit voltage V _LU only by the offset voltage of the operational amplifier A2.
Deviation only without the offset voltage, further, almost no change due to the input voltage V _in. Therefore, compared to the conventional upper and lower limit voltage limiting circuit using resistors and diodes,
The output voltage V _OUT can be accurately restricted between the lower limit set voltage _VLL and the upper limit voltage _VLU . In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 13 shows an eleventh embodiment of the voltage limiting circuit according to the present invention.
FIG. 7 is a diagram showing an embodiment of the present invention, and this embodiment is an upper / lower limit voltage limiting circuit using a non-inverting amplifier and a transistor, and corresponds to claim 2.

FIG. 13 shows an eleventh embodiment of the voltage limiting circuit of the present invention.
FIG. 5 is a circuit diagram of an upper / lower limit voltage limiting circuit 130 to which the embodiment is applied. Referring to FIG.
Reference numeral 0 includes an operational amplifier A1, which is a non-inverting amplifier, operational amplifiers A2 and A3, a resistor R _in , a resistor Rf, a resistor Rs, and transistors Tr1 and Tr2.

[0121] The operational amplifier (signal amplifier) A1, the non-inverted through the resistor R _in the input terminal the input voltage V _in is input, the inverting input terminal is grounded through a resistor Rs. The output of the operational amplifier A1 is connected to the inverting input terminal of the operational amplifier A1 via a resistor Rf.
The operational amplifier A2 is connected to the non-inverting input terminal of the operational amplifier A2 and the non-inverting input terminal of the operational amplifier A3.
The input voltage V _in via the resistor R _in is input to the amplifier,
Output as output voltage V _OUT .

The operational amplifier (first amplifier) A2 has a lower limit set voltage _VLL input to its inverting input terminal, and its output input to the base of the transistor Tr1. The operational amplifier A2 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the lower limit setting voltage V _LL and outputs the amplified voltage to the base of the transistor Tr1.

The operational amplifier (second amplifier) A3 has its upper limit voltage V _LU input to its inverting input terminal, and its output is input to the base of the transistor Tr2. The operational amplifier A3 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the upper limit voltage V _LU and outputs the amplified voltage to the base of the transistor Tr2.

The transistor Tr1 has an emitter connected to the power supply _Vcc , a collector connected to the non-inverting input terminal of the operational amplifier A1, and a transistor Tr1 and a resistor R _in.
Constitute an input limiting circuit (first input limiting circuit) 131. When the output voltage of the operational amplifier A2 becomes lower than the power supply _Vcc by the Vbe voltage of the transistor Tr1 (about 0.7 V), the input limiting circuit 131 turns on the transistor Tr1.
There is turned on through the resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1.

The transistor Tr2 has an emitter connected to the power supply _Vee , a collector connected to the non-inverting input terminal of the operational amplifier A1, and a transistor Tr2 and a resistor R _in.
Constitute an input limiting circuit (second input limiting circuit) 132. Input limiting circuit 132, the output voltage of the operational amplifier A3 is higher by Vbe voltage of the transistor Tr2 (approximately 0.7 V) than the power supply V _ee, the transistor Tr2
There is turned on through the resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1.

That is, the upper / lower limit voltage limiting circuit 130
Operational amplifier A1 which is a non-inverting amplifier as a signal amplifier
The first amplifier that amplifies the difference voltage between the output voltage V _OUT and the lower limit set voltage V _{LL as} the set limit voltage is connected to the operational amplifier A2 and the output voltage V _OUT and the upper limit voltage V _{LU as the} set limit voltage. Using an operational amplifier A3 as a second amplifier for amplifying the difference voltage between the first and second input limiting circuits 1
An upper / lower limit voltage limiting circuit using resistors R _in and transistors Tr 1 and Tr 2 as resistors 31 and 132.

Upper / lower limit voltage limiting circuit 130 of the present embodiment
According to the above, the operational amplifier A1 outputs the input voltage V
amplifying the _in output as the output voltage V _OUT, the output voltage V _OUT is input to the non-inverting input terminal of the non-inverting input terminal and an operational amplifier A3 of the operational amplifier A2. The operational amplifier A2 has a lower limit set voltage V _LL input to its inverting input terminal, and amplifies a difference voltage between the output voltage V _OUT of the operational amplifier A1 and the lower limit set voltage V _LL via the transistor Tr1. Output to the non-inverting input terminal of A1. The operational amplifier A3 has an inverting input terminal to which the upper limit voltage V _LU is input, and outputs the output voltage V _LU of the operational amplifier A1.
The difference voltage between _OUT and the upper limit voltage V _LU is determined by the transistor Tr2.
And output to the non-inverting input terminal of the operational amplifier A1. When the output voltage V _OUT of the operational amplifier A1 is higher than the lower limit set voltage V _{LL and} lower than the upper limit voltage V _LU , the output voltage of the operational amplifier A2 becomes higher. And the output voltage of the operational amplifier A3 has been shifted to the negative side.
The transistors Tr1 and Tr2 are both off. Accordingly, the input limiting circuit 131 and the input limiting circuit 132 does not limit the input voltage V _in input to the operational amplifier A1, the non-inverting input terminal of the operational amplifier A1, the input voltage V _in is input as it is. The upper and lower limit voltage limiting circuit 130 outputs the output voltage V of the operational amplifier A1.
_{If OUT} falls below the lower limit set voltage V _LL, the output voltage of the operational amplifier A3 is remains unchanged shook off the negative side, the output voltage of the operational amplifier A2 is reduced in the negative direction,
When the output voltage of the operational amplifier A2 becomes lower than the power supply _Vcc by the Vbe voltage (about 0.7 V) of the transistor Tr1, the transistor Tr1 turns on, and the input limiting circuit 131
The input voltage V _in input to the operational amplifier A1 through a resistor R _in, output voltage V _OUT is limited to be substantially lower set voltage V _LL. Further, the upper and lower limit voltage limiting circuit 130
Means that the output voltage V _OUT of the operational amplifier A1 is equal to the upper limit voltage V
_{When the} voltage rises above _LU, the output voltage of the operational amplifier A2 does not change while being swung to the positive side.
3 increases in the positive direction, and this operational amplifier A
3 the output voltage from the power supply V _ee of the transistor Tr2 of Vb
When the e voltage (about 0.7 V) increases, the transistor Tr
2 is turned on, the input limiting circuit 132, the input voltage V _in via the resistor R _in is input to the operational amplifier A1, the output voltage V _OUT is limited to be approximately the upper limit limit voltage V _LU.

As described above, the upper and lower limit voltage limiting circuit 130
Is the output voltage V _OUT of the operational amplifier A1, which is a signal amplifier.
To a voltage between the upper limit voltage V _LU and the lower limit voltage V _LL , and operates as an upper / lower voltage limit circuit. And
The output voltage V _{OU T} of the operational amplifier A1, the lower limit setting voltage V _LL
With respect to the upper limit voltage V _LU only by the offset voltage of the operational amplifier A2.
Deviation only without the offset voltage, further, almost no change due to the input voltage V _in. Therefore, compared to the conventional upper and lower limit voltage limiting circuit using resistors and diodes,
The output voltage V _OUT can be accurately restricted between the lower limit set voltage _VLL and the upper limit voltage _VLU . In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 14 shows a twelfth embodiment of the voltage limiting circuit of the present invention.
This embodiment is an upper and lower limit voltage limiting circuit using an inverting amplifier and a transistor, and corresponds to claim 2. FIG.

FIG. 14 shows a twelfth embodiment of the voltage limiting circuit of the present invention.
FIG. 14 is a circuit diagram of an upper / lower limit voltage limiting circuit 140 to which the embodiment of FIG. In FIG. 14, the upper and lower limit voltage limiting circuit 14
0 is an operational amplifier A1, which is an inverting amplifier, and an operational amplifier A
2, A3, resistance R _in , resistance Rf, and transistor Tr
1, Tr2 and the like.

[0131] The operational amplifier (signal amplifier) A1 has its inverting input via a resistor R _in the terminal input voltage V _in is input, the non-inverting input terminal is grounded. The output of the operational amplifier A1 is fed back to the inverting input terminal of the operational amplifier A1 via the resistor Rf, and the operational amplifier A2
And the inverting input terminal of the operational amplifier A3. Operational amplifier A1, an input voltage V _in is input via the resistor R _in and amplifies and outputs the output voltage V _OUT.

The operational amplifier (first amplifier) A2 has a lower limit voltage V _LL input to its non-inverting input terminal.
The output is input to the base of the transistor Tr1. The operational amplifier A2 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the lower limit setting voltage V _LL and outputs the amplified voltage to the base of the transistor Tr1.

The operational amplifier (second amplifier) A3 has an upper limit voltage V _LU input to its non-inverting input terminal,
The output is input to the base of the transistor Tr2. The operational amplifier A3 amplifies the difference voltage between the output voltage V _OUT from the operational amplifier A1 and the upper limit voltage V _LU and outputs the amplified voltage to the base of the transistor Tr2.

The transistor Tr1 has its emitter connected to the power supply _Vee , its collector connected to the inverting input terminal of the operational amplifier A1, and the transistor Tr1 and the resistor Ree.
_“in” forms an input limiting circuit (first input limiting circuit) 141. Input limit circuit 141 includes an operational output voltage of the amplifier A2 is, Vb of the transistor Tr1 than the power supply V _ee
larger when e voltage only (about 0.7 V), the transistor Tr1 is turned on, via a resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1.

The transistor Tr2 has its emitter connected to the power supply _Vcc , its collector connected to the inverting input terminal of the operational amplifier A1, and the transistor Tr2 and the resistor R
_{“in” configures} the input limiting circuit (second input limiting circuit) 142. The input limiting circuit 142 determines that the output voltage of the operational amplifier A3 is higher than the power supply _Vcc by Vb of the transistor Tr2.
If only smaller e voltage (about 0.7 V), the transistor Tr2 is turned on, via a resistor R _in limiting the magnitude of the input voltage V _in input to the operational amplifier A1.

[0136] Then, the inverting amplifier and the operational amplifier A1 by a resistor R _in and the resistor Rf is formed, the resistance R _in the
In addition to determining the closed loop gain of this inverting amplifier, it also acts as part of the input limiting circuits 141, 142, as described above.

That is, the upper and lower limit voltage limiting circuit 140
An operational amplifier A1 which is an inverting amplifier as a signal amplifier is used, and an operational amplifier A2 and an output voltage _VOU thereof are provided to a first amplifier which amplifies a difference voltage between its output voltage V _OUT and a lower limit set voltage _VLL which is a set limit voltage. _An operational amplifier A3 is used as a second amplifier for amplifying the difference voltage between _T and the upper limit voltage V _LU which is the set limit voltage, and the first and second input limit circuits 14 are used.
Which is the lower limit voltage limiting circuit on using resistance R _in the transistor Tr1 and the transistor Tr2 to 1,142.

Upper / lower limit voltage limiting circuit 140 of the present embodiment
According to the above, the operational amplifier A1 outputs the input voltage V
amplifying the _in output as the output voltage V _OUT, the output voltage V _OUT is input to the inverting input terminal of the inverting input terminal and an operational amplifier A3 of the operational amplifier A2. Operational amplifier A
2 has a lower limit voltage V _LL input to its non-inverting input terminal, and amplifies the difference voltage between the output voltage V _OUT of the operational amplifier A1 and the lower limit voltage V _LL via the transistor Tr1. Output to the inverted input terminal. Also,
The operational amplifier A3 has its non-inverting input terminal input with the upper limit voltage V _LU , and the output voltage V _LU of the operational amplifier A1.
The difference voltage between _OUT and the upper limit voltage V _LU is determined by the transistor Tr2.
And output to the inverting input terminal of the operational amplifier A1. When the output voltage V _OUT of the operational amplifier A1 is higher than the lower limit set voltage V _{LL and} lower than the upper limit voltage V _LU , the output voltage of the operational amplifier A2 becomes negative. And the operational amplifier A
The output voltage of the transistor Tr3 is turned to the positive side, and the transistors Tr1 and Tr2 are both off. Accordingly, the input limiting circuit 141 and the input limiting circuit 142 does not limit the input voltage V _in input to the operational amplifier A1, the inverting input terminal of the operational amplifier A1, the input voltage V _in is input as it is, the resistance Rf In
Only current determined with the input voltage V _in by the resistor R _in the flow, with respect to the input voltage V _in, is amplified by the gain provisions. When the output voltage V _OUT of the operational amplifier A1 falls below the lower limit set voltage V _LL , the output voltage of the operational amplifier A3 does not change while being swung to the positive side. When the output voltage of the amplifier A2 increases in the positive direction and the output voltage of the operational amplifier A2 becomes higher than the power supply _Vee by the Vbe voltage (about 0.7 V) of the transistor Tr1, the inverting input terminal of the operational amplifier A1 The transistor Tr1 is turned on, and a current flows through the transistor Tr1 and the resistor Rf so that the output voltage V _OUT becomes the lower limit setting voltage V _LL . Accordingly, the input limiting circuit 141, the input voltage V _in input to the operational amplifier A1, the output voltage V _OUT is limited to be substantially lower set voltage V _LL. Further, the upper and lower limit voltage limiting circuit 14
0 means that when the output voltage V _OUT of the operational amplifier A1 rises above the upper limit voltage V _LU , the output voltage of the operational amplifier A2 does not change while being swung to the negative side.
3 decreases in the negative direction, and this operational amplifier A
3 is higher than the power supply _Vcc by Vb of the transistor Tr2.
When the e voltage (about 0.7 V) decreases, the transistor Tr
2 is turned on, and the output voltage V _OUT is supplied to the inverting input terminal of the operational amplifier A1 through the transistor Tr2 and the resistor Rf.
Flows such that the voltage becomes the upper limit voltage V _LU . Accordingly, the input limiting circuit 142, the input voltage V _in input to the operational amplifier A1, the output voltage V _OUT is limited to be approximately the upper limit limit voltage V _LU.

As described above, the upper and lower limit voltage limiting circuit 140
Is the output voltage V _OUT of the operational amplifier A1, which is a signal amplifier.
To a voltage between the upper limit voltage V _LU and the lower limit voltage V _LL , and operates as an upper / lower voltage limit circuit. And
The output voltage V _{OU T} of the operational amplifier A1, the lower limit setting voltage V _LL
With respect to the upper limit voltage V _LU only by the offset voltage of the operational amplifier A2.
Deviation only without the offset voltage, further, almost no change due to the input voltage V _in. Therefore, compared to the conventional upper and lower limit voltage limiting circuit using resistors and diodes,
The output voltage V _OUT can be accurately restricted between the lower limit set voltage _VLL and the upper limit voltage _VLU . In addition, in the case of voltage limitation, in particular, not only power is not required, but also a resistor or the like for current limitation is not required in the output signal line, thereby realizing high-speed operation of a load capacitance and low-resistance driving. And power consumption during voltage limitation can be suppressed.

FIG. 15 is a diagram showing a specific example of the eleventh embodiment shown in FIG. 13, in which a non-inverting amplifier, an upper and lower limit voltage limiter using an input limiter circuit including a transistor and an input resistor are used. Circuit 150.

Referring to FIG. 15, upper and lower limit voltage limiting circuit 15
0 indicates transistors Q1 to Q9, transistor Q10,
Transistors Q20-Q29, transistors Q30-Q
39, transistors Tr1, Tr2, resistance R _in , resistance R
s, resistor Rf, resistors R10, R20, R21, R30,
R31 and a capacitor C1 are provided.

Transistors Q1 to Q9 and capacitor C1
An operational amplifier as the operational amplifier A1 in FIG.
A non-inverting operational amplifier 151 is configured by the resistor Rs and the resistor Rf, and an operational amplifier 152 as the operational amplifier A2 in FIG. 13 is configured by the transistors Q20 to Q28 and the resistors R20 and R21. The resistor R10 and the transistor Q10 are a common bias circuit for the non-inverting operational amplifier 151 and the operational amplifier 152. Further, the operational amplifier 153 as the operational amplifier A3 in FIG. 13 is configured by the transistors Q30 to Q38 and the resistors R30 and R31. FIG. 1 shows the configuration of the resistor R _in , the transistors Tr1 and Tr2, the transistor Q29, and the transistor Q39.
An input limiting circuit 154 as the first and second input limiting circuits of No. 3 is configured.

Note that the transistor Q25, the transistor Q26 and the transistor Q29 are
The resistor R20, the transistor Q21 and the transistor Q24 prevent the transistor Q22 and the transistor Q23 from being destroyed by applying an excessive voltage between the base and the emitter of the transistor Q22 and the transistor Q23. It is an element for performing. The transistor Q35, the transistor Q36, and the transistor Q39 are elements for avoiding the saturation of the transistor Q38,
An excessive voltage is applied between the base and the emitter of the transistor Q32 and the transistor Q33, and the transistor Q32 and the transistor Q3
3 is an element for preventing the device 3 from being destroyed.

[0144] The transistor Q1 of the non-inverting operational amplifier 151 via a resistor R _in is input the input voltage V _in, the non-inverting operational amplifier 151 amplifies the input voltage V _in an output voltage V _OUT I do. The operational amplifier 152 includes
The output voltage V _OUT of the non-inverting operational amplifier 151 is input and the lower limit setting voltage V _LL is input. The operational amplifier 152 outputs the output voltage V _OUT output from the non-inverting operational amplifier 151 and the lower limit setting voltage V _LL. The differential voltage of _LL is amplified and output to the base of the transistor Tr1. The output voltage V _OUT of the non-inverting operational amplifier 151 and the upper limit voltage V _LU are input to the operational amplifier 153, and the operational amplifier 153 is connected to the non-inverting operational amplifier 1
The difference voltage between the output voltage V _OUT output from the output terminal 51 and the upper limit voltage V _LU is amplified and output to the base of the transistor Tr2.

That is, the upper / lower limit voltage limiting circuit 150
Using a non-inverting operational amplifier 151 as a signal amplifier, its output voltage V _OUT and lower limit set voltage V which is a set limit voltage
_The operational amplifier 152 is used as the first amplifier for amplifying the difference voltage of _LL.
And an operational amplifier 15 as a second amplifier for amplifying the difference voltage between the output voltage V _OUT and the upper limit voltage V _LU which is a set limit voltage.
3 is an upper and lower limit voltage limiting circuit using the resistor R _in , the transistor Tr1, the transistor Q29, and the transistor Tr2 and the transistor Q39 in the first and second input limiting circuits 154.

[0146] According to the lower limit voltage limiting circuit 150 on the present embodiment, the non-inverting operational amplifier 151 amplifies the input voltage V _in is the input signal and outputs, the output voltage V _OUT is an operational amplifier 152 and the calculation The signal is input to the amplifier 153.
The lower limit setting voltage V _LL is input to the operational amplifier 152, and the operational amplifier 152 outputs a difference voltage between the output voltage V _OUT of the non-inverting operational amplifier 151 and the lower limit setting voltage V _LL to the base of the transistor Tr1. The operational amplifier 15
3, the upper limit voltage V _LU is input, and the operational amplifier 153 outputs the output voltage V _OUT of the non-inverting operational amplifier 151.
And the upper limit voltage V _LU is amplified and output to the base of the transistor Tr2. Then, the upper and lower limit voltage limiting circuit 150 outputs the output voltage V _OUT of the non-inverting operational amplifier 151.
Is higher than the lower limit voltage V _{LL and} lower than the upper limit voltage V _LU , the output voltage of the operational amplifier 152 becomes
The output voltage of the operational amplifier 153 is turned to the negative side, and the transistor Tr1 and the transistor Tr2 are both turned off. Accordingly, the input limiting circuit 154 does not limit the input voltage V _in input to the non-inverting operational amplifier 151, to the non-inverting operational amplifier 151, the input voltage V _in is input as it is. The upper / lower limit voltage limiting circuit 150 includes the non-inverting operational amplifier 1.
When the output voltage V _OUT of the operational amplifier 151 falls below the lower limit set voltage V _LL , the output voltage of the operational amplifier 153 does not change while being swung to the negative side, but the output voltage of the operational amplifier 152 decreases in the negative direction. When the output voltage of the operational amplifier 152 becomes lower than the power supply _Vcc by the Vbe voltage (about 0.7 V) of the transistor Tr1, the transistor Tr1 is turned on, and the input limiting circuit 154 outputs the input to the non-inverting operational amplifier 151. the voltage V _in, the output voltage V _OUT is limited to be substantially lower set voltage V _LL. Further, the upper / lower limit voltage limiting circuit 150 determines that the output voltage V _OUT of the non-inverting operational amplifier 151 is higher than the upper limit limit voltage V _LU .
Although the output voltage of the operational amplifier 152 does not change while being swung to the positive side, the output voltage of the operational amplifier 153 increases in the positive direction, and the output voltage of the operational amplifier 153 is
Vbe voltage of transistor Tr2 (about 0.7V) from _ee
Becomes larger, the transistor Tr2 is turned on, the input limiting circuit 154, the input voltage V _in input to the non-inverting operational amplifier 151, the output voltage V _OUT is limited to be approximately the upper limit limit voltage V _LU.

As described above, the upper and lower limit voltage limiting circuit 150
Restricts the output voltage V _OUT of the non-inverting operational amplifier 151 as a signal amplifier to a voltage between the upper limit voltage V _LU and the lower limit voltage V _LL , and operates as an upper / lower voltage limit circuit.
The output voltage V _OUT of the operational amplifier A1 is only shifted from the lower limit set voltage _VLL by the offset voltage of the operational amplifier A2, and the output voltage V _OUT is the offset voltage of the operational amplifier A3 from the upper limit voltage V _LU . There is only a gap, and
Almost no change due to the input voltage V _in. Therefore,
Compared with the conventional upper and lower limit voltage limiting circuit using a resistor and a diode, the output voltage V _OUT can be more accurately limited between the lower limit set voltage V _LL and the upper limit voltage V _LU . Also,
In the case of voltage limiting, in particular, not only power is not required, but also a resistor for current limiting is not required in the output signal line, so that high-speed operation of load capacitance and low-resistance driving can be realized. Power consumption at the time of voltage limitation.

FIG. 16 shows a thirteenth embodiment of the voltage limiting circuit of the present invention.
FIG. 9 is a diagram showing an embodiment of the present invention, which is a lower limit voltage limiting circuit using an operational amplifier and a multiplier, and corresponds to claim 3.

FIG. 16 is a circuit diagram showing a thirteenth power supply limiting circuit according to the present invention.
FIG. 13 is a circuit diagram of a lower limit voltage limiting circuit 160 to which the embodiment is applied. In FIG. 16, lower limit voltage limiting circuit 160
Is an operational amplifier A1 as a signal amplifier, a resistor Rs1,
It includes a resistor Rs2, an operational amplifier A2, resistors Rf1, Rf2, a multiplier M1, and the like.

[0150] The operational amplifier (signal amplifier) A1 has its non-inverting input the input voltage V _in 1, which is an input signal through the resistor Rs1 terminal is input, the resistance to its inverting input terminal Rs2
The input voltage V _in 2 inputted the input signal via.
The non-inverting input terminal of the operational amplifier A1 is grounded via the resistor Rf1, and the inverting input terminal of the operational amplifier A1 is
The output of the multiplier M1 is connected to the non-inverting input terminal of the operational amplifier A2. The output terminal of the operational amplifier A1 is connected to the A input terminal of the multiplier M1.
Is connected to the B input terminal of the multiplier M1.

The multiplier (analog multiplier) M1 has an A input terminal and a B input terminal. The B input terminal is a terminal in which only a positive input is valid, that is, a terminal which regards a negative input as zero. The multiplier M1 multiplies (A × αB) by α times the input of the A input terminal (hereinafter, referred to as A input) and the input of the B input terminal (hereinafter, referred to as B input), and outputs the output voltage V _OUT.
Output as However, αB ≦ 1. This multiplier M
The output voltage V _OUT which is the output of 1 is fed back to the inverting input terminal of the operational amplifier A1 via the resistor Rf2 and is input to the non-inverting input terminal of the operational amplifier A2.

The operational amplifier (amplifier) A3 has a lower limit set voltage _VLL input to its inverting input terminal, and a multiplier M3.
Amplify the difference voltage between the output voltage V _OUT output from the output signal 1 and the lower limit setting voltage V _LL and output the amplified voltage to the B input terminal of the multiplier M1.

That is, the lower limit voltage limiting circuit 160 includes an operational amplifier A1 which is a signal amplifier, and an operational amplifier A2 which is an amplifier for amplifying a difference voltage between the output voltage V _OUT and the lower limit set voltage _VLL which is a set limit voltage. This is a lower limit voltage limiting circuit using a multiplier M1 which is an analog multiplier that multiplies the output of the operational amplifier A1 and the output of the operational amplifier A2 and outputs the output voltage V _OUT .

According to the lower limit voltage limiting circuit 160 of the present embodiment, the operational amplifier A1 outputs the input voltage V
amplifies a difference voltage _in 1 and the input voltage V _in 2 outputs to the A input terminal of the multiplier M1, the multiplier M1 is the operational amplifier A2 which is input to the A input and the B input terminal of the input terminal A is the output B input by multiplying (a × αB), the output voltage V _{OU T}
Output as Output voltage V _OUT output from multiplier M1
Is input to the non-inverting input terminal of the operational amplifier A2, and is fed back to the operational amplifier A1 via the resistor Rf2.
The operational amplifier A2 has a lower limit set voltage V at its inverting input terminal.
_LL is entered. Operational amplifier A2 amplifies and outputs a difference voltage between the output voltage V _OUT and the lower limit setting voltage V _LL multipliers M1 to the B input terminal of the multiplier M1. When the output voltage V _OUT of the multiplier M1 is higher than the lower limit set voltage V _LL , the lower limit voltage limiting circuit 160 determines that the output voltage of the operational amplifier A2 has swung to the positive side. M
1 performs an operation of (A × 1). Therefore, the output voltage V _OUT becomes the same output voltage as in the case of only the operational amplifier _{A1, V OUT = Rf2 / Rs2} * (V in 1-V in 2)
Becomes However, it is assumed that Rf1 / Rs1 = Rf2 / Rs2. Further, the lower limit voltage limiting circuit 160 controls the output voltage V _OUT
Is lower than the lower limit setting voltage V _LL , the output voltage of the operational amplifier A2 decreases in the negative direction, and the multiplier M1
It approaches the calculation of (A × 0). That is, the operational amplifier A1
The gain from the input to the output voltage V _OUT decreases, and the output voltage V _OUT is limited so as to be substantially equal to the lower limit set voltage V _LL .

As described above, the lower limit voltage limiting circuit 160
The output voltage V _OUT is limited to a voltage higher than the lower limit set voltage _VLL , and operates as a lower limit voltage limiting circuit.

FIG. 17 shows a fourteenth embodiment of the voltage limiting circuit of the present invention.
FIG. 9 is a diagram showing an embodiment of the present invention, and this embodiment is an upper limit voltage limiting circuit using an operational amplifier and a multiplier, and corresponds to claim 3.

FIG. 17 shows a fourteenth embodiment of the power supply limiting circuit of the present invention.
FIG. 10 is a circuit diagram of an upper limit voltage limiting circuit 170 to which the embodiment is applied. In FIG. 17, the upper limit voltage limiting circuit 170
Is an operational amplifier A1 as a signal amplifier, a resistor Rs1,
It includes a resistor Rs2, an operational amplifier A3, resistors Rf1, Rf2, a multiplier M1, and the like.

[0158] The operational amplifier (signal amplifier) A1 has its non-inverting input the input voltage V _in 1, which is an input signal through the resistor Rs1 terminal is input, the resistance to its inverting input terminal Rs2
The input voltage V _in 2 inputted the input signal via.
The non-inverting input terminal of the operational amplifier A1 is grounded via the resistor Rf1, and the inverting input terminal of the operational amplifier A1 is
The output of the multiplier M1 and the inverting input terminal of the operational amplifier A3 are connected. The output terminal of the operational amplifier A1 is connected to the A input terminal of the multiplier M1, and the output terminal of the operational amplifier A3 is connected to the B input terminal of the multiplier M1.

The multiplier (analog multiplier) M1 has an A input terminal and a B input terminal, and the B input terminal is a terminal in which only a positive input is valid, that is, a terminal which regards a negative input as zero. The multiplier M1 multiplies (A × αB) by α times the input of the A input terminal (hereinafter, referred to as A input) and the input of the B input terminal (hereinafter, referred to as B input), and outputs the output voltage V _OUT.
Output as However, αB ≦ 1. This multiplier M
The output voltage V _OUT which is the output of 1 is fed back to the inverting input terminal of the operational amplifier A1 via the resistor Rf2 and is input to the inverting input terminal of the operational amplifier A3.

The operational amplifier (amplifier) A3 has an upper limit voltage V _LU input to its non-inverting input terminal, and amplifies the difference voltage between the output voltage V _OUT output from the multiplier M1 and the upper limit voltage V _LU. Then, the signal is output to the B input terminal of the multiplier M1.

That is, the upper limit voltage limiting circuit 170 includes an operational amplifier A1 as a signal amplifier, an operational amplifier A3 as an amplifier for amplifying a difference voltage between the output voltage V _OUT and an upper limit voltage V _{LU as} a set limit voltage, An upper limit voltage limiting circuit using a multiplier M1, which is an analog multiplier that multiplies the output of the operational amplifier A1 and the output of the operational amplifier A3 and outputs the output voltage V _OUT .

According to the upper limit voltage limiting circuit 170 of the present embodiment, the operational amplifier A1 outputs the input voltage V
amplifies a difference voltage _in 1 and the input voltage V _in 2 outputs to the A input terminal of the multiplier M1, the multiplier M1 is the operational amplifier A3 which is input to the A input and the B input terminal of the input terminal A is the output B input by multiplying (a × αB), the output voltage V _{OU T}
Output as Output voltage V _OUT output from multiplier M1
Is input to the inverting input terminal of the operational amplifier A3, and is fed back to the operational amplifier A1 via the resistor Rf2. The operational amplifier A3 supplies the upper limit voltage V _LU to its inverting input terminal.
Is entered. The operational amplifier A3 amplifies the difference voltage between the output voltage V _OUT of the multiplier M1 and the upper limit voltage V _LU and outputs the amplified voltage to the B input terminal of the multiplier M1. When the output voltage V _OUT of the multiplier M1 is lower than the upper limit voltage V _LU , the upper limit voltage limiting circuit 170 is in a state where the output voltage of the operational amplifier A3 is swung to the positive side. M1
Performs the operation of (A × 1). Therefore, the output voltage V
_OUT includes an operational amplifier becomes the same output voltage as in the case of only A1, the _{V OUT = Rf2 / Rs2 * (} V in 1-V in 2). However, it is assumed that Rf1 / Rs1 = Rf2 / Rs2.
When the output voltage V _OUT rises above the lower limit set voltage V _LL , the upper limit voltage limiting circuit 170 sets the operational amplifier A3
Decreases in the negative direction, and the multiplier M1 outputs (A
× 0). That is, the gain between the input of the operational amplifier A1 and the output voltage V _OUT decreases, and the output voltage V _OUT is limited so as to be substantially equal to the lower limit set voltage V _LL .

As described above, the upper limit voltage limiting circuit 170
The output voltage V _OUT is limited to a voltage lower than the upper limit voltage V _{LU and} operates as an upper voltage limit circuit.

FIG. 18 is a diagram showing a specific example of the thirteenth embodiment shown in FIG. 16, which is a lower limit voltage limiting circuit 180 using an operational amplifier and a multiplier.

In FIG. 18, lower limit voltage limiting circuit 180
Are transistors Q1-Q9, transistor Q11, transistors Q20-Q31, transistors Q60, Q6
1, Q63, Q66 to Q69, resistors Rs1, Rs2, resistors Rf1, Rf2, resistors R10, R20, R21, a capacitor C1, and the like.

The lower limit voltage limiting circuit 180 comprises an operational amplifier 181 as an operational amplifier A1 in FIG. 16 comprising transistors Q1 to Q9 and a capacitor C1, and a transistor Q6
A multiplier 182 as a multiplier M1 in FIG. 16 for performing current input type multiplication by 0, Q61, Q63 and transistors Q66 to Q69, and the input voltage V _in 1 and the input voltage V
_In 2 constitutes a differential amplifier using resistors Rs1, Rf1, Rs2, and Rf2.
31, the operational amplifier A of FIG. 16 by the resistors R20 and R21.
2 constitutes the operational amplifier 183. And
In the multiplier 182, the A input to the A input terminal of the multiplier M1 in FIG. 16 is the current input of the current flowing through the emitters of the transistors Q66 and Q67, and the B input to the B input terminal of the multiplier M1 is , The current flowing through the base of the transistor Q66 and the emitters of the transistor Q68 and the transistor Q69. As an operation of the multiplier 182, when the B input flows out of the multiplier 182, the A input is directly output to the collector of the transistor Q67 (multiplication coefficient ≒
1) When the B input flows into the multiplier 182, almost zero is output (multiplication coefficient ≒ 0). The output voltage V is applied to the operational amplifier 183 as the operational amplifier A2 in FIG.
_OUT and the lower limit voltage V _LL are input to the base of the transistor Q22 and the base of the transistor Q23, and the operational amplifier 183 amplifies the difference voltage between the lower limit voltage V _LL and the output voltage V _OUT , A current corresponding to the difference voltage is supplied as a B input.

Note that the resistor R10 and the transistor Q11
Is a common bias circuit, and transistors Q60,
Q61 and Q63 are bias circuits that define the operating potential of the multiplier 182. Also, transistors Q68 and Q6
Reference numeral 9 denotes a circuit for preventing an excessive voltage from being applied between the emitter and base of the transistors Q66 and Q67, thereby preventing the transistors Q66 and Q67 from being destroyed. The transistors Q25, Q26 and Q29 avoid saturation of the transistor Q28. Device. Further, the resistor R20 and the transistors Q21 and Q24 are connected to the transistors Q22 and Q24.
This is an element for preventing an excessive voltage from being applied between the base and the emitter of the transistor 23 to damage the transistors Q22 and Q23.

[0168] The lower limit voltage limiting circuit 180 of this embodiment, operational amplifier 181 amplifies the input voltage V _in 1 is the input signal differential voltage of the input voltage V _in 2 output as A input of the multiplier 182 , Multiplier 182 multiplies (A × αB) the A input and the B input input from operational amplifier 183 and outputs the result as output voltage V _OUT . The output voltage V _OUT output from the multiplier 182 is input to the operational amplifier 183 and is fed back to the operational amplifier 181 via the resistor Rf2.
_LL is entered. The operational amplifier 183 is connected to the multiplier 18
Amplifies the differential voltage between the second output voltage V _{OU T} and the lower limit setting voltage V _LL and outputs to the multiplier 182 as the B input. Then, the lower limit voltage limiting circuit 180 outputs the output voltage V
_{When OUT} is higher than the lower limit set voltage _VLL , the operational amplifier 18
The output voltage of No. 3 is in a state of swinging to the positive side,
The multiplier 182 performs an operation of (A × 1). Therefore, the output voltage V _OUT becomes the same output voltage as when only the operational amplifier 181 is used, and V _OUT = Rf2 / Rs2 * (V
_in 1−V _in 2). However, Rf1 / Rs1 = Rf2
/ Rs2. When the output voltage V _OUT falls below the lower limit setting voltage V _LL ,
The output voltage of the operational amplifier 183 decreases in the negative direction, and the multiplier 182 approaches the operation of (A × 0). That is,
The gain between the input of the operational amplifier 181 and the output voltage V _OUT decreases, and the output voltage V _OUT is limited to be substantially equal to the lower limit set voltage V _LL .

As described above, the lower limit voltage limiting circuit 180
The output voltage V _OUT is limited to a voltage higher than the lower limit set voltage _VLL , and operates as a lower limit voltage limiting circuit.

FIG. 19 is a diagram showing a specific example of the fourteenth embodiment shown in FIG. 17, which is an upper limit voltage limiting circuit 190 using an operational amplifier and a multiplier.

In FIG. 19, upper limit voltage limiting circuit 190
Are transistors Q1-Q9, transistor Q11, transistors Q40-Q51, transistors Q60, Q6
1, Q63 to Q65, Q68, Q69, resistors Rs1, R
s2, resistors Rf1, Rf2, resistors R10, R40, R4
1 and a capacitor C1.

The upper limit voltage limiting circuit 190 includes an operational amplifier 191 as an operational amplifier A1 shown in FIG. 17 using transistors Q1 to Q9 and a capacitor C1, and a transistor Q6.
0, Q61, Q63~Q65, Q68, a multiplier 192 as a multiplier M1 in FIG. 17 for multiplying the current input type by Q69, the resistance to the input voltage V _in 1 and the input voltage V _in 2 Rs1, Rf1, Rs2 and Rf2 constitute a differential amplifier, and transistors Q40 to Q51,
The operational amplifier 193 as the operational amplifier A3 in FIG. 17 is configured by the resistors R40 and R41. In the multiplier 192, the A input to the A input terminal of the multiplier M1 in FIG. 17 is the current input of the current flowing to the emitters of the transistors Q64 and Q65, and the B input to the B input terminal of the multiplier M1. The input is the current flowing through the base of transistor Q65 and the emitters of transistor Q68 and transistor Q69. As an operation of the multiplier 192, when the B input flows out of the multiplier 192, the A input is
Output to the 64 collectors (multiplication coefficient ≒ 1),
When the B input flows into the multiplier 192, almost zero is output (multiplication coefficient ≒ 0). The output voltage V _OUT and the upper limit voltage V _LU are input to the base of the transistor Q42 and the base of the transistor Q43, respectively, in the operational amplifier 193 as the operational amplifier A3 in FIG. The difference voltage between V _LU and the output voltage V _OUT is amplified, and a current corresponding to the difference voltage is supplied as the B input of the multiplier 192.

Note that the resistor R10 and the transistor Q11
Is a common bias circuit, and transistors Q60,
Q61 and Q63 are bias circuits that define the operating potential of the multiplier 192. Also, transistors Q68 and Q6
Reference numeral 9 denotes a circuit for preventing an excessive voltage from being applied between the emitter and base of the transistors Q64 and Q65, thereby preventing the transistors Q64 and Q65 from being destroyed. The transistors Q45, Q46 and Q49 avoid saturation of the transistor Q48. Device. Further, the resistor R40 and the transistors Q41 and Q44 are connected to the transistors Q42 and Q44.
43 is an element for preventing an excessive voltage from being applied between the base and the emitter of the transistor 43 to damage the transistors Q42 and Q43.

[0174] The upper limit voltage limiting circuit 190 of this embodiment, operational amplifier 191 amplifies the input voltage V _in 1 is the input signal differential voltage of the input voltage V _in 2 to the multiplier 192, the multiplier 192 multiplies the input A by the input B from the operational amplifier 193 (A × αB) and outputs the result as an output voltage V _OUT . The output voltage V _OUT output from the multiplier 192 is input to the operational amplifier 193,
The signal is fed back to the operational amplifier 191 via the resistor Rf2, and the operational amplifier 193 is further input with the upper limit voltage V _LU . The operational amplifier 193 amplifies the difference voltage between the output voltage V _OUT of the multiplier 192 and the upper limit voltage V _LU and amplifies the difference voltage.
92. Then, the upper limit voltage limiting circuit 190
When the output voltage V _OUT of the multiplier 192 is lower than the upper limit voltage V _LU , the output voltage of the operational amplifier 193 is on the positive side, and the multiplier 192 has (A × 1)
Is calculated. Therefore, the output voltage V _OUT becomes the same output voltage as when only the operational amplifier 191 is used, and V _OUT
= Rf2 / Rs2 * (V _in 1−V _in 2). However,
Let Rf1 / Rs1 = Rf2 / Rs2. Also, the upper limit voltage limiting circuit 190 determines that the output voltage V _{OUT
When the} voltage rises above _LL, the output voltage of the operational amplifier 193 decreases in the negative direction, and the multiplier 192 approaches the operation of (A × 0). That is, the gain between the input of the operational amplifier 191 and the output voltage V _OUT decreases, and the output voltage V _OUT is limited to be substantially equal to the lower limit set voltage V _LL .

As described above, the upper limit voltage limiting circuit 190
The output voltage V _OUT is limited to a voltage lower than the upper limit voltage V _{LU and} operates as an upper voltage limit circuit.

FIG. 20 shows a fifteenth embodiment of the voltage limiting circuit of the present invention.
FIG. 9 is a diagram showing an embodiment of the present invention, and this embodiment is an upper / lower limit voltage limiting circuit using an operational amplifier and a multiplier, and corresponds to claim 4.

FIG. 20 is a circuit diagram showing a fifteenth power supply limiting circuit according to the present invention.
3 is a circuit diagram of an upper / lower limit voltage limiting circuit 200 to which the embodiment of FIG. In FIG. 20, upper and lower limit voltage limiting circuit 20
0 is an operational amplifier A1 as a signal amplifier, and a resistor Rs
1, resistor Rs2, resistors Rf1, Rf2, operational amplifier A
2. It includes an operational amplifier A3, a multiplier M1, a multiplier M2, and the like.

[0178] The operational amplifier (signal amplifier) A1 has its non-inverting input the input voltage V _in 1, which is an input signal through the resistor Rs1 terminal is input, the resistance to its inverting input terminal Rs2
The input voltage V _in 2 inputted the input signal via.
The non-inverting input terminal of the operational amplifier A1 is grounded via the resistor Rf1, and the inverting input terminal of the operational amplifier A1 is
The output of the multiplier M2 is connected to the non-inverting input terminal of the operational amplifier A2 and the inverting input terminal of the operational amplifier A3. The output terminal of the operational amplifier A1 is connected to the A input terminal of the multiplier M1, and the output terminal of the operational amplifier A2 is connected to the B input terminal of the multiplier M1.

The multiplier (first analog multiplier) M1 is
It has an A input terminal and a B input terminal, and the B input terminal is a terminal in which only a positive input is valid, that is, a terminal that regards a negative input as zero. The multiplier M1 is connected to an input of the A input terminal (hereinafter, referred to as an input).
It is called A input. ) And the input of the B input terminal (hereinafter referred to as B input) multiplied by (A × αB) and output to the multiplier M2. However, αB ≦ 1. Like the multiplier M1, the multiplier M2 has an A input terminal and a B input terminal, and the B input terminal is a terminal where only a positive input is valid, that is, a terminal which regards a negative input as zero.

The multiplier (second analog multiplier) M2 is
The input of the A input terminal (hereinafter referred to as A input) and the input of the B input terminal (hereinafter referred to as B input) are multiplied by α times (A ×
αB) and outputs it as the output voltage V _OUT . Where α
B ≦ 1. The output voltage V which is the output of the multiplier M2
_OUT is fed back to the inverting input terminal of the operational amplifier A1 via the resistor Rf2, and is input to the inverting input terminal of the operational amplifier A3 and the non-inverting input terminal of the operational amplifier A2.

The operational amplifier (first amplifier) A2 has an output voltage V output from the multiplier M2 at its non-inverting input terminal.
_{OUT receives the} lower limit setting voltage V _{LL at} its inverting input terminal, amplifies the difference voltage between the output voltage V _OUT output from the multiplier M2 and the lower limit setting voltage V _LL , and outputs the amplified voltage to the B input terminal of the multiplier M1. I do.

The operational amplifier (second amplifier) A3 has an inverting input terminal connected to the output voltage V output from the multiplier M2.
_{OUT receives the} upper limit voltage V _{LU at} its non-inverting input terminal, amplifies the difference voltage between the output voltage V _OUT output from the multiplier M2 and the upper limit voltage V _LU , and outputs the amplified voltage to the B input terminal of the multiplier M2. Output.

That is, the upper / lower limit voltage limiting circuit 200
An operational amplifier A1 that is a signal amplifier, an operational amplifier A2 that is a first amplifier that amplifies a difference voltage between the output voltage V _OUT and a lower limit set voltage V _LL that is a set limit voltage, and an output voltage V
_An operational amplifier A3, which is a second amplifier for amplifying a difference voltage between _OUT and an upper limit voltage _VLU , which is a set limit voltage, is multiplied by an output of the operational amplifier A1 and an output of the operational amplifier A2 and output to the multiplier M2. Multiplier M as a first analog multiplier
1 and a multiplier M2, which is a second analog multiplier that multiplies the output of the multiplier M1 and the output of the operational amplifier A3 and outputs the output voltage V _OUT .

Upper and lower limit voltage limiting circuit 200 of the present embodiment
According to the operational amplifier A1 is, amplifies the differential voltage between the input voltage V _in 2 and the input voltage V _in 1 is the input signal multiplier M1
, And the multiplier M1 multiplies (A × αB) the A input of the A input terminal and the B input which is the output of the operational amplifier A2 input to the B input terminal. To the A input terminal. The multiplier M2 multiplies (A × αB) the A input of the A input terminal and the B input which is the output of the operational amplifier A3 input to the B input terminal, and outputs the output voltage V
Output as _OUT . Output voltage V output from multiplier M2
_OUT is input to the non-inverting input terminal of the operational amplifier A2 and the inverting input terminal of the operational amplifier A3, and is fed back to the operational amplifier A1 via the resistor Rf2.
_{Has a} lower limit setting voltage _VLL input to its inverting input terminal,
The upper limit voltage V _LU is input to the non-inverting input terminal of the operational amplifier A3. Operational amplifier A2 amplifies the voltage difference between the output voltage V _OUT and the lower limit setting voltage V _LL from the multiplier M2 is output to the B input terminal of the multiplier M1, the operational amplifier A3, the output voltage from the multiplier M2 The difference voltage between V _OUT and upper limit voltage V _LU is amplified and output to the B input terminal of multiplier M2. When the output voltage V _OUT of the multiplier M2 is higher than the lower limit set voltage V _{LL and} lower than the upper limit voltage V _LU , the upper and lower limit voltage limiting circuit 200 sets the output voltages of the operational amplifiers A2 and A3 to the positive side, respectively. And the multipliers M1 and M2 are
An operation of (A × 1) is performed for each. Therefore, the output voltage V _OUT becomes the same output voltage as when only the operational amplifier A1 is used, and V _OUT = Rf2 / Rs2 * (V _in 1−V
_in 2). However, Rf1 / Rs1 = Rf2 / Rs2
And When the output voltage V _OUT is lower than the lower limit set voltage V _LL (in this case, lower than the upper limit voltage V _LU ), the upper and lower limit voltage limiting circuit 200 operates the operational amplifier A3.
Output voltage of the operational amplifier A2 decreases in the negative direction, and the output voltage of the multiplier M1
Approaches the operation of (A × 0). That is, the gain between the input of the operational amplifier A1 and the output voltage V _OUT decreases, and the output voltage V _OUT is limited so as to be substantially equal to the lower limit set voltage V _LL . Furthermore, the upper and lower limit voltage limiting circuit 200
When the output voltage V _OUT rises above the upper limit voltage V _LU (in this case, it is larger than the lower limit set voltage V _LL ), the output voltage of the operational amplifier A2 remains on the positive side but the output voltage of the operational amplifier A3 The output voltage decreases in the negative direction,
The multiplier M2 approaches the operation of (A × 0). That is,
The gain from the input of the operational amplifier A1 to the output voltage V _OUT is reduced, and the output voltage V _OUT is limited so as to be substantially equal to the upper limit voltage V _LU .

As described above, the upper and lower limit voltage limiting circuit 200
Restricts the output voltage V _OUT to a voltage between the upper limit voltage V _LU and the lower limit setting voltage V _LL , and operates as an upper / lower voltage limit circuit.

FIG. 21 is a diagram showing a specific example of the fifteenth embodiment shown in FIG. 20, which is an upper / lower limit voltage limiting circuit 210 using an operational amplifier and a multiplier.

In FIG. 21, upper and lower limit voltage limiting circuit 21 is provided.
0 indicates transistors Q1 to Q9, transistor Q11,
Transistors Q20-Q31, transistors Q40-Q
51, transistors Q60-Q62, Q64, transistors Q72-Q75, transistors Q80, Q81, Q
84, Q85, resistors Rs1, Rs2, resistors Rf1, Rf
2, resistor R10, resistors R20, R21, R40, R41
And a capacitor C1 and the like.

The upper limit voltage limiting circuit 210 includes an operational amplifier 211 as an operational amplifier A1 shown in FIG. 20 including transistors Q1 to Q9 and a capacitor C1, and a transistor Q72.
To Q75, a multiplier 212 as a multiplier M1 in FIG. 20, and transistors Q80 and Q80.
81, Q84, a multiplier 213 as a multiplier M2 of Figure 20 for multiplying the current input type by Q85, the resistance to the input voltage V _in 1 and the input voltage V _in 2 Rs1, Rf
1, Rs2 and Rf2 to constitute a differential amplifier,
The operational amplifier 214 as the operational amplifier A2 in FIG. 20 is provided by the transistors Q20 to Q31 and the resistors R20 and R21.
Are connected to transistors Q40 to Q51, resistors R40 and R41.
As a result, the operational amplifier 21 as the operational amplifier A3 in FIG.
5 are each configured. Then, the multiplier 212
In FIG. 20, the A input to the A input terminal of the multiplier M1 in FIG. 20 is the current input of the current flowing through the emitters of the transistors Q72 and Q73, and the B input to the B input terminal of the multiplier M1 in FIG. , The current flowing through the base of the transistor Q72 and the emitters of the transistor Q74 and the transistor Q75. As an operation of the multiplier 212, when the B input flows out of the multiplier 212, the A input is directly output to the collector of the transistor Q73 (multiplication coefficient ≒
1) When the B input flows into the multiplier 212, almost zero is output (multiplication coefficient ≒ 0). Further, the multiplier 213
In FIG. 20, the A input to the A input terminal of the multiplier M2 in FIG. 20 is the current input of the current flowing through the emitters of the transistors Q80 and Q81, and the B input to the B input terminal of the multiplier M2 in FIG. , The current flowing through the base of the transistor Q81 and the emitters of the transistor Q84 and the transistor Q85. As an operation of the multiplier 213, when the B input flows out of the multiplier 213, the A input is output as it is to the collector of the transistor Q80 (multiplication coefficient ≒
1) When the B input flows into the multiplier 213, almost zero is output (multiplication coefficient ≒ 0). The output voltage V _OUT and the lower limit setting voltage V _LL are input to the base of the transistor Q22 and the base of the transistor Q23, respectively, in the operational amplifier 214 as the operational amplifier A2 in FIG. _LL and output voltage V _OUT
And supplies a current corresponding to the difference voltage as the B input of the multiplier 212. The output voltage V _OUT and the upper limit voltage V _LU are input to the base of the transistor Q42 and the base of the transistor Q43 in the operational amplifier 215 as the operational amplifier A3 in FIG.
Amplifies the difference voltage between the upper limit voltage V _LU and the output voltage V _OUT and supplies a current corresponding to the difference voltage as the B input of the multiplier 213.

Note that the resistor R10 and the transistor Q11
Are common bias circuits, and transistors Q60 to Q60
Q62 and Q64 are bias circuits that define the operating potentials of the multipliers 212 and 213. Also, the transistor Q7
4, Q75 and transistors Q84, Q85 are connected to the transistors Q72, Q73 of the multiplier 212 and the multiplier 213.
And a circuit for preventing an excessive voltage from being applied between the emitter and the base of the transistors Q80 and Q81 to damage the transistors Q72 and Q73 and the transistors Q80 and Q81. Further, the transistors Q25, Q2
6, Q29 are elements for avoiding saturation of the transistor Q28, and the transistors Q45, Q46, Q49
Is an element for avoiding saturation of the transistor Q48. The resistor R20, the transistors Q21 and Q24 and the resistor R40, and the transistors Q41 and Q44 receive an excessive voltage between the bases and the emitters of the transistors Q22 and Q23 and the transistors Q42 and Q43. This is an element for avoiding destruction.

The upper / lower limit voltage limiting circuit 210 is configured such that the operational amplifier 211 controls the input voltage V _in 1 and the input voltage V in
The difference voltage of _in 2 is amplified and output to the multiplier 212. The multiplier 212 multiplies (A × αB) the A input and the B input input from the operational amplifier 214 and outputs the result to the multiplier 213. . The multiplier 213 is connected to the A input and the operational amplifier 215
Is multiplied (A × αB) by the input B and output as an output voltage V _OUT . The output voltage V _OUT output from the multiplier 213 is input to the operational amplifier 214 and the operational amplifier 215, and is fed back to the operational amplifier 211 via the resistor Rf2. The operational amplifier 214 further receives the lower limit setting voltage V _LL. The upper limit voltage V _LU is further input to the operational amplifier 215. The operational amplifier 214 amplifies the difference voltage between the output voltage V _OUT from the multiplier 213 and the lower limit set voltage V _LL and outputs the amplified voltage to the multiplier 212,
5 amplifies the difference voltage between the output voltage V _OUT from the multiplier 213 and the upper limit voltage V _LU and outputs the amplified voltage to the multiplier 213. When the output voltage V _OUT of the multiplier 213 is larger than the lower limit set voltage V _{LL and} smaller than the upper limit voltage V _LU , the upper limit voltage limiting circuit 210 sets the output voltages of the operational amplifier 214 and the operational amplifier 215 to the positive side, respectively. In this state, the multiplier 212 and the multiplier 213 each perform an operation of (A × 1). Therefore, the output voltage V
_OUT becomes the same output voltage as in the case of only the operational amplifier _{211, V OUT = Rf2 / Rs2} * (V in 1-V in 2)
Becomes However, it is assumed that Rf1 / Rs1 = Rf2 / Rs2. The upper and lower limit voltage limiting circuit 210 outputs the output voltage V
_{When OUT} falls below the lower limit setting voltage V _LL , the output voltage of the operational amplifier 215 remains swinging to the positive side, but the output voltage of the operational amplifier 214 decreases in the negative direction, and the multiplier 212 It approaches the calculation of (A × 0). That is, the gain between the input of the operational amplifier 211 and the output voltage V _OUT decreases, and the output voltage V _OUT is limited to be substantially equal to the lower limit set voltage V _LL . Further, when the output voltage V _OUT rises above the upper limit voltage V _LU , the upper and lower limit voltage limiting circuit 210 keeps the output voltage of the operational amplifier 214 on the positive side, but the operational amplifier 215
Output voltage decreases in the negative direction, and the multiplier 213 outputs
It approaches the calculation of (A × 0). That is, the operational amplifier 21
The gain from the input of 1 to the output voltage V _OUT is reduced, and the output voltage V _OUT is limited to approximately the upper limit voltage V _LU .

As described above, the upper and lower limit voltage limiting circuit 210
Restricts the output voltage V _OUT to a voltage between the upper limit voltage V _LU and the lower limit setting voltage V _LL , and operates as an upper / lower voltage limit circuit.

As described above, the invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to the above, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

[0193]

According to the voltage limiting circuit of the present invention, the difference voltage between the output voltage of the signal amplifier for amplifying and outputting the input signal and a predetermined set limiting voltage is amplified by the amplifier.
When the output voltage of the amplifier exceeds a predetermined value, the magnitude of the input signal of the signal amplifier is limited by the input limiting circuit, so that the output voltage of the signal amplifier can be controlled with high accuracy while suppressing power consumption.
In addition, the voltage can be stably limited to the set limit voltage.

According to the voltage limiting circuit of the second aspect of the present invention, the difference voltage between the output voltage of the signal amplifier for amplifying and outputting the input signal and the predetermined first set limiting voltage is amplified by the first amplifier. Then, when the output voltage of the first amplifier exceeds a predetermined value, the magnitude of the input signal of the signal amplifier is limited by the first input limiting circuit, the output voltage of the signal amplifier and the predetermined second set limiting voltage When the output voltage of the second amplifier exceeds a predetermined value, the magnitude of the input signal of the signal amplifier is limited by the second input limiting circuit. The voltage can be accurately and stably limited between the first set limit voltage and the second set limit voltage while suppressing power consumption.

According to the voltage limiting circuit of the present invention, the output voltage of the signal amplifier that amplifies and outputs the input signal and the difference voltage between the output voltage of the analog multiplier and the predetermined set limiting voltage are amplified. The output voltage of the amplifier to be input to the analog multiplier, the analog multiplier performs a predetermined multiplication between the two input voltages and outputs the output voltage as an output voltage, and outputs the output voltage of the analog multiplier to the amplifier. Since the output voltage of the signal amplifier output through the analog multiplier is limited to the set limit voltage when input, the output voltage of the signal amplifier output through the analog multiplier is reduced while suppressing power consumption. It is possible to accurately and stably limit the voltage to the set limit voltage.

According to the voltage limiting circuit of the present invention, the output voltage of the signal amplifier for amplifying and outputting the input signal is input to the first analog multiplier, and the output of the first analog multiplier is output. An output voltage of a first amplifier, which is input to a second analog multiplier and amplifies a difference voltage between an output voltage of the second analog multiplier and a predetermined first set limit voltage; and a second analog multiplier And an output voltage of a second amplifier for amplifying a difference voltage between the output voltage of the second and the predetermined second set limit voltage, and input to the first and second analog multipliers, The multiplier performs predetermined multiplication between the two input voltages, and outputs the output of the signal amplifier output via the first analog multiplier and the second analog multiplier to the first set limit voltage and the second set limit voltage. The first and second analog multiply The output voltage of the outputted signal amplifier through, while suppressing power consumption, and high precision,
The voltage can be stably limited between the first set limit voltage and the second set limit voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a lower limit voltage limiting circuit to which a first embodiment of a voltage limiting circuit according to the present invention is applied.

FIG. 2 is a circuit diagram of a lower limit voltage limiting circuit to which a second embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 3 is a circuit diagram of a lower limit voltage limiting circuit to which a third embodiment of the voltage limiting circuit according to the present invention is applied;

FIG. 4 is a circuit diagram of a lower limit voltage limiting circuit to which a fourth embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 5 is a circuit diagram of an upper limit voltage limiting circuit to which a fifth embodiment of the voltage limiting circuit according to the present invention is applied.

FIG. 6 is a circuit diagram of an upper limit voltage limiting circuit to which a sixth embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 7 is a circuit diagram of an upper limit voltage limiting circuit to which a seventh embodiment of the voltage limiting circuit according to the present invention is applied;

FIG. 8 is a circuit diagram of an upper limit voltage limiting circuit to which an eighth embodiment of the voltage limiting circuit according to the present invention is applied.

FIG. 9 is a circuit diagram of a lower limit voltage limiting circuit showing a specific embodiment of the lower limit voltage limiting circuit shown in FIG. 3;

FIG. 10 shows a specific example of the upper limit voltage limiting circuit shown in FIG.
FIG. 3 is a circuit diagram of an upper limit voltage limiting circuit showing an embodiment.

FIG. 11 is a circuit diagram of an upper / lower limit voltage limiting circuit to which a ninth embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 12 is a circuit diagram of an upper / lower limit voltage limiting circuit to which a tenth embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 13 is a circuit diagram of an upper / lower limit voltage limiting circuit to which an eleventh embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 14 is a circuit diagram of an upper / lower limit voltage limiting circuit to which a twelfth embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 15 is a circuit diagram of an upper and lower limit voltage limiting circuit showing a specific embodiment of the upper and lower limit voltage limiting circuit shown in FIG. 13;

FIG. 16 is a circuit diagram of a lower limit voltage limiting circuit to which a thirteenth embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 17 is a circuit diagram of an upper limit voltage limiting circuit to which a fourteenth embodiment of the voltage limiting circuit of the present invention is applied.

FIG. 18 is a circuit diagram of a lower limit voltage limiting circuit showing a specific embodiment of the lower limit voltage limiting circuit shown in FIG. 16;

FIG. 19 is a circuit diagram of an upper limit voltage limiting circuit showing a specific embodiment of the upper limit voltage limiting circuit shown in FIG. 17;

FIG. 20 is a circuit diagram of an upper / lower limit voltage limiting circuit to which a fifteenth embodiment of the voltage limiting circuit of the present invention is applied.

21 is a circuit diagram of an upper and lower limit voltage limiting circuit showing a specific embodiment of the upper and lower limit voltage limiting circuit shown in FIG. 20;

FIG. 22 is a circuit diagram of an example of a conventional lower limit voltage limiting circuit.

FIG. 23 is a circuit diagram of an example of a conventional upper limit voltage limiting circuit.

FIG. 24 is a circuit diagram of an example of a conventional upper and lower limit voltage limiting circuit.

[Explanation of symbols]

10, 20, 30, 40 Lower limit voltage limiter 11, 21, 31, 41 Input limiter 50, 60, 70, 80 Upper limit voltage limiter 51, 52, 53, 54 Input limiter A1, A2, A3 Operational amplifier R _in resistor Rf resistor Rs resistance D1, D2 diode V _LL limit setting voltage V _LU upper limit voltage V _OUT output voltage V _in the input voltage V _OUT output voltage Tr1, Tr2 transistor Q1~Q10, Q20~Q29, Q30~Q39 transistor R10, R20, R21, R30, R31 Resistance C1 Capacitor 90 Lower limit voltage limiting circuit 91 Non-inverting operational amplifier circuit 92 Operational amplifier 93 Input limiting circuit 100 Upper limit voltage limiting circuit 101 Non-inverting operational amplifier circuit 102 Operational amplifier 103 Input limiting circuit 110, 120, 130, 140, 150 Upper and lower limit voltage limiting circuit 11 , 112, 121, 122, 131 input limiting circuit 132, 141, 142 input limiting circuit 151 non-inverting operational amplifier 152 operational amplifier 153 operational amplifier 154 input limiting circuit 160 lower limit voltage limiting circuit 170 upper limit voltage limiting circuit 180 lower limit voltage limiting circuit 181 , 183 Operational amplifier 182 Multiplier 190 Upper limit voltage limiting circuit 191, 193 Operational amplifier 192 multiplier 200, 210 Upper and lower limit voltage limiting circuit Rs1, Rs2, Rf1, Rf2 Resistance R40, R41 Resistance M1, M2 Multipliers Q40-Q51, Q60 To Q69, Q72 to Q75 Transistors Q80, Q81, Q84, Q85 Transistors

Claims (4)

[Claims] A signal amplifier for amplifying an input signal and outputting the amplified signal; an amplifier for amplifying a difference voltage between an output voltage of the signal amplifier and a predetermined set limit voltage; An input limiting circuit for limiting the magnitude of the input signal input to the signal amplifier, wherein an output voltage of the signal amplifier is limited to the set limiting voltage. 2. A signal amplifier for amplifying and outputting an input signal, a first amplifier for amplifying a difference voltage between an output voltage of the signal amplifier and a predetermined first set limiting voltage, and the first amplifier A first input limiting circuit that limits the magnitude of the input signal input to the signal amplifier when the output voltage of the signal amplifier exceeds a predetermined value, and the output voltage of the signal amplifier and the first set limiting voltage are different. A second amplifier for amplifying a difference voltage from a predetermined second set limiting voltage, and limiting the magnitude of the input signal input to the signal amplifier when the output voltage of the second amplifier exceeds a certain value. A second input limiting circuit that limits an output voltage of the signal amplifier between the first set limiting voltage and the second set limiting voltage. 3. A signal amplifier for amplifying and outputting an input signal, and an analog multiplier having two input terminals and performing a predetermined multiplication of input voltages input to the two input terminals and outputting the result. An amplifier for amplifying a difference voltage between the output voltage of the analog multiplier and a predetermined set limit voltage, wherein the output voltage of the signal amplifier is input to one input terminal of the analog multiplier, A voltage limiting circuit which inputs an output voltage to the other input terminal of the analog multiplier and limits an output of the signal amplifier output via the analog multiplier to the set limiting voltage. 4. A signal amplifier which amplifies and outputs an input signal, and a first analog which has two input terminals and performs predetermined multiplication of input voltages input to the two input terminals and outputs the result. A multiplier, a second analog multiplier having two input terminals, performing a predetermined multiplication between input voltages input to the two input terminals and outputting the result, and an output of the second analog multiplier A first amplifier for amplifying a difference voltage between a voltage and a predetermined first set limit voltage, and a predetermined second setting different from the output voltage of the second analog multiplier and the first set limit voltage A second amplifier that amplifies a difference voltage from the limit voltage, and an output voltage of the signal amplifier is input to one input terminal of the first analog multiplier, and an output of the first analog multiplier is output. Into one input terminal of the second analog multiplier. Inputting the output voltage of the first amplifier and the output voltage of the second amplifier to the other input terminals of the first analog multiplier and the second analog multiplier, respectively, A voltage limiting circuit for limiting an output of the signal amplifier output via a multiplier and the second analog multiplier between the first set limit voltage and the second set voltage. .