JPH10242373A - Semiconductor chip package - Google Patents

Semiconductor chip package

Info

Publication number
JPH10242373A
JPH10242373A JP9314876A JP31487697A JPH10242373A JP H10242373 A JPH10242373 A JP H10242373A JP 9314876 A JP9314876 A JP 9314876A JP 31487697 A JP31487697 A JP 31487697A JP H10242373 A JPH10242373 A JP H10242373A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead
chip package
internal
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9314876A
Other languages
Japanese (ja)
Other versions
JP2981194B2 (en
Inventor
Do-Su Jeung
道秀 鄭
Oh-Sik Kwon
五植 權
Eiki So
泳僖 宋
Binhin Nin
旻彬 任
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH10242373A publication Critical patent/JPH10242373A/en
Application granted granted Critical
Publication of JP2981194B2 publication Critical patent/JP2981194B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip package in which a high-integration- degree semiconductor chip is mounted by using an LOC structure. SOLUTION: A semiconductor chip 40 is provided with central electrode pads 48 which are arranged in the center of an active face along respective long sides 42 of the semiconductor chip 40 and with peripheral electrode pads 49 which are arranged along respective peripheral parts of its short sides 44. In addition, inner leads at a lead frame are provided with first inner leads 10, of LOC structure, which are attached to the active face 46 and with second inner leads 12, of standard type, which are arranged so as to be separated from the semiconductor chip 40. The first inner leads 10 are connected electrically to the central electrode pads 48 by a wire bonding operation or by metal bumps, and the second inner leads 12 are connected electrically to the peripheral electrode pads 49 by a wire bonding operation. When the bend size of the first internal leads 10 is adjusted, an optimum vertical structure at the inside of a semiconductor chip package 200 can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップパッ
ケージに関し、より詳細には、チップ縮小技術等により
集積度が高まった半導体素子を効果的に実装するため、
ＬＯＣリードと標準型リードが複合された構造を有する
半導体チップパッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package, and more particularly to a semiconductor chip package for effectively mounting a semiconductor element having a high degree of integration by a chip shrinking technique.
The present invention relates to a semiconductor chip package having a structure in which an LOC lead and a standard lead are combined.

【０００２】[0002]

【従来の技術】半導体チップには、内部回路素子を外部
素子と電気的に連結するため、半導体チップの活性面に
複数の電極パッドが形成されている。電極パッドの配列
によって半導体チップを区分すると、電極パットがチッ
プ活性面の中央に配列される中央パッド型と、電極パッ
トがチップ活性面の周辺に形成される周辺パッド型とで
分けられる。中央パッド型半導体チップは、周辺パッド
型に比べて信号伝達差が減少し、信号伝達通路が短くな
って高速化に有利であり、電極パッドの設計が容易にな
るという利点を有する。また、同一の容量と機能を有す
る半導体メモリチップを中央パッド型に設計すると、周
辺パッド型に比べてチップのサイズを４％乃至７％程度
減少させることができるので、１つのウェーハから製造
されるチップの数が増加し、生産性及び歩留まりが向上
する。このため、現在大部分のメモリチップは、中央パ
ッド型に設計されている。2. Description of the Related Art A plurality of electrode pads are formed on an active surface of a semiconductor chip in order to electrically connect an internal circuit element to an external element. When the semiconductor chip is divided according to the arrangement of the electrode pads, the semiconductor chip is divided into a central pad type in which the electrode pads are arranged at the center of the chip active surface and a peripheral pad type in which the electrode pads are formed around the chip active surface. The central pad type semiconductor chip has an advantage in that the signal transmission difference is reduced, the signal transmission path is shortened and the speed is increased, and the design of the electrode pads is facilitated, as compared with the peripheral pad type semiconductor chip. Also, when semiconductor memory chips having the same capacity and function are designed as a central pad type, the chip size can be reduced by about 4% to 7% as compared with the peripheral pad type, so that the semiconductor memory chips are manufactured from one wafer. The number of chips increases, and productivity and yield improve. For this reason, most memory chips are currently designed with a central pad type.

【０００３】中央パッド型半導体チップを組立るために
は、リードがチップの活性面上に延設されて取付けられ
るＬＯＣ構造を採択するか、リードがチップの端部から
離れて配列される標準型リードと中央電極パッドとをワ
イヤボンディングする方法を使用することができる。し
かし、後者は、ボンディングワイヤの長さが非常に長く
なるため、信頼性が低下し、実際生産に適用するには難
しい点が多い。一方、ＬＯＣ構造を採択する場合、リー
ドフレームの製造において、標準型リードフレームに比
べて費用が多くかかるが、ボンディングワイヤの長さが
短くて信頼性がよくなり、１つのウェーハから製造する
ことができるチップの数が増加するため、全体的に費用
節減が可能であるので、現在メモリ製品に幅広く適用さ
れている。In order to assemble a center pad type semiconductor chip, a LOC structure in which leads extend and are mounted on an active surface of the chip is adopted, or a standard type in which the leads are arranged away from the end of the chip. A method of wire bonding the lead and the center electrode pad can be used. However, in the latter case, since the length of the bonding wire is very long, the reliability is reduced, and there are many points that are difficult to apply to actual production. On the other hand, in the case of adopting the LOC structure, the cost of manufacturing the lead frame is higher than that of the standard type lead frame, but the bonding wire length is short and the reliability is improved, so that it is possible to manufacture from one wafer. Since the number of chips that can be formed is increased, cost can be reduced as a whole, and thus it is widely applied to memory products.

【０００４】ＬＯＣパッケージは、リードフレームのリ
ードがチップの活性面に取付けられるため、リードが占
める面積が減少し、半導体チップとパッケージのサイズ
比を大いに向上させることができる。例えば、一般的な
構造のパッケージでは、サイズ比を最大６０％まで向上
させることができ、半導体チップがリード上に取付けら
れるＣＯＬパッケージでは、サイズ比を最大７０％まで
向上させることができるが、ＬＯＣパッケージでは、サ
イズ比を最大９０％まで高めることができる。半導体チ
ップとパッケージのサイズ比が向上すると、実装密度が
高まり、チップを狭い空間にパッケージ形態で実装する
ことができる。そこで現在、ＬＯＣパッケージ技術は、
主に大型チップの実装に焦点を合わせて開発されてい
る。In the LOC package, since the lead of the lead frame is attached to the active surface of the chip, the area occupied by the lead is reduced, and the size ratio between the semiconductor chip and the package can be greatly improved. For example, in a package having a general structure, the size ratio can be increased up to 60%, and in a COL package in which a semiconductor chip is mounted on a lead, the size ratio can be increased up to 70%. In the package, the size ratio can be increased up to 90%. As the size ratio between the semiconductor chip and the package increases, the mounting density increases, and the chip can be mounted in a narrow space in a package form. Therefore, at present, LOC package technology
It has been developed mainly focusing on large chip mounting.

【０００５】[0005]

【発明が解決しようとする課題】ところが、同一容量の
メモリチップは、微細加工技術の持続的な発達により、
初期１世代メモリチップに比べて次世代メモリチップの
サイズが縮小され、集積度が高まる。メモリチップの縮
小は、１世代メモリチップサイズの約７０％までなされ
る。したがって、単位ウェーハ当たり製造されるメモリ
チップの数が増加し、歩留まりが向上するため、ＬＯＣ
パッケージ技術はメモリチップの製造会社で必修的に使
用される技術の１つである。However, memory chips of the same capacity have been developed due to the continuous development of fine processing technology.
The size of the next generation memory chip is reduced and the degree of integration is increased compared to the initial one generation memory chip. Memory chips are reduced to about 70% of the first generation memory chip size. Therefore, the number of memory chips manufactured per unit wafer is increased, and the yield is improved.
Package technology is one of the technologies that are required by memory chip manufacturers.

【０００６】しかるに、チップ縮小技術等によりメモリ
チップの集積度が向上すると、組立工程で技術的難点が
発生する。例えば、ＬＯＣ構造を採択してメモりチップ
を組立る場合、リードフレーム加工技術がチップ縮小技
術を追いつかないため、活性面の面積が減少した次世代
メモリチップ上にリードフレームのリードを全部配置す
ることができない。リードフレームは、スタンピング工
程やエッチング工程により製造され、リードフレームリ
ードの幅や間隔は、リードフレーム厚さの約８０％以上
になる場合にのみ、所望のパターンを有するリードを形
成することができる。このようなリードフレームの加工
限界を克服するため、リードフレームの厚さを低減する
と、微細パターンのリードを製造することができ、チッ
プ縮小技術により活性面が減少したメモリチップにリー
ドフレームのリードを全て配置することができる。しか
し、リードフレームの厚さが非常に小さい場合、組立工
程時に小さい衝撃によりリードが損傷されるので、リー
ドフレームの厚さを低減することは、リードフレーム加
工技術の限界を克服し、半導体チップの高集積化に対応
するための適切な方案にならない。However, if the degree of integration of memory chips is improved by chip shrinking technology or the like, technical difficulties occur in the assembly process. For example, when assembling a memory chip by adopting the LOC structure, since the lead frame processing technology cannot keep up with the chip reduction technology, all the leads of the lead frame are arranged on a next-generation memory chip having a reduced active surface area. Can not do. The lead frame is manufactured by a stamping process or an etching process, and a lead having a desired pattern can be formed only when the width and the interval of the lead frame lead are about 80% or more of the lead frame thickness. Reducing the thickness of the lead frame to overcome the processing limit of the lead frame can produce fine pattern leads, and the lead frame leads can be mounted on memory chips whose active surface has been reduced by chip reduction technology. All can be arranged. However, when the thickness of the lead frame is very small, the lead may be damaged by a small impact during the assembling process, so reducing the thickness of the lead frame overcomes the limitations of the lead frame processing technology and reduces the size of the semiconductor chip. It is not an appropriate plan to cope with high integration.

【０００７】したがって、チップ縮小技術等により集積
度が高まった半導体チップを、中央パッド型半導体チッ
プの利点とＬＯＣ構造の利点を生かしながら実装するた
めの新たな構造の半導体チップパッケージが必要にな
る。本発明の目的は、高集積度の半導体チップをＬＯＣ
構造を用いて実装する半導体チップパッケージを提供す
ることにある。Therefore, a semiconductor chip package having a new structure for mounting a semiconductor chip having an increased degree of integration by chip reduction technology or the like while taking advantage of the advantages of the center pad type semiconductor chip and the advantages of the LOC structure is required. An object of the present invention is to integrate a highly integrated semiconductor chip into a LOC.
An object of the present invention is to provide a semiconductor chip package mounted using a structure.

【０００８】本発明の他の目的は、リードフレーム加工
限界を克服し、高集積度の半導体チップを実装すること
ができる半導体チップパッケージを提供することにあ
る。Another object of the present invention is to provide a semiconductor chip package capable of overcoming the processing limit of a lead frame and mounting a highly integrated semiconductor chip.

【０００９】[0009]

【課題を解決するための手段】本発明による半導体チッ
プパッケージは、活性面の中央部に配列される複数の中
央電極パッド、及び活性面の周辺部に配列される複数の
周辺電極パッドが複合された構造を有する半導体チップ
と、中央電極パッドを介して半導体チップと電気的に連
結され、チップ活性面に取付けられる第１内部リード、
及び周辺電極パッドを介して半導体チップと電気的に連
結され、チップの端部から離れて配列される第２内部リ
ードを有するリードフレームとを備える。A semiconductor chip package according to the present invention is composed of a plurality of central electrode pads arranged at the center of the active surface and a plurality of peripheral electrode pads arranged at the periphery of the active surface. A semiconductor chip having a bent structure, a first internal lead electrically connected to the semiconductor chip via the central electrode pad, and attached to the chip active surface;
And a lead frame electrically connected to the semiconductor chip via the peripheral electrode pad and having a second internal lead arranged away from an end of the chip.

【００１０】半導体チップは通常短辺及び長辺を有し、
半導体チップの電極パッドと電気的に連結される内部リ
ードと一体に形成される外部リードが、半導体チップの
短辺及び長辺に沿って配列されるようにすることによ
り、カード(quad)型半導体チップパッケージを実現する
ことができる。一方、外部リードが半導体チップの長辺
に沿って配列されるようにすれば、デュアル(dual)型半
導体チップパッケージを実現することができる。A semiconductor chip usually has a short side and a long side,
The external leads formed integrally with the internal leads electrically connected to the electrode pads of the semiconductor chip are arranged along the short side and the long side of the semiconductor chip, so that a card (quad) semiconductor A chip package can be realized. On the other hand, if the external leads are arranged along the long side of the semiconductor chip, a dual type semiconductor chip package can be realized.

【００１１】半導体チップパッケージに使用されるリー
ドフレームは、コーナーリードとリードフレームのサイ
ドレールとの間に連結されるタイバーを備え、これによ
り、パッケージ素子が最終的に個別化される前に、組立
工程で個別パッケージ素子をストリップ形態で維持し、
また長さが非常に長いコーナーリードが組立工程中に変
形されることを防止する。また、リードフレームは、リ
ードフレームリードに半導体チップを取付けるとき、ま
たは半導体チップの電極パッドとリードフレームリード
とを電気的に連結するとき、リードと半導体チップの位
置を認識して整列を容易にするための整列キーを備える
ことができる。A lead frame used in a semiconductor chip package has a tie bar connected between a corner lead and a side rail of the lead frame, so that the package element can be assembled before it is finally individualized. In the process, maintain the individual package elements in strip form,
It also prevents corner leads that are very long from being deformed during the assembly process. Also, when mounting the semiconductor chip on the lead frame lead or electrically connecting the electrode pads of the semiconductor chip to the lead frame lead, the lead frame recognizes the position of the lead and the semiconductor chip to facilitate alignment. An alignment key can be provided.

【００１２】ＬＯＣ構造の第１内部リードには屈曲部が
形成され、屈曲のサイズは、第１内部リードをチップ活
性面に取付ける接着剤の厚さ、半導体チップの厚さ等を
考慮して決定され、屈曲のサイズを調節することによ
り、半導体チップがパッケージ胴体の中央に位置する最
適の垂直構造を実現する。A bent portion is formed in the first internal lead of the LOC structure, and the size of the bend is determined in consideration of the thickness of the adhesive for attaching the first internal lead to the chip active surface, the thickness of the semiconductor chip, and the like. By adjusting the size of the bend, an optimum vertical structure in which the semiconductor chip is located at the center of the package body is realized.

【００１３】[0013]

【発明の実施の形態】以下、図面を参照として本発明を
詳細に説明する。図１は、本発明による半導体チップパ
ッケージに適合するリードフレームストリップの部分平
面図である。リードフレームストリップ１００は、同一
のリードフレームパターンが繰り返されているので、複
数の半導体チップを実装してダイボンディング、ワイヤ
ボンディング及びモールディング工程等のような組立工
程を同時に進行することができる。移送用孔１６は、組
立工程中又は組立工程の間でリードフレームストリップ
１００を移送するに使用される。同一のパターンで繰り
返される単位リードフレームは、分離スロット２２によ
り区分される。図１には、１つの単位リードフレームに
該当するパターンだけを図示した。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a partial plan view of a lead frame strip adapted to a semiconductor chip package according to the present invention. Since the same lead frame pattern is repeated on the lead frame strip 100, a plurality of semiconductor chips can be mounted and assembly processes such as die bonding, wire bonding, and molding can be performed simultaneously. The transfer holes 16 are used to transfer the lead frame strip 100 during or during the assembly process. Unit lead frames repeated in the same pattern are separated by separation slots 22. FIG. 1 shows only a pattern corresponding to one unit lead frame.

【００１４】単位リードフレームは、半導体チップの図
示しない電極パッドと電気的に連結される複数の内部リ
ード１０、１２と、半導体チップを外部と電気的に連結
する複数の外部リード１４ａ、１４ｂとを有する。内部
リードと外部リードは、ダムバー(dam bar) ２８により
連結されている。ダムバー２８は、図１で一点鎖点で表
示したモールディング領域３４内にプラスチックモール
ディング樹脂を充填してパッケージ胴体を形成するモー
ルディング工程において、モールディング樹脂がモール
ディング領域３４外に流れ出すことを防止するためのも
のである。モールディング工程が終わると、ダムバー２
８を切断し、タイバー１８を切断することにより、全体
的に連結されている複数の内部リード及び外部リードを
個別化させる。The unit lead frame includes a plurality of internal leads 10 and 12 electrically connected to an electrode pad (not shown) of the semiconductor chip and a plurality of external leads 14a and 14b electrically connecting the semiconductor chip to the outside. Have. The inner and outer leads are connected by a dam bar 28. The dam bar 28 is used to prevent the molding resin from flowing out of the molding region 34 in a molding process of forming a package body by filling a plastic molding resin into the molding region 34 indicated by a chain line in FIG. It is. When the molding process is over, dam bar 2
By cutting the tie bar 18 and the tie bar 18, a plurality of internal leads and external leads connected to each other are individually separated.

【００１５】サイドレール２４は、単位リードフレーム
をストリップ形態で維持するためのものである。モール
ディング領域３４の４つのコーナーに位置するコーナー
リード１５には、サイドレール２４と連結されているタ
イバー１８が形成されている。タイバー１８は、コーナ
ーリード１５とサイドレール２４とを連結するものであ
って、ダムバー２８を切断した後、最終的に単位素子で
個別化するまで単位リードフレームをサイドレール２４
に連結させる役割をし、且つ組立工程の進行中に長さが
最も長いコーナーリード１５の変形を防止する役割をす
る。The side rails 24 are for maintaining the unit lead frame in a strip form. The tie bars 18 connected to the side rails 24 are formed on the corner leads 15 located at the four corners of the molding area 34. The tie bar 18 connects the corner lead 15 and the side rail 24. After cutting the dam bar 28, the unit lead frame is connected to the side rail 24 until it is finally individualized by unit elements.
And prevents deformation of the longest corner lead 15 during the assembly process.

【００１６】ダミーリード２０は、半導体チップと連結
されないリードであり、電源供給用リード２６は、陽の
電源ＶＤＤと陰の電源ＶＳＳのような電源を半導体チッ
プに供給するための通路である。電源供給用リード２６
は、リードのインダクタンス成分を減少させるため、２
つに分岐される構造を有する。リードフレームリードの
うち、中央側に延設される第１内部リード１０は、ＬＯ
Ｃ構造のリードであり、第２内部リード１２は、標準型
リードである。第１内部リード１０は、接着剤３２によ
り半導体チップの活性面に直接取付けられ、屈曲部３０
を有する。このような構造を有するリードフレームは、
中央電極パッドと周辺電極パッドが組合わされた半導体
チップを組立るのに適合する。The dummy lead 20 is a lead not connected to the semiconductor chip, and the power supply lead 26 is a path for supplying power to the semiconductor chip, such as a positive power supply VDD and a negative power supply VSS. Power supply lead 26
Reduces the inductance component of the lead by 2
It has a structure that is branched into two. Among the lead frame leads, the first internal lead 10 extending to the center side is
The lead is a C-structure lead, and the second internal lead 12 is a standard lead. The first internal lead 10 is directly attached to the active surface of the semiconductor chip by an adhesive 32,
Having. The lead frame having such a structure,
It is suitable for assembling a semiconductor chip in which a center electrode pad and a peripheral electrode pad are combined.

【００１７】このように組立られた半導体チップパッケ
ージの一例について説明する。図２は、本発明の一実施
例による半導体チップパッケージの分解平面図である。
半導体チップパッケージ２００は、１００個の入出力ピ
ンを有する。図２において、各々の入出力ピンには、ピ
ン番号が記載されており、該当ピンを介して伝達される
信号によるピン名前が表示されているが、これに対する
詳細な説明は省略する。但し、ＶＤＤは、半導体チップ
４０に供給される陽の電源電圧、ＶＳＳは、陰の電源電
圧を意味する。An example of the semiconductor chip package assembled as described above will be described. FIG. 2 is an exploded plan view of a semiconductor chip package according to an embodiment of the present invention.
The semiconductor chip package 200 has 100 input / output pins. In FIG. 2, a pin number is described for each input / output pin, and a pin name based on a signal transmitted through the corresponding pin is displayed, but a detailed description thereof will be omitted. Here, VDD indicates a positive power supply voltage supplied to the semiconductor chip 40, and VSS indicates a negative power supply voltage.

【００１８】半導体チップ４０は、長辺４２と短辺４４
を有する。このような矩形構造は、半導体メモリチップ
に一般的に使用されている。半導体チップ４０の活性面
４６には、複数の電極パッド４８、４９が形成されてお
り、活性面の中央部分に２列に並設される中央電極パッ
ド４８と、活性面の短辺の周辺部に沿って配列されてい
る周辺電極パッド４９とで分けられる。The semiconductor chip 40 has a long side 42 and a short side 44
Having. Such a rectangular structure is generally used for a semiconductor memory chip. A plurality of electrode pads 48 and 49 are formed on the active surface 46 of the semiconductor chip 40. The central electrode pads 48 are arranged in two rows at the central portion of the active surface, and the peripheral portion on the short side of the active surface. And the peripheral electrode pads 49 arranged along.

【００１９】内部リードのうち、接着剤３２が取付けら
れている複数の第１内部リード１０は、半導体チップ４
０の活性面４６上に接着されるＬＯＣ構造を有し、半導
体チップの長辺４２に沿って配列されている。複数の第
１内部リード１０は、ボンディングワイヤ５２により中
央電極パッド４８に電気的に連結され、半導体チップの
長辺に沿って配列されている第１外部リード１４ａに連
結される。Among the internal leads, the plurality of first internal leads 10 to which the adhesive 32 is attached are connected to the semiconductor chip 4.
The semiconductor chip has a LOC structure bonded on the active surface 46 and is arranged along the long side 42 of the semiconductor chip. The plurality of first internal leads 10 are electrically connected to the center electrode pad 48 by bonding wires 52, and are connected to the first external leads 14a arranged along the long side of the semiconductor chip.

【００２０】接着剤３２は、電気絶縁性であり、例え
ば、ポリイミド系の両面接着テープを使用する。接着テ
ープを複数の第１内部リードに取付け、内部リードをチ
ップの活性面に載置した後、熱圧着方式により第１内部
リードを半導体チップの活性面に取付ける。接着テープ
を使用せずに、不完全硬化状態の接着剤をチップ活性面
に塗布した後、第１内部リードを活性面に載置し、熱と
圧力を加えて第１内部リードをチップの活性面に取付け
る方法を使用することもできる。The adhesive 32 is electrically insulating, and uses, for example, a polyimide double-sided adhesive tape. After the adhesive tape is attached to the plurality of first internal leads and the internal leads are placed on the active surface of the chip, the first internal leads are attached to the active surface of the semiconductor chip by a thermocompression bonding method. After applying an incompletely cured adhesive to the active surface of the chip without using an adhesive tape, the first internal lead is placed on the active surface, and the first internal lead is activated by applying heat and pressure. Surface mounting methods can also be used.

【００２１】一方、複数の第２内部リード１２は、半導
体チップの短辺４４に沿って配列されているが、第１内
部リード１０とは別に、活性面４６に接着されなく、チ
ップの短辺４４から離れている標準型リード構造を有す
る。複数の第２内部リード１２は、ボンディングワイヤ
５２により周辺電極パッド４９に電気的に連結され、半
導体チップの短辺に沿って配列されている第２外部リー
ド１４ｂに連結される。On the other hand, the plurality of second internal leads 12 are arranged along the short side 44 of the semiconductor chip. It has a standard lead structure remote from 44. The plurality of second internal leads 12 are electrically connected to the peripheral electrode pads 49 by bonding wires 52, and are connected to the second external leads 14b arranged along the short side of the semiconductor chip.

【００２２】このように、ＬＯＣ構造の第１内部リード
と標準型構造の第２内部リードが複合された構造を有す
るリードフレームを使用することにより、リードフレー
ムの加工限界を克服し、高集積度のメモリ素子を実装す
ることが可能である。また、半導体チップは、中央パッ
ド型と周辺パッド型が複合された電極パッドを有するた
め、信号伝達差減少、信号伝達通路の縮小、容易な電極
パッドの設計及びチップサイズの減少等の利点が得られ
る。As described above, by using a lead frame having a structure in which the first internal lead having the LOC structure and the second internal lead having the standard structure are combined, the processing limit of the lead frame can be overcome and the high integration degree can be achieved. Can be mounted. Further, since the semiconductor chip has an electrode pad in which the center pad type and the peripheral pad type are combined, advantages such as a reduction in signal transmission difference, a reduction in signal transmission path, an easy electrode pad design and a reduction in chip size are obtained. Can be

【００２３】周辺電極パッド４９は、接着剤３２と一定
距離Ｄだけ離れるべきである。距離Ｄは、リードフレー
ムの製造公差、パッケージ組立公差、及び周辺電極パッ
ドとワイヤをボンディングするキャピラリと第１内部リ
ードとの接触等を考慮して決定され、最小限２０ｍｉｌ
以上の距離Ｄを維持しなければならない。ピン番号３６
〜４５及び８６〜９５に該当するリードは、電気的連結
がなされないダミーリード２０であり、これは、特定メ
モリ素子に対して定められたパッケージ外観規格による
外部リードのピン数と、実際実装されるメモリ素子の特
性によって必要なピン数との差異によって生ずるもので
ある。The peripheral electrode pad 49 should be separated from the adhesive 32 by a fixed distance D. The distance D is determined in consideration of the manufacturing tolerance of the lead frame, the package assembly tolerance, and the contact between the capillary for bonding the peripheral electrode pad and the wire and the first internal lead, and is at least 20 mil.
The above distance D must be maintained. Pin number 36
45 and 86 to 95 are dummy leads 20 that are not electrically connected, and correspond to the number of pins of external leads according to a package appearance standard defined for a specific memory element and the number of actual mounted leads. This is caused by the difference from the required number of pins depending on the characteristics of the memory element.

【００２４】第１内部リードには、整列キー５０が形成
されており、これは、第１内部リードに半導体チップを
取付けるとき、半導体チップ４０とリードフレームリー
ドの位置を認識して正確な整列がなされるようにするた
めのものである。また、整列キー５０は、半導体チップ
４０の電極パッド４８、４９と内部リード１０、１２と
を電気的に連結するワイヤボンディング工程において、
半導体チップ４０とリード１０、１２の位置を認識する
のに使用することができる。整列キー５０は、スタンピ
ングやエッチングによりリードフレームパターンを形成
するときに形成され、リードフレームと同一の材質より
なる。An alignment key 50 is formed on the first internal lead, and when the semiconductor chip is mounted on the first internal lead, the alignment between the semiconductor chip 40 and the lead frame lead is recognized and accurate alignment is performed. It is to be done. Further, the alignment key 50 is used in a wire bonding process for electrically connecting the electrode pads 48 and 49 of the semiconductor chip 40 and the internal leads 10 and 12.
It can be used to recognize the positions of the semiconductor chip 40 and the leads 10 and 12. The alignment key 50 is formed when a lead frame pattern is formed by stamping or etching, and is made of the same material as the lead frame.

【００２５】電源供給用リード２６は、半導体チップ４
０に例えばＶＤＤとＶＳＳの電源を供給するためのリー
ドであって、電極パッドにワイヤボンディングされる先
端が２つに分岐する構造を有する。このように電源供給
通路を並列にすると、リードのインダクタンス成分を減
少させることができ、より安定的な電源供給が可能であ
る。The power supply lead 26 is connected to the semiconductor chip 4
0 is a lead for supplying power of, for example, VDD and VSS, and has a structure in which a tip to be wire-bonded to an electrode pad is branched into two. When the power supply paths are arranged in parallel in this manner, the inductance component of the leads can be reduced, and more stable power supply can be achieved.

【００２６】供給電源の安定のため、例えば図３に示す
ように、バスバー構造を採用することができる。バスバ
ー５６は、同一の電源を供給するリードを１つの通路で
連結させる。従って、電源を素子の各部分に一定のレベ
ルで供給することができ、雑音の影響を受けることが少
ない。図３を参照すると、第１内部リード１０の中で、
ピン番号５、１１、１９は、陰の電源電圧が供給され、
このピンに該当する内部リードは、バスバー５６ａによ
り１つに連結されている。また、ピン番号５９、６７、
７３、７９に該当する内部リードは、バスバー５６ｂに
より１つに連結され、陽の電源電圧が印可される。For stabilizing the power supply, for example, a bus bar structure can be adopted as shown in FIG. The bus bar 56 connects leads for supplying the same power supply in one passage. Therefore, power can be supplied to each part of the element at a constant level, and there is little influence of noise. Referring to FIG. 3, among the first internal leads 10,
Pin numbers 5, 11, and 19 are supplied with a negative power supply voltage,
The internal lead corresponding to this pin is connected to one by a bus bar 56a. Also, pin numbers 59, 67,
The internal leads corresponding to 73 and 79 are connected together by a bus bar 56b, and a positive power supply voltage is applied.

【００２７】一方、図２に示すように、第１内部リード
１０は、チップの活性面４６に取付けられるとき、フュ
ーズボックス５４を回避することができるように配置し
なければならない。フューズボックス５４は、メモリチ
ップの不良メモリセルを余分のメモリセルに交換するた
めのものであって、レーザー等で切断されることができ
るように、アルミニウム線が露出された部分を有する。
フューズボックス５４が第１内部リード１０に被覆され
ていると、レーザー切断が不可能になる。On the other hand, as shown in FIG. 2, the first internal lead 10 must be arranged so as to avoid the fuse box 54 when attached to the active surface 46 of the chip. The fuse box 54 is for replacing a defective memory cell of a memory chip with an extra memory cell, and has a portion where an aluminum line is exposed so that it can be cut by a laser or the like.
If the fuse box 54 is covered with the first internal lead 10, laser cutting becomes impossible.

【００２８】複数の第１内部リードは、図４に示すよう
に、屈曲部３０を有している。図４は、図２のIV−IV線
に沿って切断した断面図である。第１内部リード１０に
屈曲を形成することは、半導体チップ４０がパッケージ
導体６０の中央に位置するようにするためのものであ
る。例えば、半導体チップ４０のサイズが１９７mil ×
３４０mil であり、チップの厚さｔが０．３mil であ
り、接着剤の厚さが０．１mil である場合、屈曲３０の
サイズｓを０．２milにして、半導体チップから上部パ
ッケージ胴体までの距離ｄ１（＝１．０５mil）と、下
部パッケージ胴体までの距離ｄ２（＝１．０５mil ）と
を同一にする。プラスチックパッケージ胴体は、トラン
スファモールディング工程により形成されるが、トラン
スファモールディング工程では、パッケージ胴体を成形
すべきキャビティに、ダイボンディング及びワイヤボン
ディングが完了されたリードフレームストリップを装着
し、液状のモールディング樹脂を高圧でキャビティに注
入する。もし、上部パッケージ胴体までの距離と、下部
パッケージ胴体までの距離が異なると、注入されるモー
ルディング樹脂の圧力が相異して、半導体チップが元の
位置からずれる不良が生ずることがある。これは、モー
ルディング工程後のパッケージ胴体の反りの原因となる
ことがある。したがって、本実施例のように、第１内部
リード１０に屈曲部３０を形成して上下部パッケージ胴
体の均衡を取ると、安定的な垂直構造を実現することが
可能である。屈曲のサイズｓが０．２mil のものについ
て説明したが、これは、例示的なものに過ぎないし、半
導体チップのサイズや厚さ等によって調節することがで
きる。Each of the plurality of first internal leads has a bent portion 30, as shown in FIG. FIG. 4 is a sectional view taken along the line IV-IV in FIG. The formation of the bends in the first internal leads 10 is for positioning the semiconductor chip 40 at the center of the package conductor 60. For example, the size of the semiconductor chip 40 is 197 mil ×
340 mil, the thickness t of the chip is 0.3 mil, and the thickness of the adhesive is 0.1 mil, the size s of the bend 30 is 0.2 mil, and the distance from the semiconductor chip to the upper package body is The distance d1 (= 1.05 mil) to the lower package body is made equal to d1 (= 1.05 mil). The plastic package body is formed by a transfer molding process. In the transfer molding process, a lead frame strip on which die bonding and wire bonding have been completed is mounted in a cavity where the package body is to be molded, and the liquid molding resin is subjected to high pressure. Inject into cavity. If the distance to the upper package body is different from the distance to the lower package body, the pressure of the injected molding resin may be different, which may cause a defect that the semiconductor chip deviates from its original position. This may cause the package body to warp after the molding process. Therefore, when the bent portion 30 is formed in the first internal lead 10 and the upper and lower package bodies are balanced as in the present embodiment, a stable vertical structure can be realized. Although the case where the bending size s is 0.2 mil has been described, this is merely an example, and can be adjusted by the size and thickness of the semiconductor chip.

【００２９】図５は、図２のＶ−Ｖ線に沿って切断した
断面図である。上述したように、周辺電極パッド４９
は、半導体チップ４０の短辺に沿って配設されており、
ボンディングワイヤ５９により第２内部リード１２に電
気的に連結されている。第２内部リード１２は、半導体
チップ４０から離れて配設された標準型リードである。
半導体チップパッケージ２００では、内部リード１２、
１０及び電極パッド４９、４８がボンディングワイヤ５
９により電気的に連結される。しかしながら、チップの
活性面４６上に取付けられる第１内部リード１０は、金
属バンプにより電極パッドと電気的に接続されることも
可能である。FIG. 5 is a sectional view taken along the line VV of FIG. As described above, the peripheral electrode pad 49
Are arranged along the short side of the semiconductor chip 40,
It is electrically connected to the second internal lead 12 by a bonding wire 59. The second internal lead 12 is a standard type lead that is disposed apart from the semiconductor chip 40.
In the semiconductor chip package 200, the internal leads 12,
10 and the electrode pads 49 and 48 are the bonding wires 5
9 are electrically connected. However, the first internal leads 10 mounted on the active surface 46 of the chip can be electrically connected to the electrode pads by metal bumps.

【００３０】図６は、本発明の他の実施例による半導体
チップパッケージの断面図である。半導体チップパッケ
ージ２１０の第１内部リード１０は、半導体チップ４０
の活性面に取付けられて、チップの電極パッド４８に電
気的に連結される。リードと電極パッドとの電気的連結
は、金属バンプ７０により行われる。金属バンプ７０
は、半導体チップの電極パッド上に形成される。金属バ
ンプは、金や銅又は錫−鉛合金よりなる。金属バンプ７
０が形成された電極パッド４８上に第１内部リード１０
を整列させ、熱と圧力を加えながら、リードとバンプと
を接合させる。FIG. 6 is a sectional view of a semiconductor chip package according to another embodiment of the present invention. The first internal lead 10 of the semiconductor chip package 210 is
And is electrically connected to the electrode pads 48 of the chip. Electrical connection between the lead and the electrode pad is made by a metal bump 70. Metal bump 70
Are formed on the electrode pads of the semiconductor chip. The metal bump is made of gold, copper or a tin-lead alloy. Metal bump 7
0 on the electrode pad 48 on which the first internal lead 10 is formed.
Are aligned, and the leads and bumps are joined while applying heat and pressure.

【００３１】金属バンプを用いて第１内部リード１０と
中央電極パッド４８とを電気的に連結させる場合、整列
が正確になされるように特に注意すべきである。そし
て、図６には図示しないが、第１内部リード１０と半導
体チップ４０間の接続力を高めるため、接着剤を使用す
ることも可能である。図７は、本発明の一実施例による
半導体チップパッケージの斜視図である。半導体チップ
パッケージ３００は、パッケージ胴体６０の４辺から突
出する外部リード１４を備えるカード型パッケージであ
る。外部リード１４は、例えば、鴎の翼形状やＪ字形状
で折曲され、これにより、パッケージ３００が図示しな
い外部回路基板に面実装される。カード型パッケージ
は、多くの入出力ピン数を要求する素子に適合し、面実
装方式を採択するため、ピン挿入方式より実装密度が高
い。When the first internal lead 10 and the center electrode pad 48 are electrically connected to each other by using the metal bumps, special care must be taken to ensure the alignment. Although not shown in FIG. 6, it is also possible to use an adhesive in order to increase the connection force between the first internal lead 10 and the semiconductor chip 40. FIG. 7 is a perspective view of a semiconductor chip package according to an embodiment of the present invention. The semiconductor chip package 300 is a card-type package including external leads 14 protruding from four sides of the package body 60. The external lead 14 is bent in, for example, a seagull wing shape or a J-shape, whereby the package 300 is surface-mounted on an external circuit board (not shown). The card-type package is suitable for elements requiring a large number of input / output pins, and adopts a surface mounting method.

【００３２】かかるカード型パッケージは、図１及び図
２に示すように、外部リード１４が半導体チップ４０の
長辺４２に沿って配設される第１外部リード１４ａと、
半導体チップ４０の短辺４４に沿って配設される第２外
部リード１４ｂとを備えることにより可能となる。図８
は、本発明の他の実施例による半導体チップパッケージ
の分解平面図である。図８の半導体チップパッケージ４
００は、図２の実施例と同様に、半導体チップ１４０の
活性面１４６上に載置され、中央電極パッド１４８に電
気的に連結されるＬＯＣ構造の第１内部リード１１２
と、半導体チップ１４０の短辺１４４から離れて配設さ
れ、周辺電極パッド１４９に電気的に連結される標準型
第２内部リード１１０とが複合された構造を有する。第
１内部リード１１２は、パッケージの最適垂直構造を達
成するため、屈曲部を有し、接着剤１３２によりチップ
活性面１４６に取付けられる。接着剤１３２は、周辺電
極パッド１４９と２００mil 以上の距離を維持しなけれ
ばならない。電源供給用リード１２６は、２つに分岐さ
れており、全て第２内部リードとして配列されているも
のが図示されているが、第１内部リードに配列すること
も可能である。As shown in FIGS. 1 and 2, the card type package includes a first external lead 14a in which the external leads 14 are disposed along the long side 42 of the semiconductor chip 40;
This can be achieved by providing the second external leads 14b disposed along the short side 44 of the semiconductor chip 40. FIG.
FIG. 7 is an exploded plan view of a semiconductor chip package according to another embodiment of the present invention. The semiconductor chip package 4 of FIG.
2, the first internal lead 112 having a LOC structure is mounted on the active surface 146 of the semiconductor chip 140 and electrically connected to the center electrode pad 148, similarly to the embodiment of FIG.
And the standard second internal lead 110 which is disposed apart from the short side 144 of the semiconductor chip 140 and is electrically connected to the peripheral electrode pad 149. The first internal lead 112 has a bend and is attached to the chip active surface 146 by an adhesive 132 to achieve an optimal vertical configuration of the package. The adhesive 132 must maintain a distance of at least 200 mils from the peripheral electrode pad 149. Although the power supply lead 126 is divided into two and is shown as being all arranged as the second internal lead, it may be arranged in the first internal lead.

【００３３】タイバー１８０は、モールディング樹脂に
より封止されてパッケージ胴体の内部に包含されるが、
リードフレームストリップのサイドレールと連結されて
おり、単位リードフレームが最終的に個別化されるまで
個別素子をストリップ形態で維持する。第１内部リード
１１２及び第２内部リード１１０は、各々ボンディング
ワイヤにより電極パッド１４８及び１４９に連結されて
いる。しかし、上述のように、ＬＯＣ構造を有する第１
内部リード１１２は、図示しない金属バンプにより中央
電極パッド１４８に連結することも可能である。The tie bar 180 is sealed in the molding resin and contained in the package body.
It is connected to the side rails of the lead frame strip and maintains the individual elements in strip form until the unit lead frame is finally singulated. The first internal lead 112 and the second internal lead 110 are connected to the electrode pads 148 and 149 by bonding wires, respectively. However, as described above, the first having the LOC structure
The internal lead 112 can be connected to the center electrode pad 148 by a metal bump (not shown).

【００３４】第１内部リード１１２と一体に連結されて
いる第１外部リード１１４ａ及び第２内部リード１１０
と一体に連結されている第２外部リード１１４ｂは、全
て長辺に沿って配設されている。これにより、パッケー
ジ４００は、図９に示すように、外部リード１１４がパ
ッケージの２辺から突出するデュアル型パッケージを実
現することができる。外部リード１１４は、図９に示す
ように、パッケージ４００を外部回路基板に面実装する
ために、鴎の翼形状やＪ字形状で折曲するか、またはピ
ン挿入方式を適用することかできるように外部リード１
１４を折曲することが可能である。The first external lead 114a and the second internal lead 110 which are integrally connected to the first internal lead 112
The second external leads 114b that are integrally connected to the first side are all disposed along the long side. Thus, the package 400 can realize a dual package in which the external leads 114 protrude from two sides of the package, as shown in FIG. As shown in FIG. 9, the external lead 114 can be bent in a seagull wing shape or a J-shape, or a pin insertion method can be used for surface mounting the package 400 on an external circuit board. External lead 1
14 can be bent.

【００３５】[0035]

【発明の効果】以上説明したように、本発明による半導
体チップパッケージは、ＬＯＣ構造のリードと標準型リ
ードが複合されているので、チップ縮小技術等によって
半導体チップの集積度が高まっても半導体チップを効果
的に実装することができる。また、半導体チップは、中
央電極パッドと周辺電極パッドが複合された構造を有す
るので、中央電極パッド型の長所とＬＯＣ構造の長所を
全て生かすことができる。As described above, in the semiconductor chip package according to the present invention, since the LOC structure lead and the standard type lead are combined, even if the degree of integration of the semiconductor chip is increased by chip reduction technology or the like, the semiconductor chip is not damaged. Can be implemented effectively. In addition, since the semiconductor chip has a structure in which the central electrode pad and the peripheral electrode pad are combined, all the advantages of the central electrode pad type and the advantages of the LOC structure can be utilized.

【図面の詳細な説明】[Detailed description of drawings]

【図１】本発明による半導体チップパッケージに適合す
るリードフレームストリップの部分平面図である。FIG. 1 is a partial plan view of a lead frame strip adapted to a semiconductor chip package according to the present invention.

【図２】本発明の一実施例による半導体チップパッケー
ジの分解平面図である。FIG. 2 is an exploded plan view of a semiconductor chip package according to an embodiment of the present invention.

【図３】本発明の一実施例による半導体チップパッケー
ジの部分分解平面図である。FIG. 3 is a partially exploded plan view of a semiconductor chip package according to an embodiment of the present invention.

【図４】図２のIV−IV線断面図である。FIG. 4 is a sectional view taken along line IV-IV of FIG. 2;

【図５】図２のＶ−Ｖ線断面図である。FIG. 5 is a sectional view taken along line VV of FIG. 2;

【図６】本発明の他の実施例による半導体チップパッケ
ージの断面図である。FIG. 6 is a sectional view of a semiconductor chip package according to another embodiment of the present invention.

【図７】本発明の一実施例による半導体チップパッケー
ジの斜視図である。FIG. 7 is a perspective view of a semiconductor chip package according to an embodiment of the present invention.

【図８】本発明のさらに他の実施例による半導体チップ
パッケージの部分分解平面図である。FIG. 8 is a partially exploded plan view of a semiconductor chip package according to another embodiment of the present invention.

【図９】本発明のさらに他の実施例による半導体チップ
パッケージの斜視図である。FIG. 9 is a perspective view of a semiconductor chip package according to another embodiment of the present invention;

【符号の説明】[Explanation of symbols]

１０、１２ 内部リード １４ａ、１４ｂ 外部リード １５ コーナーリード １８ タイバー ２０ ダミーリード ２４ サイドレール ２６ 電源供給用リード ２８ ダムバー ３０ 屈曲部 ３２ 接着剤 ４２ 長辺 ４４ 短辺 ４６ 活性面 ４８、４９ 電極パッド ５２ ボンディングワイヤ ５６ バスバー 10, 12 Internal lead 14a, 14b External lead 15 Corner lead 18 Tie bar 20 Dummy lead 24 Side rail 26 Power supply lead 28 Dam bar 30 Bend 32 Adhesive 42 Long side 44 Short side 46 Active surface 48, 49 Electrode pad 52 Bonding Wire 56 busbar

───────────────────────────────────────────────────── フロントページの続き (72)発明者 任 旻彬 大韓民国忠清南道天安市多價洞384−29番 地 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Min-Akira

Claims (21)

【特許請求の範囲】[Claims] 【請求項１】 集積回路素子が設けられている活性面と
長辺及び短辺を有し、前記長辺に平行に前記活性面の中
央部に配設される複数の中央電極パッド、及び前記短辺
に平行に前記活性面の周辺部に配設される複数の周辺電
極パッドを含む半導体チップと、 内部リード、及び前記内部リードと一体に形成され、前
記半導体チップを外部に電気的に連結するための外部リ
ードを有し、前記内部リードは、前記長辺に沿って配設
され、前記活性面に取付けられる複数の第１内部リー
ド、及び前記短辺に沿って配設され、前記半導体チップ
の端部から離れている複数の第２内部リードを有し、前
記外部リードは、前記複数の第１内部リードと一体に形
成され、前記長辺に沿って配設される複数の第１外部リ
ード、及び前記複数の第２内部リードと一体に形成さ
れ、前記短辺に沿って配列される複数の第２外部リード
を有するリードフレームと、 前記複数の第１及び第２内部リードと、前記半導体チッ
プの中央電極パッド及び周辺電極パッドとを電気的に連
結する電気的連結手段と、 前記半導体チップ、内部リード及び電気的連結手段を封
止するパッケージ胴体と、 を備えることを特徴とする半導体チップパッケージ。An active surface on which an integrated circuit element is provided, a long side and a short side, and a plurality of central electrode pads arranged at a central portion of the active surface in parallel with the long side; A semiconductor chip including a plurality of peripheral electrode pads disposed on a periphery of the active surface in parallel with the short side; an internal lead; and an integrated lead formed with the internal chip, and electrically connecting the semiconductor chip to the outside. An internal lead disposed along the long side, a plurality of first internal leads attached to the active surface, and disposed along the short side, and the semiconductor A plurality of second internal leads separated from an end of the chip, wherein the external leads are formed integrally with the plurality of first internal leads and are arranged along the long side; One external lead and the plurality of second internal leads And a lead frame having a plurality of second external leads arranged along the short side, the plurality of first and second internal leads, and a center electrode pad and a peripheral electrode pad of the semiconductor chip. A semiconductor chip package comprising: electrical connection means for electrically connecting; and a package body for sealing the semiconductor chip, the internal leads, and the electrical connection means. 【請求項２】 前記リードフレームは、コーナー内部リ
ードとサイドレールとを連結するタイバーを有すること
を特徴とする請求項１に記載の半導体チップパッケー
ジ。2. The semiconductor chip package according to claim 1, wherein the lead frame has a tie bar connecting the inner corner lead and the side rail. 【請求項３】 前記複数の第１内部リードは、半導体チ
ップ及びリードの位置を認識することができる整列キー
を備えることを特徴とする請求項１に記載の半導体チッ
プパッケージ。3. The semiconductor chip package according to claim 1, wherein the plurality of first internal leads include an alignment key for recognizing a position of the semiconductor chip and the lead. 【請求項４】 前記電気的連結手段は、ボンディングワ
イヤであることを特徴とする請求項１に記載の半導体チ
ップパッケージ。4. The semiconductor chip package according to claim 1, wherein said electrical connection means is a bonding wire. 【請求項５】 前記電気的連結手段は、前記複数の第１
内部リードと前記中央電極パッドとを連結する金属バン
プと、前記複数の第２内部リードと前記周辺電極パッド
を連結するボンディングワイヤとを含むことを特徴とす
る請求項１に記載の半導体チップパッケージ。5. The electric connection means according to claim 5, wherein
2. The semiconductor chip package according to claim 1, further comprising: a metal bump connecting the internal lead to the central electrode pad; and a bonding wire connecting the plurality of second internal leads to the peripheral electrode pad. 【請求項６】 前記中央電極パッドは、２列に配列され
ていることを特徴とする請求項１に記載の半導体チップ
パッケージ。6. The semiconductor chip package according to claim 1, wherein the center electrode pads are arranged in two rows. 【請求項７】 前記複数の第１内部リードは、屈曲構造
を有することを特徴とする請求項１に記載の半導体チッ
プパッケージ。7. The semiconductor chip package according to claim 1, wherein the plurality of first internal leads have a bent structure. 【請求項８】 前記内部リードは、前記半導体チップに
電源を供給するための電源供給用内部リードを備えてお
り、前記電源供給用内部リードは、２つに分岐されるこ
とを特徴とする請求項１に記載の半導体チップパッケー
ジ。8. The internal lead for power supply for supplying power to the semiconductor chip, wherein the internal lead for power supply is branched into two. Item 2. The semiconductor chip package according to item 1. 【請求項９】 前記複数の第１内部リードは、電気絶縁
性接着テープにより前記活性面に取付けられることを特
徴とする請求項１に記載の半導体チップパッケージ。9. The semiconductor chip package according to claim 1, wherein the plurality of first internal leads are attached to the active surface by an electrically insulating adhesive tape. 【請求項１０】 前記接着テープは、ポリイミド系の両
面接着テープであることを特徴とする請求項９に記載の
半導体チップパッケージ。10. The semiconductor chip package according to claim 9, wherein the adhesive tape is a polyimide-based double-sided adhesive tape. 【請求項１１】 前記複数の第１内部リードは、屈曲構
造を有し、前記屈曲のサイズは、前記接着テープの厚さ
及び前記半導体チップの厚さにより決定され、前記半導
体チップが前記パッケージ胴体の中央に位置するように
調節されることを特徴とする請求項９に記載の半導体チ
ップパッケージ。11. The plurality of first internal leads have a bent structure, and the size of the bend is determined by a thickness of the adhesive tape and a thickness of the semiconductor chip, and the semiconductor chip is mounted on the package body. 10. The semiconductor chip package according to claim 9, wherein the semiconductor chip package is adjusted to be positioned at a center of the semiconductor chip package. 【請求項１２】 前記周辺電極は、前記接着テープから
２０mil 以上離れていることを特徴とする請求項９に記
載の半導体チップパッケージ。12. The semiconductor chip package according to claim 9, wherein the peripheral electrode is separated from the adhesive tape by 20 mil or more. 【請求項１３】 前記複数の第１内部リードの中で、同
一の電源電圧が供給されるリードは、バスバーにより１
つの通路で連結されていることを特徴とする請求項１に
記載の半導体チップパッケージ。13. A lead to which the same power supply voltage is supplied among the plurality of first internal leads is connected to one of the first internal leads by a bus bar.
2. The semiconductor chip package according to claim 1, wherein the semiconductor chip package is connected by two passages. 【請求項１４】 前記活性面には、レーザーによる切断
が可能な金属線が露出する部分を有するフューズボック
スが形成されており、前記複数の第１内部リードは、前
記フューズボックスを回避して前記活性面に取付けられ
ることを特徴とする請求項１に記載の半導体チップパッ
ケージ。14. A fuse box having a portion on which a metal wire that can be cut by a laser is exposed is formed on the active surface, and the plurality of first internal leads avoid the fuse box, and The semiconductor chip package according to claim 1, wherein the semiconductor chip package is attached to an active surface. 【請求項１５】 集積回路素子が設けられている活性面
と長辺及び短辺を有し、前記長辺に平行に前記活性面の
中央部に配設される複数の中央電極パッド、及び前記短
辺に平行に前記活性面の周辺部に配設される複数の周辺
電極パッドを含む半導体チップと、 内部リードと外部リードとを有し、前記内部リードは、
前記長辺に沿って配設され、前記活性面に取付けられる
複数の第１内部リード、及び前記短辺に沿って配設さ
れ、前記半導体チップの端部から離れている複数の第２
内部リードを有し、前記外部リードは、前記複数の第１
内部リードと一体に形成され、前記長辺に沿って配設さ
れる複数の第１外部リード、及び前記複数の第２内部リ
ードと一体に形成され、前記長辺に沿って配列される複
数の第２外部リードを有するリードフレームと、 前記複数の第１及び第２内部リードと、前記半導体チッ
プの中央電極パッド及び周辺電極パッドとを電気的に連
結する電気的連結手段と、 前記半導体チップ、内部リード及び電気的連結手段を封
止するパッケージ胴体と、 を備えることを特徴とする半導体チップパッケージ。15. A plurality of central electrode pads having an active surface on which an integrated circuit element is provided, a long side and a short side, and arranged at a central portion of the active surface in parallel with the long side. A semiconductor chip including a plurality of peripheral electrode pads arranged in a peripheral portion of the active surface in parallel with the short side, and an internal lead and an external lead;
A plurality of first internal leads arranged along the long side and attached to the active surface; and a plurality of second internal leads arranged along the short side and separated from an end of the semiconductor chip.
An internal lead, wherein the external lead is connected to the plurality of first leads.
A plurality of first external leads formed integrally with the internal lead and disposed along the long side, and a plurality of first external leads formed integrally with the plurality of second internal leads and arranged along the long side A lead frame having a second external lead; electrical connection means for electrically connecting the plurality of first and second internal leads; a central electrode pad and a peripheral electrode pad of the semiconductor chip; A semiconductor chip package, comprising: a package body that seals internal leads and electrical connection means. 【請求項１６】 前記リードフレームは、前記パッケー
ジ胴体に封止され、サイドレールに連結されるタイバー
を備えることを特徴とする請求項１５に記載の半導体チ
ップパッケージ。16. The semiconductor chip package according to claim 15, wherein the lead frame includes a tie bar sealed to the package body and connected to a side rail. 【請求項１７】 前記複数の第１内部リードは、屈曲構
造を有することを特徴とする請求項１５に記載の半導体
チップパッケージ。17. The semiconductor chip package according to claim 15, wherein the plurality of first internal leads have a bent structure. 【請求項１８】 前記複数の第１内部リードは、電気絶
縁性接着テープにより前記活性面に取付けられることを
特徴とする請求項１５に記載の半導体チップパッケー
ジ。18. The semiconductor chip package according to claim 15, wherein the plurality of first internal leads are attached to the active surface by an electrically insulating adhesive tape. 【請求項１９】 前記複数の第１内部リードは、屈曲構
造を有し、前記屈曲のサイズは、前記接着テープの厚さ
及び前記半導体チップの厚さにより決定され、前記半導
体チップが前記パッケージ胴体の中央に位置するように
調節されることを特徴とする請求項１８に記載の半導体
チップパッケージ。19. The plurality of first internal leads have a bent structure, and the size of the bend is determined by the thickness of the adhesive tape and the thickness of the semiconductor chip, and the semiconductor chip is mounted on the package body. 19. The semiconductor chip package according to claim 18, wherein the semiconductor chip package is adjusted to be positioned at a center of the semiconductor chip. 【請求項２０】 前記複数の第１内部リードの中で、同
一の電源電圧が供給されるリードは、バスバーにより１
つの通路で連結されていることを特徴とする請求項１５
に記載の半導体チップパッケージ。20. One of the plurality of first internal leads to which the same power supply voltage is supplied is connected to one of the first internal leads by a bus bar.
16. The connection according to claim 15, wherein the connection is made by three passages.
7. A semiconductor chip package according to claim 1. 【請求項２１】 前記活性面には、レーザーによる切断
が可能な金属線が露出する部分を有するフューズボック
スが形成されており、前記複数の第１内部リードは、前
記フューズボックスを回避して前記活性面に取付けられ
ることを特徴とする請求項１５に記載の半導体チップパ
ッケージ。21. A fuse box having a portion on which a metal wire that can be cut by a laser is exposed is formed on the active surface, and the plurality of first internal leads avoid the fuse box, and The semiconductor chip package according to claim 15, wherein the semiconductor chip package is attached to an active surface.
JP9314876A 1997-02-28 1997-11-17 Semiconductor chip package Expired - Fee Related JP2981194B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR19970006505 1997-02-28
KR1997P6505 1997-08-07
KR1019970037789A KR100227120B1 (en) 1997-02-28 1997-08-07 Semiconductor chip package having combinational structure of lead-on-chip leads and standard normal leads
KR1997P37789 1997-08-07

Publications (2)

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JPH10242373A true JPH10242373A (en) 1998-09-11
JP2981194B2 JP2981194B2 (en) 1999-11-22

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KR (1) KR100227120B1 (en)
CN (1) CN1114948C (en)
DE (1) DE19749539B4 (en)
FR (1) FR2760289B1 (en)
TW (1) TW354856B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
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US6518652B2 (en) 2000-09-04 2003-02-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor package
US7138725B2 (en) 2003-10-01 2006-11-21 Renesas Technology Corp. Semiconductor device
JP2017066233A (en) * 2015-09-29 2017-04-06 株式会社巴川製紙所 Adhesive tape for electronic component
CN110931420A (en) * 2019-11-19 2020-03-27 苏州日月新半导体有限公司 Heating block unit and heating device

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KR100401536B1 (en) * 1997-12-31 2004-01-24 주식회사 하이닉스반도체 Method for altering center pad type semiconductor chip to peripheral pad type semiconductor chip
DE10158770B4 (en) 2001-11-29 2006-08-03 Infineon Technologies Ag Lead frame and component with a lead frame
KR100525091B1 (en) * 2001-12-28 2005-11-02 주식회사 하이닉스반도체 semiconductor package
KR100654338B1 (en) * 2003-10-04 2006-12-07 삼성전자주식회사 Tape circuit substrate and semiconductor chip package using thereof

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JPH06105721B2 (en) * 1985-03-25 1994-12-21 日立超エル・エス・アイエンジニアリング株式会社 Semiconductor device
JP2748940B2 (en) * 1989-06-05 1998-05-13 株式会社日立製作所 Resin-sealed semiconductor device
JPH01276656A (en) * 1988-04-27 1989-11-07 Mitsubishi Electric Corp Resin sealed semiconductor
JPH02132848A (en) * 1988-11-14 1990-05-22 Nec Corp Semiconductor device
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518652B2 (en) 2000-09-04 2003-02-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor package
US7138725B2 (en) 2003-10-01 2006-11-21 Renesas Technology Corp. Semiconductor device
JP2017066233A (en) * 2015-09-29 2017-04-06 株式会社巴川製紙所 Adhesive tape for electronic component
CN110931420A (en) * 2019-11-19 2020-03-27 苏州日月新半导体有限公司 Heating block unit and heating device

Also Published As

Publication number Publication date
CN1114948C (en) 2003-07-16
CN1192048A (en) 1998-09-02
DE19749539B4 (en) 2006-04-13
KR19980069880A (en) 1998-10-26
TW354856B (en) 1999-03-21
DE19749539A1 (en) 1998-09-10
FR2760289A1 (en) 1998-09-04
JP2981194B2 (en) 1999-11-22
KR100227120B1 (en) 1999-10-15
FR2760289B1 (en) 2002-08-30

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