JPH02132848A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02132848A JPH02132848A JP28585688A JP28585688A JPH02132848A JP H02132848 A JPH02132848 A JP H02132848A JP 28585688 A JP28585688 A JP 28585688A JP 28585688 A JP28585688 A JP 28585688A JP H02132848 A JPH02132848 A JP H02132848A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- parts
- package
- resin package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 28
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 238000007789 sealing Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 150000003376 silicon Chemical class 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＤＩＰ （デュアルインラインパッケージ）
型の半導体装置に関し、特に半導体チップと接続される
リードの形状に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a DIP (dual in-line package).
The present invention relates to a type of semiconductor device, and particularly relates to the shape of a lead connected to a semiconductor chip.
？ 〔従来の技術）
従来のこの種の半導体装置は第４図および第５図に示す
ように構成されている．
・ 第４図は従来のＤＴＰ型集積回路をパッケージを破
断して示す平面図、第５図は第４図中Ｖ−Ｖ線断面図で
ある。これらの図において、１はシリコンチップで、こ
のシリコンチップ１は上面にボンディングパッド１ａが
複数並設されており、樹脂封止後にリードフレーム本体
（図示せず）から分断されるアイランド２上に接合され
ている。また、前記ボンディングパッド１ａは、シリコ
ンチップ１の西側部と対応するようにシリコンチップｌ
の上面における側部側に側端縁と平行になるように配列
されている。３はリード、４は封止用モールド樹脂で、
この封止用モールド樹脂４によってパッケージが形成さ
れている．また、前記リード３は前記シリコンチップ１
のボンディングパッド１ａにボンディングワイヤ５を介
して接続される内部リード部３ａと、パッケージの側部
から突出される外部リード部３ｂとから構成され、外部
リード部３ｂを前記パッケージの側部から突出させてバ
ンケージの二側部に複数並設されている。? [Prior Art] A conventional semiconductor device of this type is constructed as shown in FIGS. 4 and 5. - FIG. 4 is a plan view showing a conventional DTP integrated circuit with the package cut away, and FIG. 5 is a sectional view taken along the line V-V in FIG. 4. In these figures, 1 is a silicon chip, and this silicon chip 1 has a plurality of bonding pads 1a arranged in parallel on its upper surface, and is bonded to an island 2 that is separated from a lead frame body (not shown) after resin sealing. has been done. Further, the bonding pad 1a is arranged on the silicon chip 1 so as to correspond to the west side of the silicon chip 1.
They are arranged parallel to the side edges on the upper surface of the lateral side. 3 is a lead, 4 is a mold resin for sealing,
A package is formed by this sealing mold resin 4. Further, the lead 3 is connected to the silicon chip 1.
The package is composed of an internal lead part 3a connected to the bonding pad 1a via a bonding wire 5, and an external lead part 3b protruding from the side of the package. A plurality of them are arranged in parallel on two sides of the bunkage.
このように構成された従来のＤＩＰ型集積回路を組み立
てるには、先ず、リード３を一体的に支持するリードフ
レーム（図示せず）のアイランド２上にシリコンチップ
１を接合させ、このシリコンチップ１のボンディングバ
ソド１ａとリード３における内部リード部３ａの先端部
とをボンディングワイヤ５を介して接続する。次いで、
シリコンチップ１をリードフレームごとモールド金型（
図示せず）内に型締めし、モールド樹脂４によってパ・
７ケージを形成する。モールド樹脂４が硬化した後、リ
ードフレームをモールド金型から離型させ、各リード３
．３・・・およびアイランド２をリードフレーム本体か
ら分断させる。しかる後、外部リード３ｂを所定形状に
折曲げて組み立てが終了する。To assemble the conventional DIP integrated circuit configured in this way, first, the silicon chip 1 is bonded onto the island 2 of a lead frame (not shown) that integrally supports the leads 3. The bonding bath 1a and the tip of the internal lead portion 3a of the lead 3 are connected via the bonding wire 5. Then,
Silicon chip 1 is molded together with the lead frame (
(not shown), and the mold is sealed with mold resin 4.
Form 7 cages. After the mold resin 4 has hardened, the lead frame is released from the mold, and each lead 3 is
．． 3... and the island 2 is separated from the lead frame body. Thereafter, the external lead 3b is bent into a predetermined shape, and the assembly is completed.
しかるに、このように構成された従来の集積回路におい
ては、モールド樹脂４でパッケージを形成することによ
ってモールド樹脂４とリード３とが強固に接着されるよ
うに構成されているが、リード３とモールド樹脂４とが
一体に形成されているわけではないために、リード３と
モールド樹脂４との界面を伝ってパッケージ内に湿気が
侵入しシリコンチフプ１が腐食される場合がある。特に
、従来のＤＩＰ型集積回路のようにリード３がパッケー
ジの二側部に並設された集積回路においては、パッケー
ジの幅方向側部側に、換言すればパッケージにおける外
部リード部３ｂが突出される側部側に配設されたボンデ
ィングパッド１ａと接続されるリード３は、第４図に示
すように、モールド樹脂４と接着されて封止される部分
が他のり一ド３に較べて短くなる。この封止部分の短い
リ一ド３を伝って湿気が容易に侵入され易く、耐湿性が
低かった。このような不具合を解消するためにはパッケ
ージの幅方向の寸法を大きく設定すればよいが、このよ
うにすると集積回路自体が大型化されてしまう。However, in the conventional integrated circuit configured in this way, the mold resin 4 and the leads 3 are firmly bonded by forming the package with the mold resin 4, but the lead 3 and the mold Since the resin 4 and the lead 3 are not integrally formed, moisture may enter the package through the interface between the leads 3 and the mold resin 4, and the silicon chip 1 may be corroded. In particular, in an integrated circuit such as a conventional DIP type integrated circuit in which the leads 3 are arranged in parallel on two sides of the package, the external lead portions 3b of the package protrude from the sides in the width direction of the package. As shown in FIG. 4, the lead 3 connected to the bonding pad 1a disposed on the side of the board is shorter than the other leads 3 in the part where it is bonded and sealed with the mold resin 4. Become. Moisture easily penetrated through the short lead 3 of this sealed portion, resulting in low moisture resistance. In order to solve this problem, the size of the package in the width direction may be increased, but this increases the size of the integrated circuit itself.
本発明に係る半導体装置は、半導体チップにおける外部
リード部側のポンディングパッドを半導体チップの主面
における幅方向の中央部付近に配設し、このボンディン
グパッドと接続されるリードの内部リード部を樹脂パッ
ケージ内に封止される部位で折曲げ、半導体チップの上
方に延在させたものである。In the semiconductor device according to the present invention, the bonding pad on the external lead side of the semiconductor chip is arranged near the center in the width direction on the main surface of the semiconductor chip, and the internal lead part of the lead connected to this bonding pad is It is bent at the portion sealed in the resin package and extended above the semiconductor chip.
半導体チップの主面における幅方向の中央部付近に配設
されたボンディングパッドと接続されるリードにおいて
は、樹脂パッケージによって封止される部分が長くなる
。In a lead connected to a bonding pad disposed near the widthwise center of the main surface of the semiconductor chip, the portion sealed by the resin package becomes long.
以下、本発明の一実施例を第１図ないし第３図によって
詳細に説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.
第１図は本発明に係る集積回路をパフケージを破断して
示す平面図、第２図は本発明に係る集積回路を示す側面
図、第３図は第２図中ｍ−ｍ線断面図である。これらの
図において前記第４図および第５図で説明したものと同
一もしくは同等部材については同一符号を付し、ここに
おいて詳細な説明は省略する。これらの図において、１
１はシリコンチップで、このシリコンチップ１１の上面
におけるパッケージの長手方向側部側側には第一のボン
ディングパフド１２がバンケージの幅方向に沿って複数
並設されており、かつシリコンチップ１１の上面におけ
るパッケージの幅方向中央部付近には第二のボンディン
グパンド１３がバンケージの長手力向に沿って複数並設
されている。１４は前記第二のボンディングパッド１３
に接続されるリードで、このリード１４は第二のボンデ
ィングパッド１３にボンディングワイヤ５を介して接続
される内部リード部１４ａと、パッケージの幅方向側部
から突出される外部リード部１４ｂとから構成されてい
る。また、このリード１４の内部リード部１４ａは、第
１図および第３図に示すように、樹脂パッケージ内に封
止される部位で上方へ折曲げられ、ワイヤボンディング
される先端部がシリコンチップｌ１の上方に延在される
ように形成されている。FIG. 1 is a plan view showing an integrated circuit according to the present invention with the puff cage cut away, FIG. 2 is a side view showing the integrated circuit according to the present invention, and FIG. 3 is a sectional view taken along line m-m in FIG. be. In these figures, the same or equivalent members as those explained in FIGS. 4 and 5 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In these figures, 1
Reference numeral 1 denotes a silicon chip, and a plurality of first bonding puffs 12 are arranged in parallel along the width direction of the buncage on the longitudinal side of the package on the upper surface of the silicon chip 11. A plurality of second bonding pads 13 are arranged in parallel along the longitudinal direction of the bankage near the center in the width direction of the package on the upper surface. 14 is the second bonding pad 13
This lead 14 is composed of an internal lead part 14a connected to the second bonding pad 13 via the bonding wire 5, and an external lead part 14b protruding from the widthwise side of the package. has been done. Further, as shown in FIGS. 1 and 3, the internal lead portion 14a of this lead 14 is bent upward at a portion to be sealed in the resin package, and the tip portion to be wire bonded is attached to the silicon chip l1. It is formed to extend above.
このように構成されたＤＩＰ型集積回路を組み立てるに
は、先ず、リードフレーム（図示せず）のアイランド２
上にシリコンチツプ１１を接合させ、このシリコンチッ
プ１１の第一のボンデイングパツド１２とリ一ド３にお
ける内部リード部３ａの先端部とをワイヤボンデイング
すると共に、第二のポンディングバッド１３とリ一ド１
４の内部リード部１４ａの先端部とをワイヤボンデイン
グする。次いで、シリコンチップ１１をリードフレーム
ごとモールド金型（図示せず）内に型締めし、モールド
樹脂４によってパッケージを形成する。この際、リード
１４の内部リード部１４ａは全面に渡りモールド樹脂４
により覆われることになる。モールド樹脂４が硬化した
後、リードフレームをモールド金型から離型させ、各リ
ード３．３・・・、１４．１４・・・およびアイランド
２をリードフレームから分断させる。しかる後、外部リ
ード３ｂ． １４ｂを所定形状に折曲げて組み立てが終
了する。To assemble the DIP integrated circuit configured in this way, first, island 2 of the lead frame (not shown) is assembled.
A silicon chip 11 is bonded onto the silicon chip 11, and the first bonding pad 12 of this silicon chip 11 and the tip of the internal lead part 3a of the lead 3 are wire bonded, and the second bonding pad 13 and the lead are bonded together. 1 card 1
Wire bonding is performed to the tip of the internal lead portion 14a of No. 4. Next, the silicon chip 11 is clamped together with the lead frame in a mold (not shown), and a package is formed using the mold resin 4. At this time, the internal lead portion 14a of the lead 14 is molded with mold resin 4 over the entire surface.
It will be covered by After the mold resin 4 has hardened, the lead frame is released from the mold, and the leads 3, 3, 14, 14, and the island 2 are separated from the lead frame. After that, external lead 3b. The assembly is completed by bending 14b into a predetermined shape.
したがって、リード１４は内部リード部１４ａがシリコ
ンチップ１１の上方に延在するように形成されており、
この内部リード部１４ａが全面に渡りモールド樹脂４に
よって封止されることになるから、封止部分の長さを長
く取ることができる。Therefore, the leads 14 are formed such that the internal lead portions 14a extend above the silicon chip 11,
Since this internal lead portion 14a is entirely sealed with mold resin 4, the length of the sealed portion can be increased.
以上説明したように本発明によれば、半導体チップにお
ける外部リード部側のボンディングパッドを半導体チッ
プの主面における幅方向の中央部付近に配設し、このボ
ンディングパッドと接続されるリードの内部リード部を
樹脂パッケージ内に封止される部位で折曲げ、半導体チ
ップの上方に延在させたため、半導体チップの主面にお
ける幅方向の中央部付近に配設されたボンディングパッ
ドと接続されるリードにおいては、樹脂パッケージによ
って封止される部分が長くなる。したがって、封止部分
が短いために樹脂パッケージとの界面を伝って湿気が侵
入され易いリードがなくなるから、耐湿性を向上させる
ことができ信頼性の高い半導体装置を得ることができる
。As explained above, according to the present invention, the bonding pad on the external lead portion side of the semiconductor chip is arranged near the center in the width direction on the main surface of the semiconductor chip, and the internal lead of the lead connected to this bonding pad is Since the lead is bent at the part to be sealed in the resin package and extended above the semiconductor chip, the lead connected to the bonding pad located near the widthwise center of the main surface of the semiconductor chip is bent. In this case, the part sealed by the resin package becomes longer. Therefore, since the sealing portion is short and there is no lead through which moisture can easily enter through the interface with the resin package, moisture resistance can be improved and a highly reliable semiconductor device can be obtained.
第１図は本発明に係る集積回路をパッケージを破断して
示す平面図、第２図は本発明に係る集積回路を示す側面
図、第３図は第２図中ｍ−ｍ線断面図、第４図は従来の
ＤＩＰ型集積回路をノ々ソケージを破断して示す平面図
、第５図は第４図中Ｖ−ｖ線断面図である。
４・・・・モールド樹脂、５・・・・ボンデイングワイ
ヤ、１１・・・・シリコンチップ、１２・・・・第一の
ボンディングパッド、１３・・・・第二のポンデイング
ノ寸・ノド、ｌ４・・・・リード。
第４図FIG. 1 is a plan view showing an integrated circuit according to the present invention with the package cut away, FIG. 2 is a side view showing the integrated circuit according to the present invention, and FIG. 3 is a sectional view taken along the line m-m in FIG. FIG. 4 is a plan view showing a conventional DIP type integrated circuit with the slotted cage cut away, and FIG. 5 is a sectional view taken along the line V--V in FIG. 4...Mold resin, 5...Bonding wire, 11...Silicon chip, 12...First bonding pad, 13...Second bonding diameter/nod, l4... ...Lead. Figure 4
Claims (1)
続されたリードが外部リード部を樹脂パッケージの側部
から突出させて樹脂パッケージの二側部に複数並設され
た半導体装置において、前記半導体チップにおける前記
外部リード部側のボンディングパッドを半導体チップの
主面における幅方向の中央部付近に配設し、このボンデ
ィングパッドと接続されるリードの内部リード部を樹脂
パッケージ内に封止される部位で折曲げ、半導体チップ
の上方に延在させたことを特徴とする半導体装置。In a semiconductor device in which a plurality of leads whose internal lead parts are connected to bonding pads of a semiconductor chip are arranged in parallel on two sides of a resin package with external lead parts protruding from the side parts of the resin package, the external leads of the semiconductor chip A bonding pad on the lead part side is arranged near the center in the width direction on the main surface of the semiconductor chip, and an internal lead part of the lead connected to this bonding pad is bent at a part to be sealed in the resin package. A semiconductor device characterized by extending above a semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28585688A JPH02132848A (en) | 1988-11-14 | 1988-11-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28585688A JPH02132848A (en) | 1988-11-14 | 1988-11-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02132848A true JPH02132848A (en) | 1990-05-22 |
Family
ID=17696939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28585688A Pending JPH02132848A (en) | 1988-11-14 | 1988-11-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02132848A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2760289A1 (en) * | 1997-02-28 | 1998-09-04 | Samsung Electronics Co Ltd | SEMICONDUCTOR CHIP CASE HAVING A COMBINED STRUCTURE OF CONDUCTORS SITUATED ON THE CHIP AND NORMAL STANDARD CONDUCTORS |
| EP0987758A3 (en) * | 1991-12-27 | 2000-05-24 | Fujitsu Limited | Semiconducter device and method of producing the same |
| US6150728A (en) * | 1995-05-12 | 2000-11-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having a pad arrangement with reduced occupying area |
-
1988
- 1988-11-14 JP JP28585688A patent/JPH02132848A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0987758A3 (en) * | 1991-12-27 | 2000-05-24 | Fujitsu Limited | Semiconducter device and method of producing the same |
| US6150728A (en) * | 1995-05-12 | 2000-11-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having a pad arrangement with reduced occupying area |
| FR2760289A1 (en) * | 1997-02-28 | 1998-09-04 | Samsung Electronics Co Ltd | SEMICONDUCTOR CHIP CASE HAVING A COMBINED STRUCTURE OF CONDUCTORS SITUATED ON THE CHIP AND NORMAL STANDARD CONDUCTORS |
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