JPH01312866A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH01312866A JPH01312866A JP14395988A JP14395988A JPH01312866A JP H01312866 A JPH01312866 A JP H01312866A JP 14395988 A JP14395988 A JP 14395988A JP 14395988 A JP14395988 A JP 14395988A JP H01312866 A JPH01312866 A JP H01312866A
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- leads
- lead frame
- lead
- tip end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000008188 pellet Substances 0.000 abstract description 7
- 244000171726 Scotch broom Species 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置用リードフレームに関し、特にイン
ナーリード部の形状に特徴を有する半導体装置用リード
フレームに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame for a semiconductor device having a characteristic shape in the shape of an inner lead portion.
従来、この種の半導体装置用リードフレームは、イナー
リード部は第3図に示されているように、そのリード先
端部がペレット9の周縁からほぼ一定の距離にあるよう
に一列にそろえて設けられていた。Conventionally, in this type of lead frame for a semiconductor device, the inner leads are arranged in a line so that the lead tips are at a substantially constant distance from the periphery of the pellet 9, as shown in FIG. It was getting worse.
上述した従来の半導体装置用リードフレームは、インナ
ーリード部においてそのリード先端部が一列にそろって
いるので、一定のポンディングワイヤ長を必要とする。In the conventional lead frame for a semiconductor device described above, the lead tips are aligned in a line in the inner lead portion, so a certain length of bonding wire is required.
また、インナーリードの配列密度が低いという欠点があ
る。Another drawback is that the arrangement density of the inner leads is low.
本発明の半導体装置用リードフレームは、半導体素子を
搭載するアイランド部を有する半導体用リードフレーム
において、前記リードフレームのインナーリード先端部
と前記アイランド部との距離が長い第1のリードと短い
第2のリードとを交互に配列したことを特徴とする。A lead frame for a semiconductor device according to the present invention has a first lead having a long distance between an inner lead tip of the lead frame and the island part, and a second lead having a short distance between the inner lead tip of the lead frame and the island part. It is characterized by that the leads are arranged alternately.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の平面図である。インナーリ
ード1の先端部は、ペレットから近い第1の距離にある
第1のインナーリード先端部と、ペレットから遠い第2
の距離にある第2のインナーリード先端部から構成され
ている。そして、第1のインナーリード先端部と第2の
インナーリード先端部が交互に配列されている。FIG. 1 is a plan view of one embodiment of the present invention. The tip of the inner lead 1 is a first inner lead tip that is closer to the pellet, and a second inner lead tip that is farther from the pellet.
The tip of the second inner lead is located at a distance of . The first inner lead tip portions and the second inner lead tip portions are arranged alternately.
第2図は本発明の他の実施例の平面図である。FIG. 2 is a plan view of another embodiment of the invention.
この実施例ではイナーリードのリード先端部を2つおき
に長く配列した例で、アイランドのコーナ一部でリード
の配列密度を高め、また、つきでたリード先端において
はボンディングワイヤー長が短くできるという利点があ
る。In this example, the lead tips of every two inner leads are arranged long, which increases the arrangement density of the leads in a part of the corner of the island, and also allows the length of the bonding wire to be shortened at the protruding lead tips. There are advantages.
以上説明したように本発明は、リードフレームのインナ
ーリード部のリード先端部とベレット間の距離が近いも
のと遠いものとを交互に配列することにより、ポンディ
ングワイヤー長の減少し、インナーリードの配列密度の
向上が可能となるという効果がある。As explained above, the present invention reduces the length of the bonding wire by alternately arranging the distances between the lead tips of the inner lead portion of the lead frame and the pellets to be closer and farther apart. This has the effect of making it possible to improve the arrangement density.
第1図は本発明の一実施例の平面図、第2図は本発明の
他の実施例の平面図、第3図は従来のリードフレームの
平面図である。
1.4.7・・・・・・インナーリード、2,5゜8・
・・・・・アイランド、3,6.9・・・・・・ベレッ
ト。
代理人 弁理士 内 原 音
$ 1 回
箒 3 閉FIG. 1 is a plan view of one embodiment of the present invention, FIG. 2 is a plan view of another embodiment of the present invention, and FIG. 3 is a plan view of a conventional lead frame. 1.4.7・・・Inner lead, 2.5°8・
...Island, 3,6.9...Berrett. Agent Patent Attorney Uchihara Oto $ 1 Broom 3 Closed
Claims (1)
置用リードフレームにおいて、前記リードフレームのイ
ンナーリード先端部と前記アイランド部との距離が長い
第1のリードと短い第2のリードとを交互に配列したこ
とを特徴とする半導体装置用リードフレーム。In a lead frame for a semiconductor device having an island portion on which a semiconductor element is mounted, first leads having a long distance between the inner lead tip portion of the lead frame and the island portion and second leads having a short distance are alternately arranged. A lead frame for semiconductor devices characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14395988A JPH01312866A (en) | 1988-06-10 | 1988-06-10 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14395988A JPH01312866A (en) | 1988-06-10 | 1988-06-10 | Lead frame for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01312866A true JPH01312866A (en) | 1989-12-18 |
Family
ID=15351031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14395988A Pending JPH01312866A (en) | 1988-06-10 | 1988-06-10 | Lead frame for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01312866A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5168368A (en) * | 1991-05-09 | 1992-12-01 | International Business Machines Corporation | Lead frame-chip package with improved configuration |
US5420460A (en) * | 1993-08-05 | 1995-05-30 | Vlsi Technology, Inc. | Thin cavity down ball grid array package based on wirebond technology |
US6838755B2 (en) * | 2000-05-23 | 2005-01-04 | Stmicroelectronics S.R.L. | Leadframe for integrated circuit chips having low resistance connections |
KR100609333B1 (en) * | 2000-01-06 | 2006-08-09 | 삼성전자주식회사 | Lead frame comprising mixed inner lead |
US7812429B2 (en) | 2008-02-13 | 2010-10-12 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
-
1988
- 1988-06-10 JP JP14395988A patent/JPH01312866A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5168368A (en) * | 1991-05-09 | 1992-12-01 | International Business Machines Corporation | Lead frame-chip package with improved configuration |
US5420460A (en) * | 1993-08-05 | 1995-05-30 | Vlsi Technology, Inc. | Thin cavity down ball grid array package based on wirebond technology |
KR100609333B1 (en) * | 2000-01-06 | 2006-08-09 | 삼성전자주식회사 | Lead frame comprising mixed inner lead |
US6838755B2 (en) * | 2000-05-23 | 2005-01-04 | Stmicroelectronics S.R.L. | Leadframe for integrated circuit chips having low resistance connections |
US7812429B2 (en) | 2008-02-13 | 2010-10-12 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
US7964941B2 (en) | 2008-02-13 | 2011-06-21 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
US8148200B2 (en) | 2008-02-13 | 2012-04-03 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
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