JPH10242342A - Semiconductor mounting structure - Google Patents
Semiconductor mounting structureInfo
- Publication number
- JPH10242342A JPH10242342A JP3882397A JP3882397A JPH10242342A JP H10242342 A JPH10242342 A JP H10242342A JP 3882397 A JP3882397 A JP 3882397A JP 3882397 A JP3882397 A JP 3882397A JP H10242342 A JPH10242342 A JP H10242342A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- mounting structure
- insulating film
- semiconductor
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は回路基板と半導体素
子との実装構造体に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a circuit board and a semiconductor element.
【０００２】[0002]
【従来の技術】近年、ノートパソコン、携帯電話、ＰＨ
Ｓ、ＰＤＡなどの携帯情報機器、またムービ、カメラな
どの携帯映像機器などで高密度実装のニーズが益々高く
なっている。これに対応すべく、半導体素子の実装は従
来のパッケージ品を実装する方法から、半導体素子を直
接回路基板に実装する、いわゆる、ベアチップ実装方式
が主流になりつつある。2. Description of the Related Art In recent years, notebook computers, mobile phones, PHs
The need for high-density packaging is increasing in portable information devices such as S and PDA, and portable video devices such as movies and cameras. In order to cope with this, the so-called bare chip mounting method, in which the semiconductor element is directly mounted on a circuit board, is becoming the mainstream, instead of the conventional method of mounting a packaged product.
【０００３】従来のベアチップ実装方法は半導体素子を
フェースアップで基板に接続し、半導体素子と回路基板
のパッド間をワイヤボンディング法で接続する方法であ
る。The conventional bare chip mounting method is a method in which a semiconductor element is connected face-up to a substrate, and a pad between the semiconductor element and a circuit board is connected by a wire bonding method.
【０００４】[0004]
【発明が解決しようとする課題】従来のベアチップ実装
構造体は、半導体素子の面積以外にもワイヤボンディン
グ用のパッド面積及びワイヤボンディングによる配線長
を必要とする。これに対し、はんだ、金、導電性接着
剤、異方性導電フィルムなどを接続材料として半導体素
子をフェースダウンで基板に接続接着する（フリップチ
ップアタッチ）方法は、回路基板上の必要搭載面積はチ
ップサイズであり、接続配線長も数十μｍであるため、
究極の高密度実装方式であると考えられる。このフリッ
プチップアタッチは、半導体素子と回路基板を充填樹脂
及び異方性導電フィルムの封止樹脂を硬化して接続信頼
性を確保する方法であるが、回路基板の導体配線によっ
て生じる凹凸が充填樹脂の流動性を低下させ、さらにス
ルーホール等の穴に気泡が残留するため、半導体素子と
回路基板の間隙または半導体素子周辺のフィレット部に
ボイドが発生し、接続信頼性が低下するという問題を有
していた（図３）。また、半導体素子面と対向する回路
基板にスルーホール等が存在することにより、充填樹脂
が裏面に流動して搭載部品の実装を困難にするという問
題も有していた（図４）。The conventional bare chip mounting structure requires a pad area for wire bonding and a wiring length by wire bonding in addition to the area of the semiconductor element. On the other hand, the method of connecting and bonding a semiconductor element to a substrate face down using a solder, gold, a conductive adhesive, an anisotropic conductive film, or the like as a connection material (flip chip attach) requires a required mounting area on a circuit board. Since it is a chip size and the connection wiring length is several tens of μm,
It is considered to be the ultimate high-density mounting method. This flip-chip attach is a method of securing the connection reliability by filling the semiconductor element and the circuit board with the filling resin and the sealing resin of the anisotropic conductive film. Of the semiconductor device and the circuit board, or a fillet around the semiconductor device, resulting in a decrease in connection reliability. (Fig. 3). In addition, the presence of through holes and the like in the circuit board facing the semiconductor element surface also causes a problem that the filling resin flows to the back surface, making it difficult to mount the mounted components (FIG. 4).
【０００５】[0005]
【課題を解決するための手段】本発明は、上記問題を解
決すべく、半導体素子面と対向する回路基板上に絶縁膜
等を設けることで、導体配線により生じる凹凸やスルー
ホール等の穴を回路基板の該絶縁膜や導電粒子等によっ
て極力平滑化したことを特徴とする半導体実装構造体の
構成を備えたものである。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an insulating film or the like on a circuit board facing a semiconductor element surface to reduce unevenness caused by conductor wiring and holes such as through holes. The semiconductor mounting structure is characterized by being smoothed as much as possible by the insulating film and the conductive particles of the circuit board.
【０００６】[0006]
【発明の実施の形態】本発明の実施例について図面を用
いて説明する。Embodiments of the present invention will be described with reference to the drawings.
【０００７】図１は、本発明の半導体の実装構造体の断
面図である。すなわち、はんだ、金、導電性接着剤、あ
るいは異方性導電フイルムの導電粒子等の接続材料２を
用いて、半導体素子６をフェースダウンで回路基板８に
搭載し半導体素子６と回路基板８との電気的接続を行う
実装構造体で、半導体素子６と回路基板８の隙間に充填
樹脂や異方性導電フィルム等の封止樹脂１を充填し硬化
して本発明の半導体の実装構造体を得る。半導体の実装
構造体の接続信頼性を確保するためには、図３に示すボ
イド１０の発生量を低減する必要がある。そこで、半導
体素子６面に対向する回路基板８上に絶縁膜７を設ける
ことで、導体配線３やスルーホール４及びビアホール５
の有無に関係なく、半導体素子６に対向する面の回路基
板８上を極力平坦化してボイド１０の発生量を低減する
ことができる。絶縁膜７は、絶縁膜７の厚さｈ１と導体
配線３の高さｈ２及び接続材料６の高さｈ３によりｈ２
＋ｈ３＋＞ｈ１＞ｈ２を満足する厚さとする。この条件
によって、導体配線３やスルーホール４及びビアホール
５の有無に関係なく、半導体素子６に対向する面の回路
基板８上を極力平坦化することができる。そのため、封
止樹脂１の流動性の低下を防止し、ボイド１０の発生量
を低減し、半導体素子６と回路基板８との絶縁性も確保
できる構造となるため、接続信頼性が向上する。FIG. 1 is a sectional view of a semiconductor mounting structure according to the present invention. That is, the semiconductor element 6 is mounted face down on the circuit board 8 using the connection material 2 such as solder, gold, conductive adhesive, or conductive particles of an anisotropic conductive film. In the mounting structure for electrically connecting the semiconductor device 6, the gap between the semiconductor element 6 and the circuit board 8 is filled with a sealing resin 1 such as a filling resin or an anisotropic conductive film and cured to form the semiconductor mounting structure of the present invention. obtain. In order to ensure the connection reliability of the semiconductor mounting structure, it is necessary to reduce the amount of voids 10 shown in FIG. Therefore, by providing the insulating film 7 on the circuit board 8 facing the surface of the semiconductor element 6, the conductor wiring 3, the through hole 4, and the via hole 5 are provided.
Irrespective of the presence / absence, the surface of the circuit board 8 facing the semiconductor element 6 can be made as flat as possible to reduce the amount of voids 10 generated. The insulating film 7 has a thickness h2 according to the thickness h1 of the insulating film 7, the height h2 of the conductor wiring 3, and the height h3 of the connection material 6.
+ H3 +>h1> h2. Under these conditions, the surface facing the semiconductor element 6 on the circuit board 8 can be made as flat as possible irrespective of the presence or absence of the conductor wiring 3, the through hole 4, and the via hole 5. Therefore, the fluidity of the sealing resin 1 is prevented from being reduced, the amount of the voids 10 is reduced, and the insulating property between the semiconductor element 6 and the circuit board 8 is ensured, so that the connection reliability is improved.
【０００８】図２は本発明の半導体の実装構造体の断面
図である。図２は、図１で絶縁膜７の厚さがｈ１≧ｈ２
の場合でも、スルーホール４やビアホール５の穴を絶縁
膜７で埋めることができない場合が存在する。そこで、
回路基板作製時に、メッキ工程でメッキを成長させてス
ルーホール４やビアホール５の穴を埋めること、もしく
は導電粒子等によってスルーホール４やビアホール５の
穴を埋めることでボイド９の発生量を低減して、接続信
頼性を向上させることができる。FIG. 2 is a sectional view of a semiconductor mounting structure according to the present invention. FIG. 2 shows that the thickness of the insulating film 7 in FIG.
In some cases, the through holes 4 and the via holes 5 cannot be filled with the insulating film 7 in some cases. Therefore,
In producing the circuit board, the plating 9 is grown in a plating step to fill the holes of the through holes 4 and the via holes 5, or the holes 9 of the through holes 4 and the via holes 5 are filled with conductive particles or the like to reduce the amount of voids 9 generated. Thus, connection reliability can be improved.
【０００９】[0009]
【発明の効果】本発明は、半導体素子と対向面に設けた
回路基板上の絶縁膜等により、半導体素子と回路基板と
の絶縁性が向上し、絶縁膜によってボイドの発生量を低
減できるとともに樹脂の流動時間を短くできる効果があ
り、半導体の実装構造体の接続信頼性を向上することが
できる。また、導体配線のスルーホールを絶縁膜もしく
は導体粒子等を形成して表面層を埋めることで、回路基
板裏面への封止樹脂の流出を防ぐことができる。According to the present invention, the insulating property between the semiconductor element and the circuit board is improved by the insulating film on the circuit board provided on the surface facing the semiconductor element, and the amount of voids can be reduced by the insulating film. There is an effect that the flow time of the resin can be shortened, and the connection reliability of the semiconductor mounting structure can be improved. Further, by forming an insulating film or conductive particles in the through holes of the conductor wiring and filling the surface layer, it is possible to prevent the sealing resin from flowing out to the back surface of the circuit board.
【図１】本発明の半導体の実装構造体の一実施例の断面
図。FIG. 1 is a sectional view of an embodiment of a semiconductor mounting structure of the present invention.
【図２】本発明の半導体の実装構造体の第二実施例の断
面図。FIG. 2 is a sectional view of a second embodiment of the semiconductor mounting structure of the present invention.
【図３】半導体素子と対向する面の回路基板が導体配線
によって生じる凹凸を持った状態で実装した半導体実装
構造体の断面図。FIG. 3 is a cross-sectional view of a semiconductor mounting structure in which a circuit board on a surface facing a semiconductor element is mounted with irregularities caused by conductor wiring.
【図４】半導体素子と対向する面の回路基板が導体配線
によって生じるスルーホール等の穴が存在した状態で実
装した半導体実装構造体の断面図。FIG. 4 is a cross-sectional view of a semiconductor mounting structure in which a circuit board on a surface facing a semiconductor element is mounted in a state where holes such as through holes formed by conductor wiring exist.
１…封止樹脂、 ２…接続材料、 ３…電極パッド、 ４…スルーホール、 ５…ビアホール、 ６…半導体素子、 ７…絶縁膜、 ８…回路基板、 ９…導電粒子、 １０…ボイド、 １１…樹脂の裏面流出。 DESCRIPTION OF SYMBOLS 1 ... sealing resin, 2 ... connection material, 3 ... electrode pad, 4 ... through hole, 5 ... via hole, 6 ... semiconductor element, 7 ... insulating film, 8 ... circuit board, 9 ... conductive particles, 10 ... void, 11 ... Resin on the back of the resin.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 成川 泰弘 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 (72)発明者 浅田 豊樹 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiro Narukawa 292 Yoshidacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside of Hitachi, Ltd. Hitachi, Ltd. Production Technology Laboratory
Claims (4)
合、半導体素子面と対向する回路基板の絶縁性を、基板
側の絶縁膜により確保することを特徴とする半導体の実
装構造体。1. A semiconductor mounting structure, wherein when a semiconductor element is mounted face down, insulation of a circuit board facing the semiconductor element surface is ensured by an insulating film on the substrate side.
回路基板の導体配線によって生じる表面層の凹凸を極力
小さくした半導体の実装構造体。2. A semiconductor mounting structure in which the insulating film according to claim 1 minimizes unevenness of a surface layer caused by conductor wiring of the circuit board.
回路基板の導体配線によって生じる基板内層への穴を絶
縁膜により穴の表面を埋めて極力平滑化した半導体の実
装構造体。3. A semiconductor mounting structure in which a hole in an inner layer of a substrate, which is formed by conductor wiring of the circuit board, is smoothed as much as possible by filling the surface of the hole with an insulating film by the insulating film according to claim 1.
合、上記半導体素子の面と対向する回路基板の平滑性
を、上記回路基板の導体配線によって生じる上基板内層
への穴を上記導体粒子によって穴の表面を埋めて極力平
滑化したことを特徴とする半導体の実装構造体。4. When the semiconductor element is mounted face down, the smoothness of the circuit board facing the surface of the semiconductor element is improved by using a hole in the upper substrate inner layer caused by conductor wiring of the circuit board. A semiconductor mounting structure characterized in that the surface of the semiconductor is filled and smoothed as much as possible.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3882397A JPH10242342A (en) | 1997-02-24 | 1997-02-24 | Semiconductor mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3882397A JPH10242342A (en) | 1997-02-24 | 1997-02-24 | Semiconductor mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10242342A true JPH10242342A (en) | 1998-09-11 |
Family
ID=12535976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3882397A Pending JPH10242342A (en) | 1997-02-24 | 1997-02-24 | Semiconductor mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10242342A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009135428A (en) * | 2007-11-09 | 2009-06-18 | Panasonic Corp | Mounted structural body and method of manufacturing the same |
-
1997
- 1997-02-24 JP JP3882397A patent/JPH10242342A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009135428A (en) * | 2007-11-09 | 2009-06-18 | Panasonic Corp | Mounted structural body and method of manufacturing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20060427 |