JPH10242270A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the EM resistance deterioration of upper layer wirings with suppressing the coupling capacitance between the upper layer wirings by including Al films in these wirings; this film selectively and directly covering contact plugs which connect the upper layer wirings to lower layer wirings. SOLUTION: An upper layer wiring 121a connected to a lower layer semiconductor 111a through contact holes 115a is composed of Al films 142a, 143a and Ti nitride film 144a; the film 142a perfectly covering the top ends of plugs 116 at the top ends of the holes 115a to thereby easily suppress the increase of the contact resistance between the wiring 121a and plugs 116. This easily suppresses the local increase of the current density of the wiring 121a at and near the tops of the holes 115a and hence the electromigration resistance reduction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multi-layer wiring and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, in semiconductor devices having multilayer wiring, the width and spacing of wiring in each layer have been reduced and the diameter of contact holes for connecting wiring belonging to different layers has been reduced. Is required. The relationship between the conventional upper layer wiring and the contact hole was as follows. Since the line width at the portion covering the contact hole was set wider than the line width of the upper layer wiring at the portion away from the contact hole, the upper layer wiring completely covered the upper end of the contact hole. More specifically, assuming that the line width of the upper wiring at a position away from the contact hole has the minimum processing size, the upper wiring width at the portion covering the contact hole has at least the minimum processing size (the upper wiring with respect to the contact hole). 2) The value obtained by adding twice the value of the alignment margin. That is, the minimum value of the conventional wiring pitch of the upper layer wiring and the arrangement pitch of the contact holes was 2 × (minimum processing dimension + alignment margin).

In addition, since the inspector ratio of a contact hole provided between a lower wiring and an upper wiring becomes higher with higher integration, the upper wiring is directly connected to the lower wiring via the contact hole. Instead, the connection between the upper layer wiring and the lower layer wiring tends to be performed via a contact plug formed of a conductive film filling the contact hole. Further, in order to suppress an increase in the sheet resistance of the upper wiring due to a reduction in the line width itself of the upper wiring, it is apt to be avoided to increase the thickness of the conductor film (constituting these upper wirings). is there. When the thickness of the upper wiring is increased, the coupling capacitance (parasitic capacitance) between the adjacent upper wirings is increased and the high-speed operation characteristics of the semiconductor device are reduced. It is set to a thin value (within the allowable range of the current density required for these upper wirings).

Under these technical trends, reflecting the further demand for high integration, in recent multilayer wiring, the minimum value of the wiring pitch of the upper layer wiring and the minimum pitch of the arrangement pitch of the contact holes are each 2 × minimum processing dimension. (Such contact holes are called borderless contact holes). That is, for example, the line width of the upper layer wiring is not set particularly wide even at the upper end of the contact hole, but is set to a constant value. As a result, in multilayer wiring having borderless contact holes, alignment of
The margin is also neglected, and an event occurs that a part of the upper end of each contact hole (contact plug) is not covered with the upper wiring.

[0005]

In particular, a multilayer wiring in which a contact plug is mainly composed of a tungsten film and an upper wiring is mainly composed of an aluminum alloy film (containing aluminum having an atomic weight smaller than that of tungsten) is mainly used. Consider a case where the contact hole is formed of the borderless contact hole in the semiconductor device provided. At this time, it is likely that a part of the upper end of the contact plug is not covered with the upper layer wiring, and this causes various problems.

First, in the multilayer wiring having the above structure, the electromigration (abbreviated as EM) resistance of the upper wiring tends to decrease in a portion where current mainly flows from the contact plug to the upper wiring. For this reason, voids in the aluminum alloy film are likely to be generated immediately above or near the contact plug of the upper wiring, and the reliability of the upper wiring is likely to be deteriorated.
The EM due to this aluminum atom is generated in the same direction as the current, and increases as the current density of the upper wiring increases.
The rate tends to be determined by the interface (contact surface) between the upper wiring and the contact plug. In the multilayer wiring having the above structure, the contact area between the contact plug and the upper wiring at the upper end of the contact plug is smaller than the surface area of the upper end of the contact plug. Therefore, the effective current density at the contact surface between the contact plug and the upper wiring becomes higher (than the current density of the upper wiring at a position separated from the contact plug), and the EM is rate-limited at this contact surface. EM here is more likely to occur due to the fact that the current density is locally increased.

For this EM, if, for example, in the upper wiring of the minimum wiring pitch, a spacer made of a conductive film is formed on the side surface of these upper wiring, the above E
The increase in M can be suppressed. However, in this case, the interval between the upper wirings is reduced as a whole, and as a result, the coupling capacitance (parasitic capacitance) between the adjacent upper wirings is increased and the high-speed operation characteristics of the semiconductor device are reduced. .

The second problem is that the contact area between the contact plug and the upper wiring is reduced,
Since the contact resistance (contact resistance) at the contact surface between the plug and the upper wiring increases, the power consumption of the upper wiring (particularly, the power wiring and the like) where EM is likely to occur increases.

Accordingly, an object of the present invention is to provide a contact
In a semiconductor device having a multilayer wiring mainly composed of a tungsten film as a plug and an aluminum alloy film as an upper wiring, deterioration of the EM resistance of the upper wiring is suppressed while suppressing an increase in coupling capacitance between adjacent upper wirings. It is an object of the present invention to provide a semiconductor device having a multilayer wiring having a structure that can easily suppress the increase in power consumption and a method for manufacturing the same.

[0010]

The first aspect of the semiconductor device of the present invention is characterized in that the lower surface wiring provided on the surface of the semiconductor substrate or on the surface of the semiconductor substrate is an interlayer insulating film having a flat upper surface. This interlayer insulating film is provided with contact holes having a diameter equal to the minimum processing dimension and reaching these lower wirings, and these contact holes are filled with a contact plug including at least a tungsten film. Further, at least the bottom of these contact plugs directly connected to these lower wirings is made of a barrier conductor film, and the upper wiring connected to the lower wirings through the contact plugs is An aluminum film that selectively and directly covers the upper end of the contact plug; Directly covers the upper surface of the interlayer insulating film and a small distance further in that it comprises at least an aluminum alloy film connected directly to these aluminum film directly above the upper end of these contact plugs. Preferably, an upper end of the contact plug substantially coincides with an upper surface of the interlayer insulating film. More preferably, the upper surface of the aluminum alloy film is directly covered with a second barrier conductor film having a second required thickness.

The semiconductor device according to the second aspect of the present invention is characterized in that the surface of the semiconductor substrate or the lower wiring provided on the surface of the semiconductor substrate is covered with an interlayer insulating film having a flat upper surface. The insulating film is provided with contact holes having a diameter equal to the minimum processing dimension and reaching these lower wirings, and these contact holes are filled with a contact plug including at least a tungsten film. The bottom of these contact plugs directly connected to these lower wirings is made of a barrier conductor film, and the upper wiring connected to the lower wiring via the contact plugs has a required thickness. An aluminum alloy film provided on the upper surface of the interlayer insulating film with a minimum line width and a minimum interval equal to the minimum processing dimension; In that it comprises at least an aluminum film covering the side surfaces of these aluminum alloy film directly on the upper end just above and the upper end just above the vicinity of the transfected plug. Preferably, a second barrier conductor film having a second required thickness is provided between the bottom surface of the aluminum alloy film and the interlayer insulating film, and further, these second barrier conductor films are provided. Is directly connected to the upper end of the contact plug, and the upper surface of the aluminum alloy film is
Are directly covered with a third barrier conductor film having a required film thickness, and the side surfaces of the second and third barrier conductor films are located immediately above and near the upper end of the contact plug. It is directly covered by the aluminum film. Alternatively, a second barrier conductor film having a second required thickness is provided between the bottom surface of the aluminum alloy film and the interlayer insulating film.
And the upper surface of the aluminum alloy film excluding the area immediately above the upper end of the contact plug and the area immediately above the upper end of the contact plug has a third required thickness. A side surface of the second barrier conductor film is directly covered with the aluminum film immediately above the contact plug and in the vicinity of an upper end of the contact plug; Further, the upper surface of the aluminum alloy film is directly covered with these aluminum films. More preferably, the upper end of the contact plug substantially coincides with the upper surface of the interlayer insulating film.

A feature of a third aspect of the semiconductor device of the present invention is that a surface of a semiconductor substrate or a lower wiring provided on the surface of the semiconductor substrate is covered with an interlayer insulating film having a flat upper surface, and a minimum processing is performed. An upper layer wiring provided on the upper surface of the interlayer insulating film with a minimum line width and a minimum interval equal to the dimensions has a diameter equal to the minimum processing size provided in the interlayer insulating film and has A semiconductor device connected to these lower wirings through contact holes reaching the wiring, wherein a surface of the interlayer insulating film at an upper end portion of the contact hole has a minimum processing dimension in a longitudinal direction of the upper wiring. Recesses having a long length and having a width equal to the minimum processing dimension in a direction perpendicular to the longitudinal direction are provided so as to overlap with these contact holes, and the bottom surfaces of these recesses are formed on the upper surface. The contact hole and the concave portion are provided at a position higher than the upper surface of the lower wiring, and the contact hole and the recess are filled with a contact plug including at least a tungsten film. The bottoms of these contact holes in the plug and the bottoms of these recesses in these contact plugs are made of a barrier conductor film, and the upper wiring further contains an aluminum alloy film of at least a required thickness. . Preferably, a second barrier conductor film having a second required thickness is provided between the bottom surface of the aluminum alloy film and the interlayer insulating film, and further, these second barrier conductor films are provided. The film connects directly to the top of the contact plug,
The upper surface of the aluminum alloy film is directly covered with a third barrier conductor film having a third required thickness.
More preferably, the upper end of the contact plug substantially coincides with the upper surface of the interlayer insulating film.

A feature of the first aspect of the method of manufacturing a semiconductor device according to the present invention is that a lower wiring is formed on a surface of a semiconductor substrate, and an interlayer insulating film having a flat upper surface is formed to cover these lower wirings. Forming a contact hole reaching the lower wiring with a diameter equal to the minimum processing size in the interlayer insulating film; forming a first barrier conductor film on the entire surface; A tungsten film is formed on the entire surface, and the tungsten film and the first barrier conductor film which cover the upper surface of the interlayer insulating film are removed by a CMP method to fill the contact hole with the tungsten film and the first barrier conductor. Forming a contact plug composed of a film, and forming an aluminum film in a self-aligned manner on the upper end of the contact plug by a vapor deposition method, Forming an aluminum alloy film having a first required thickness on the entire surface and forming a second barrier conductor film having a second required thickness on the entire surface; and forming at least the second barrier conductor film and aluminum An upper layer comprising an aluminum film and a pattern of these laminated conductor films having a minimum line width and a minimum interval equal to the minimum processing size by patterning the laminated conductor film composed of an alloy film by anisotropic etching. And forming a wiring. Preferably, the anisotropic etching for patterning the laminated conductor film including the second barrier conductor film and the aluminum alloy film is ECR plasma etching. More preferably, in the anisotropic etching for patterning the laminated conductor film including the second barrier conductor film and the aluminum alloy film, the element or the compound of the element except aluminum constituting the aluminum alloy film is removed. By monitoring, the etching of the aluminum film in the anisotropic etching is suppressed.

A feature of a second aspect of the method of manufacturing a semiconductor device according to the present invention is that a lower layer wiring is formed on the surface of the semiconductor substrate, and an interlayer insulating film having a flat upper surface is formed to cover the lower layer wiring. Forming a contact hole having a diameter equal to the minimum processing dimension and reaching these lower wirings in the interlayer insulating film; and forming a first barrier conductor film over the entire surface by a sputtering method. A tungsten film is formed on the entire surface by a growth method, and the tungsten film covering the upper surface of the interlayer insulating film and the first barrier conductor film are removed by a CMP method to fill the contact hole. Forming a contact plug made of a barrier conductor film, forming a second barrier conductor film having a first required thickness on the entire surface, and forming a second portion on the entire surface by sputtering; Forming an aluminum alloy film having a thickness of 3 nm, forming a third barrier conductor film having a third required thickness on the entire surface, and further forming an insulating film on the entire surface by a vapor deposition method; The film is patterned by anisotropic etching, and the laminated conductor film including the third barrier conductor film, the aluminum alloy film, and the second barrier conductor film is patterned by anisotropic etching to obtain a minimum processing dimension. Forming a pattern consisting of these laminated conductor films having a minimum line width and a minimum interval equal to,
Forming a photoresist film having an opening immediately above and near the upper end of the contact plug and covering the upper surface of the interlayer insulating film including the pattern made of the laminated conductor film; An aluminum film is formed in a self-aligned manner on the side surfaces of these laminated conductor films immediately above and immediately above the upper ends of these contact plugs by chemical vapor deposition using a mask. And a step of forming an upper layer wiring composed of a pattern formed of these laminated conductor films. Preferably, the sputtering method for forming the first barrier conductor film is a collimation sputtering method. More preferably, the source gas in the chemical vapor deposition of the aluminum film is a vaporized gas of tri-methyl aluminum or a vaporized gas of メ チ ル -methyl aluminum hydride.

A feature of a third aspect of the method of manufacturing a semiconductor device according to the present invention is that a lower layer wiring is formed on a surface of a semiconductor substrate, the lower layer wiring is covered, a flat upper surface is formed, and a silicon oxide is formed. Forming an interlayer insulating film made of a film, forming a silicon nitride film covering an upper surface of the interlayer insulating film, having a diameter equal to a minimum processing size, penetrating the silicon nitride film and the interlayer insulating film, and forming a lower layer of these layers; Forming a contact hole reaching the wiring, forming a first titanium nitride film over the entire surface by sputtering, forming a tungsten film over the entire surface by vapor deposition, and covering the upper surface of the silicon nitride film by CMP A contact plug made of the tungsten film and the first titanium nitride film which fills the contact hole by removing the tungsten film and the first titanium nitride film. Forming a second titanium nitride film having a first required thickness over the entire surface, forming an aluminum alloy film having a second required thickness over the entire surface by sputtering, and forming a third aluminum nitride film over the entire surface. Forming a titanium / tungsten film of a required film thickness, further forming a first silicon oxide film over the entire surface by vapor phase epitaxy, and oxidizing the first silicon oxide film by patterning by anisotropic etching. A silicon film cap is formed, and a laminated conductor film composed of the titanium-tungsten film, the aluminum alloy film, and the second titanium nitride film is patterned by anisotropic etching to obtain a minimum line width and a minimum interval equal to the minimum processing size. Forming a pattern composed of these laminated conductor films having the following steps; and forming a second silicon oxide film on the entire surface, and etching the second silicon oxide film with an etch barrier. Forming a silicon oxide film spacer covering the side surface of the pattern made of the laminated conductor film, and having an opening just above the contact plug and in the vicinity of the upper end of the contact plug. A photoresist film covering the upper surface of the interlayer insulating film including the pattern is formed, and the silicon oxide film cap, the silicon oxide film spacer, and the titanium / tungsten film are etched by a buffered hydrofluoric acid solution using the photoresist film as a mask. Removing the photo-resist film; and performing chemical vapor deposition on the side surfaces of the second titanium nitride film and the side surfaces of the aluminum alloy film immediately above and near the upper end of the contact plug. And an aluminum film is formed in a self-aligned manner with the upper surface. A step of forming an upper layer wiring composed of a pattern composed of Preferably, the sputtering method for forming the first titanium nitride film is a collimation sputtering method. More preferably, the source gas in the chemical vapor deposition of the aluminum film is a vaporized gas of trimethyl aluminum, a vaporized gas of ヂ methyl aluminum hydride, or a vaporized gas of tri-isobutyl aluminum. .

A feature of a fourth aspect of the method of manufacturing a semiconductor device according to the present invention is that a surface of a semiconductor substrate or a lower wiring provided on the surface of the semiconductor substrate is covered with an interlayer insulating film having a flat upper surface. An upper layer wiring provided on the upper surface of the interlayer insulating film having a minimum line width and a minimum interval equal to the minimum processing size, having an aperture equal to the minimum processing size provided in the interlayer insulating film; A method of manufacturing a semiconductor device which is connected to these lower wirings through contact holes that reach these lower wirings, wherein the lower wirings are formed on or on the surface of the semiconductor substrate, and the lower wirings are covered. Forming an interlayer insulating film having a flat upper surface, and forming an upper surface of the interlayer insulating film in a region of the surface of the interlayer insulating film which overlaps a region where an upper end of the contact hole is to be formed. It has a length longer than the minimum processing dimension in the longitudinal direction in which the upper wiring is to be formed, has a width equal to the minimum processing dimension in a direction perpendicular to the longitudinal direction, and is located at a position higher than the upper surface of these lower wirings. Forming a concave portion having a bottom portion, and forming a contact hole penetrating at least a part of the bottom portion of the concave portion and having a diameter equal to a minimum processing size and reaching the lower wiring in the interlayer insulating film; A first barrier conductor film is formed on the entire surface by sputtering, a tungsten film is formed on the entire surface by vapor deposition, and the tungsten film and the first barrier conductor covering the upper surface of the interlayer insulating film by CMP. Removing the film to fill the contact hole and the concave portion to form a contact plug composed of the tungsten film and the first barrier conductor film; A second barrier conductor film having a first required thickness is formed, an aluminum alloy film having a second required thickness is formed on the entire surface by sputtering, and a third required thickness is formed on the entire surface. (3) forming a barrier conductor film, and patterning the laminated conductor film including the third barrier conductor film, the aluminum alloy film and the second barrier conductor film by anisotropic etching to form the upper wiring. And forming. Preferably, the sputtering method for forming the first barrier conductor film is a collimation sputtering method.

[0017]

Next, the present invention will be described with reference to the drawings.

FIG. 1A is a schematic plan view of a semiconductor device.
Referring to FIG. 1B and FIG. 1B and FIG. 1C, which are schematic cross-sectional views taken along line AA and line BB in FIG. Semiconductor devices
0.4 where the minimum processing dimension is 0.4 μm (400 nm) and the alignment margin is 0.05 μm (50 nm)
This is a semiconductor device having a multilayer wiring according to the μm design rule (and process technology), and is as follows. In the schematic cross-sectional views of FIGS. 1B and 1C, only the semiconductor substrate and the conductor film are hatched to avoid complication, and the hatching for the insulator film is omitted. In addition, various line widths, intervals, contact hole diameters, and the like described below are based on ideal conditions ignoring fluctuations (or variations) such as reduction or enlargement depending on a manufacturing method such as etching. Are described on the premise of the value of (a value equal to the design target value).

For example, on the surface of the silicon substrate 101, the lower wirings 111 a, 111 b, 11
1c, 111d and the like are provided. The insulating film 10
Reference numeral 2 denotes a LOCOS type field oxide film having a thickness of, for example, about 0.4 μm, and the upper surface of the insulating film 102 is not necessarily required to be flat. Further, in the present embodiment, the lower layer wiring is not limited to the one provided on the surface of the silicon substrate 101 (when the upper surface of each lower layer wiring has the same height). May be included. The minimum line width and the minimum interval of these lower wirings 111a and the like are each 0.4 μm, and the minimum wiring pitch is 0.8 μm. The film thickness of these lower wirings 111a and the like (excluding the lower wiring formed of a diffusion layer) is, for example, 0.4
μm. When the lower wiring 111a or the like mainly includes an aluminum alloy film, the lower wiring 111a
Are covered with a barrier conductor film such as a titanium nitride film.

The lower wirings 111a, 111b, 111c,
The upper surface of the insulating film 102 including 111d and the like is covered with an interlayer insulating film 112 made of a silicon oxide film. The upper surface of the interlayer insulating film 112 is flat.
The thickness of the interlayer insulating film immediately above 1a is 1.0 μm. In the interlayer insulating film 112, the lower wirings 111a and 111
Contact holes 115 reaching 1b, 111c, 111d
a, 115b, 115c, and 115d are provided.
The diameter of these contact holes 115a and the like is 0.4 μm, and the closest contact hole (for example, contact hole 11
5a and the contact hole 115b) are also 0.4 μm, and the minimum arrangement pitch of the contact holes is 0.8 μm. The exposed portion formed in the lower wiring 111a by the contact hole 115a is mainly the upper surface. The height difference exists between the
An exposed portion is also formed on a part of the side surface of the lower wiring 111a due to the shift of the mask alignment in lithography. The width of the gap formed by the contact hole 115a on the side surface of the lower wiring 111a is a value equal to or less than the alignment margin, and is at most 0.05 μm.
(50 nm).

Contact holes 115a, 115b, 115
c and 115d are filled with contact plugs 116, respectively. The upper end of the contact plug 116 substantially coincides with the upper surface of the interlayer insulating film 112. The contact plug 116 is formed by stacking a tungsten film 132a on a first barrier conductor film, for example, a titanium nitride film 131a. The first barrier conductor film is not limited to a titanium nitride film, but may be a titanium-tungsten film. For example, when the lower wiring includes a diffusion layer, the first barrier conductor film may be formed of a titanium film and a titanium nitride film. Become. The thickness of the titanium nitride film 131a and the like on the upper surface of the lower wiring 111a and the like is preferably at least about 50 nm in order to function as a barrier conductor film. The thickness of the titanium nitride film 131a or the like in the portion directly covering the side surface such as the contact hole 115a is several times the thickness of the titanium nitride film 131a or the like in the portion provided on the upper surface of the lower wiring 111a or the like. About 1.

Contact holes 115a, 115b, 115
The upper ends of the contact plugs 116 provided on the c and 115d are aluminum films 142a and 142b, respectively.
It is directly covered by 142c and 142d. These aluminum films 142a, 142b, 142c, 14
Each film thickness of 2d is, for example, about 0.2 μm.
The aluminum alloy films 143a, 143b, 14 provided directly on the upper surface of the interlayer insulating film 112 so as to cover the upper surface.
The film thickness of each of 3c and 143d is, for example, about 0.4 μm.
These aluminum alloy films 143a, 143b, 14
3c, 143d are contact holes 115a, 115b, 1
At the upper ends of 15c and 115d, they are directly connected to aluminum films 142a, 142b, 142c and 142d, respectively. The minimum line width and minimum interval of the aluminum alloy film 143a and the like are each 0.4 μm, and the minimum wiring pitch is 0.8 μm. These aluminum alloy films 143a are, for example, 0.5 wt. % Of copper alloy. These aluminum alloy films 1
The upper surfaces of 43a, 143b, 143c and 143d are second barrier conductor films each having a thickness of, for example, 25 nm or more.
50 nm titanium nitride films 144a, 144b, 144
c, 144d directly. The second barrier conductor film is not limited to a titanium nitride film, but may be a titanium-tungsten film. These titanium nitride films 1
44a and the like improve the resistance to stress migration (abbreviated as SM) of the upper wiring and also have a function as an anti-reflection film (although it is an advantage in a manufacturing method).

The lower wiring 1 is formed through the contact hole 115a.
The upper wiring 121a connected to the lower wiring 11a is composed of an aluminum film 142a, an aluminum alloy film 143a, and a titanium nitride film 144a. The upper wiring 121b connected to the lower wiring 111b through the contact hole 115b is an aluminum film 142b, an aluminum alloy film. 143b
And upper layer wiring 121c connected to lower layer wiring 111c through contact hole 115c is formed of aluminum film 142c, aluminum alloy film 143c and titanium nitride film 144c, and is formed of lower layer through contact hole 115d. The upper wiring 121d connected to the wiring 111d is an aluminum film 142
d, aluminum alloy film 143d and titanium nitride film 1
44d.

In the present example of the first embodiment, the existence of the aluminum film 142a and the like becomes important (here,
For example, if the aluminum film 142a does not exist, the structure becomes the same as a multilayer wiring structure having a normal borderless contact hole, and the problem of the present invention cannot be solved. For example, the upper wiring 121a is formed in the contact hole 115a.
The upper end of the contact plug 116 is completely covered by the aluminum film 142a at the upper end of the contact plug 116, and the contact area between the upper wiring 121a and the contact plug 116 becomes (0.4 μm) ² . Therefore, according to the present example of the first embodiment, it is easy to suppress an increase in the contact resistance between the upper wiring and the contact plug, and it is possible to suppress the increase in the upper end of the contact hole or in the vicinity thereof. It is easy to suppress a local increase in the current density of the upper wiring, and it is easy to suppress a decrease in EM resistance. The distance between adjacent upper wirings becomes narrower than 0.4 μm (minimum processing size) and the thickness of the aluminum-based metal film becomes thicker, not just on the upper wiring but on the top of the contact hole (contact plug). Because of the limited portion, it is easy to suppress an increase in coupling capacitance between adjacent upper-layer wirings.

The aluminum alloy film 143a covers the upper surface of the interlayer insulating film 112 via another barrier conductor film (different from the titanium nitride film 144a) (interlayer insulating film 11a).
2 has an upper layer wiring of a two-layer structure), and an aluminum alloy film 143a is connected to an aluminum film 142a via another barrier conductor film at the upper end of the contact hole 115a (contact plug 116). Is not preferred. In this case, aluminum film 142a is regarded as forming the upper end of contact plug 116 filling contact hole 115a, and the contact between aluminum film 142a and another barrier conductor film (pattern) is formed. The area (that is, the contact area between the upper wiring and the contact plug) is (0.4 μm).
m) Since it is smaller than ^2, the increase of the contact resistance and the increase of the current density cannot be prevented.

Referring to FIG. 1 together with FIGS. 2 and 3 which are schematic cross-sectional views of the manufacturing process taken along the line AA in FIG. 1A, according to one example of the first embodiment. The semiconductor device is formed as follows.

First, an insulating film 102 made of a LOCOS type field oxide film having a thickness of, for example, about 0.4 μm and covering the surface of the silicon substrate 101 is formed. On the surface or on the surface of the silicon substrate 101 (for example, the insulating film 102
Via) the lower wirings 111a, 111b, 111c, 1
11d and the like are formed. The thickness of the lower wiring other than the diffusion layer formed on the surface of the silicon substrate 101 is, for example, 0.4 μm.
m. A silicon oxide film is formed on the entire surface, and the upper surface of the silicon oxide film is planarized by a CMP method, so that an interlayer insulating film 112 is formed. The difference between the upper surface of the lower wiring 111a formed on the upper surface of the flat portion of the insulating film 102 and the upper surface of the interlayer insulating film 112 is, for example, 1.0 μm. By photolithography using anisotropic etching, contact holes 115a, 115b, 115c, 115d having a diameter of 0.4 μm and reaching the lower wirings 111a, 111b, 111c, 111d are formed in the interlayer insulating film 112. You. It is easy to prevent these contact holes 115a and the like from reaching the bottom surface of the lower wiring 111a and the like (FIGS. 1 and 2A). If the lower wiring includes a lower wiring having an upper surface with a height difference of 0.4 μm or more from the upper surface of the lower wiring 111a (for example, a diffusion layer formed on the surface of the silicon substrate 101), the above photo- It is preferable to form contact holes reaching these lower wirings by photolithography different from lithography.

Next, the contact hole 1 is formed by sputtering.
A titanium nitride film 131 is formed on the entire surface including the surface 15a and the like. In order for the titanium nitride film 131 to function as a barrier conductor film with respect to the lower wiring 111a or the like, on the upper surface of the lower wiring 111a or the like at the bottom of the contact hole 115a or the like,
It is preferable that the thickness of the titanium nitride film 131 be about 50 nm. If the sputtering method is an ordinary sputtering method, the film thickness on the side wall of the contact hole 115a is 10 nm.
In the case of the collimation sputtering method, the thickness is at most about 5 nm. When a diffusion layer is included in the lower wiring, a titanium film is preferably formed in advance under the titanium film 131. Subsequently, a film thickness of 400 nm to 500 nm is formed on the entire surface by a blanket CVD method using tungsten hexafluoride (WF ₆ ) and monosilane (SiH ₄ ) as source gases and hydrogen (H ₂ ) as a carrier gas.
Approximately tungsten film 132 is formed. Since the filling property of the tungsten film 132 into the contact hole 115a and the like is excellent, the coverage of the titanium nitride film 131 is not hindered in the gap formed between the side surface of the lower wiring 111a and the like and the contact hole 115a. Even if there is, the portion is almost completely filled with the tungsten film 132 (FIG. 2B). Note that the selective growth of the tungsten film instead of the formation of the tungsten film 132 by the blanket CVD method does not necessarily mean that the upper surfaces of all the lower wirings have the same height, and the depth of the contact holes reaching the lower wirings is not always the same. Are not always the same, which is not preferable.

Subsequently, the tungsten film 132 and the titanium nitride film 131 are subjected to a CMP method until the tungsten film 132 and the titanium nitride film 131 on the upper surface of the interlayer insulating film 112 are completely removed.
A contact plug 116 made of a tungsten film 132a and a titanium nitride film 131a is formed in the interior of the semiconductor device 15a and the like. The upper end of the contact plug 116 is substantially flat, and furthermore, the interlayer insulating film 11 is substantially flat.
2 (FIG. 1 and FIG. 2 (c)). Since the upper surface of the interlayer insulating film 112 is flat, such a contact plug 116 can be formed by the CMP method. Forming the contact plug 116 having such a shape by the etch-back method without using the CMP method requires an etching gas (or etching condition) in which the etching rates of the tungsten film 132 and the titanium nitride film 131 are substantially equal. Not easy because there is nothing. According to the etch-back method, the shape of the upper end of the contact plug has a step, which hinders the preferable formation (selective growth) of the aluminum film in the next step.

Next, the CVD method (low pressure CVD (LPCV)
D) method), the contact holes 115a, 115b, 1
Contact plug 116 filled with 15c and 115d
Aluminum films 142a, 142 each having a thickness of about 200 nm selectively and directly covering
b, 142c and 142d are formed. At this time, since the shape of the upper end of the contact plug 116 is as described above, it is easy to form the aluminum film 142a or the like having a shape that is not affected by step coverage [FIGS.
(A)]. If irregularities are present at the upper end of the contact plug 116, the upper surface of the aluminum film 142a or the like is not flat, but has irregularities. Will occur.

Selective LPCVD of this aluminum film
As a raw material gas, a vaporized gas of trimethyl aluminum (Al (CH ₃ ) ₃ ), a vaporized gas of ヂ · methyl aluminum hydride (Al · H (CH ₃ ) ₂ ) or tri-isobutyl・ Aluminum (A
A vaporized gas of l (CH ₂ · CH (CH ₃ ) ₂ ) ₃ ) is used, and hydrogen (H ₂ ) and nitrogen (N ₂ ) are used as carrier gases. For example, tri-iso-butyl aluminum is vaporized at about 20 ° C. and about 25 Pa, and Δ-methyl aluminum hydride is vaporized at about 20 ° C. and about 270 Pa.
Vaporize to the extent. When tri-isobutylaluminum vaporized gas is used as a source gas, the temperature is 250 ° C., 130 ° C.
When the LPCVD method at about Pa is used, and when a vaporized gas of ヂ · methyl aluminum hydride is used as a source gas, L at 100 ° C. to 250 ° C. and about 130 Pa is used.
The PCVD method is adopted.

Next, at a substrate temperature of 150 ° C. to 250 ° C., a 400 nm-thick aluminum alloy film 143 made of aluminum-copper is formed on the entire surface by sputtering. For forming the aluminum alloy film 143, a high-temperature sputtering method is not preferable (for the reason described later). Subsequently, a film thickness of 25 nm to 5
A titanium nitride film 144 of about 0 nm is formed [FIG.
(B)].

Next, a mixed gas of boron chloride (BCl ₃ ) and chlorine (Cl ₂ ) is adopted as an etching gas.
The titanium nitride film 144 and the aluminum alloy film 143 are sequentially etched by anisotropic dry etching using the photo resist film as a mask. At this time, although the aluminum film 142a and the like are also etched,
Since it is necessary to leave the aluminum film 142a or the like completely covering the upper end of the contact plug 116, it is preferable to suppress the etching of the aluminum film 142a as small as possible. Thereby, the aluminum film 14
Aluminum alloy films 143a, 143 directly connected to the upper surfaces of 2a, 142b, 142c, 142d, respectively.
b, 143c, 143d are formed, and the titanium nitride films 144a, 144 directly cover the upper surfaces of these aluminum alloy films 143a, 143b, 143c, 143d, respectively.
4b, 144c and 144d are formed, and the upper layer wiring 121 is formed.
a, 121b, 121c, and 121d are formed (FIG. 1). After the photo-resist film is removed, an aluminum film or the like is subjected to alloying heat treatment at about 450 ° C. By this heat treatment, the aluminum alloy film 143
The interface between a and the aluminum film 142a substantially disappears.

The above anisotropic etching requires etching controllability. At least aluminum alloy film 1
It is preferable to lower the etching rate near the interface between the aluminum film 43 and the aluminum film 142a. For example, 800
If the flow rates of boron chloride and chlorine are 3 sccm and 6 sccm under the power of W and 1.3 Pa, respectively, the etching rate of these aluminum-based films becomes extremely low at about 50 nm / min. Further, means for detecting the interface in the anisotropic etching is required. In this case, since the aluminum alloy film 143 contains copper, the etching end point of the aluminum alloy film 143 is determined by emission spectrum analysis of copper chloride (CuCl ₂ ) or secondary ion mass spectrum analysis (SIMS) of copper. Perform detection. In particular, when the end point of etching is detected by SIMS, it is preferable that the etching rate in the above-mentioned etching be low because the response delay is large.

When the upper surface of the aluminum film 142a or the like has irregularities, the detection of the interface becomes unclear. Further, if the aluminum alloy film 143 is formed by a high temperature sputtering method,
3 is diffused into the aluminum film 142a during the formation of the aluminum alloy film 143 and the aluminum film 142.
Since the interface with a or the like becomes unclear, it becomes difficult to suppress the etching of the aluminum film 142a or the like by the monitoring method in the anisotropic etching. For example, Japanese Patent Application Laid-Open No. Hei 6-260441, which was previously filed by the present applicant, relates to a method of manufacturing an upper layer wiring utilizing the provision of the upper end of a contact plug lower than the upper end of a contact hole.・ Even if the contact hole is applied, when patterning the aluminum alloy film and the barrier conductor film to form the upper layer wiring, the aluminum alloy film and the barrier conductor film filling the upper end of the contact hole are selectively left. This is not easy due to the micro-loading effect of anisotropic etching.

In the first embodiment, the contact
An aluminum film is formed on the upper end of the plug by selective growth, and the object of the invention is achieved by utilizing the presence of the aluminum film. On the other hand, in the second embodiment of the present invention, the upper wiring is (a pattern of) a laminated conductor film including an aluminum alloy film and at least the laminated conductor film immediately above the contact plug and near the upper end of the contact plug. The object of the present invention has been attained by forming an aluminum film directly covering the side surface of (pattern).

FIG. 4A is a schematic plan view of a semiconductor device.
4B and FIG. 4C, which are schematic cross-sectional views taken along line AA and line BB in FIG. 4A, the first embodiment of the second embodiment of the present invention. The semiconductor device according to the example is also a semiconductor device having a multilayer wiring according to a 0.4 μm design rule (and process technology) in which a minimum processing dimension is 0.4 μm and an alignment margin is 0.05 μm. I have. 4 (b),
In the schematic cross-sectional view of (c), only the semiconductor substrate and the conductive film are hatched to avoid complication, and the hatching for the insulator film is omitted. In addition, various line widths, intervals, contact hole diameters, and the like described below are based on ideal conditions ignoring fluctuations (or variations) such as reduction or enlargement depending on a manufacturing method such as etching. Are described on the premise of the value of (a value equal to the design target value).

For example, the lower wirings 211aa, 211a are formed on the surface of the silicon substrate 201a via the insulating film 202a.
b, 211ac, 211ad, etc. are provided. The insulating film 202a is, for example, an LO film having a thickness of about 0.4 μm.
An insulating film 202a made of a COS type field oxide film
Does not necessarily have to be flat. Furthermore, the lower wiring in the first example of the second embodiment is also limited to the wiring provided on the surface of the silicon substrate 201a (when the upper surfaces of the respective lower wirings have the same height). Instead, a diffusion layer or the like constituting a semiconductor element provided on the surface of the silicon substrate 201a may be included. The minimum line width and the minimum interval of the lower wiring 211aa and the like are each 0.4 μm, and the minimum wiring pitch is 0.8 μm. When the lower wiring 211aa or the like is not a diffusion layer, the film thickness of the lower wiring 211aa or the like is, for example, 0.4 μm.

The lower wirings 211aa, 211ab, 211
The upper surface of the insulating film 202a including ac, 211ad, and the like is covered with an interlayer insulating film 212a made of a silicon oxide film. The upper surface of the interlayer insulating film 212a is flat. For example, the thickness of the interlayer insulating film immediately above the lower wiring 211aa is 1.
0 μm. In the interlayer insulating film 212a, lower wirings 211aa, 211ab, 211ac, 211ad are provided, respectively.
Contact holes 215aa, 215ab, 215 reaching
ac, 215ad are provided. The diameter of these contact holes 215aa and the like is 0.4 μm, the interval between the closest contact holes (for example, contact hole 215aa and contact hole 215ab) is 0.4 μm, and the minimum arrangement pitch of the contact holes is 0.8 μm. Becomes The width of the gap formed by the side surface of the lower wiring 211aa and the side surface of the contact hole 215aa is a value equal to or less than the alignment margin, and is at most 0.05 μm (50 nm).

Contact holes 215aa, 215ab, 2
15ac and 215ad are contact plug 2 respectively
16a. Contact plug 21
The upper end of 6a substantially coincides with the upper surface of the interlayer insulating film 212a. The contact plug 216a is formed by stacking a tungsten film 232a on a first barrier conductor film, for example, a titanium nitride film 231a. The first barrier conductor film is not limited to a titanium nitride film, but may be a titanium-tungsten film. For example, when the lower wiring includes a diffusion layer, the first barrier conductor film may be formed of a titanium film and a titanium nitride film. Become. The thickness of the titanium nitride film 231a on the upper surface of the lower wiring 211aa is preferably at least about 50 nm in order to function as a barrier conductor film.
The thickness of the titanium nitride film 231a at the portion directly covering the side surface such as the contact hole 215aa is not limited even if the thickness is lower.
Titanium nitride film 231 at the portion provided on the upper surface of 1aa
The thickness is about a fraction of the thickness of a.

Contact holes 215aa, 215ab, 2
On the upper ends of the contact plugs 216a provided on the 15ac and 215ad, titanium nitride films 241aa and 241aa having a thickness of about 50 nm, which are second barrier conductor films, respectively.
1ab, 241ac, and 241ad are directly connected. These titanium nitride films 241aa, 241ab, 2
41ac and 241ad are interlayer insulating films 212a, respectively.
Each of which has a form directly covering the upper surface of
12a extends on the upper surface. The minimum line width and minimum interval of these titanium nitride films 241aa, 241ab, 241ac, 241ad are each 0.4 μm. The second barrier conductor film is not limited to a titanium nitride film, but may be a titanium film, a laminated film of a titanium film and a titanium nitride film, or a titanium / tungsten film. These titanium nitride films 241aa, 241ab, 241ac, 24
On the upper surface of 1ad, the aluminum alloy films 243aa, 243ab, 243ac, and 243a have the appearance of directly covering the respective upper surfaces and have the same shape as these titanium nitride films.
d is provided. The film thickness of the aluminum alloy film 243aa or the like is, for example, 0.4 μm, for example, 0.5 wt.
% Of copper alloy.

These aluminum alloy films 243aa, 243aa,
The upper surfaces of 243ab, 243ac, and 243ad are third barrier conductor films, for example, each having a thickness of 25 nm to 5 nm.
0 nm titanium nitride films 244aa, 244ab, 244
ac, directly covered by 244ad. The third barrier conductor film is not limited to a titanium nitride film,
A titanium / tungsten film may be used. Further, the upper surfaces of the titanium nitride films 244aa, 244ab, 244ac, 244ad are respectively covered with silicon oxide film caps 246aa, 246aa,
246ab, 246ac, 246ad are directly covered. For example, a laminated conductor film (pattern) including the titanium nitride film 241aa, the aluminum alloy film 243aa, and the titanium nitride film 244aa is formed by a contact hole 215
In aa, the upper end of the contact plug 216a filling the contact hole 215aa is not always completely covered. This is due to misalignment in photolithography, and the maximum width of the exposed portion of the contact plug 216a that is not covered by the laminated conductive film is about 50 nm (equal to the alignment margin).

For example, in the laminated conductor film (pattern) including the titanium nitride film 241aa, the aluminum alloy film 243aa, and the titanium nitride film 244aa, the contact hole 2
The side surface of the laminated conductor film just above the upper end of the contact plug 216a filling the hole 15aa and in the vicinity of, for example, within 0.2 μm from the upper end of the contact plug 216a has a thickness of 50 nm to 100 n.
m of the aluminum film 247aa. Further, the aluminum film 247aa directly and completely covers the exposed portion of the contact plug 216a which is not covered with the laminated conductor film.

The upper wiring 221aa connected to the lower wiring 211aa through the contact hole 215aa is composed of a titanium nitride film 241aa, an aluminum alloy film 243aa, a titanium nitride film 244aa, and an aluminum film 247aa, and the lower wiring through the contact hole 215ab. The upper wiring 221ab connected to 211ab is composed of a titanium nitride film 241ab, an aluminum alloy film 243ab, a titanium nitride film 244ab, and an aluminum film 247ab. It is composed of a film 241ac, an aluminum alloy film 243ac, a titanium nitride film 244ac, and an aluminum film 247ac, and is connected to the lower wiring 211ad through a contact hole 215ad. Upper wiring 221ad which is titanium nitride film 241Ad, aluminum alloy film 243Ad, and a titanium nitride film 244ad and aluminum film 247Ad.

In the first example of the second embodiment, the presence of the aluminum film 247aa and the like becomes important (here, for example, if the aluminum film 247aa does not exist, a normal borderless contact hole is formed). It becomes the same as the multi-layer wiring structure which has, and cannot solve the problem of the present invention). For example, at the upper end of the contact hole 215aa, the titanium nitride film 241aa and the aluminum film 247a
a completely covers the upper end of the contact plug 216a, and the contact area between the upper wiring 221aa and the contact plug 216a becomes (0.4 μm) ² . Therefore, the first example of the second embodiment is also
As in the first embodiment of the first embodiment, it is easy to suppress an increase in the contact resistance between the upper wiring and the contact plug, and the upper wiring at the upper end portion of the contact hole or in the vicinity thereof can be easily suppressed. , It is easy to suppress a local increase in the current density, and it is easy to suppress a decrease in EM resistance. 0.4 μm spacing between upper wiring
Since the narrower than the (minimum processing dimension) is not limited to the entire upper layer wiring but to the upper portion of the contact hole and a portion in the vicinity thereof, it is easy to suppress an increase in coupling capacitance between adjacent upper layer wirings. (Note that the fact that the aluminum film 247aa and the like are provided on the entire side surface of the laminated conductor film (pattern) increases the coupling capacitance between adjacent upper-layer wirings.
Not preferred).

The upper layer wiring according to the first example of the second embodiment is thicker than the upper layer wiring according to the example of the first embodiment. However, this increase in film thickness hardly causes an increase in coupling capacity. Unless voids of aluminum (alloy) are generated immediately above (and in the vicinity of) the contact holes by EM, the resistivity of titanium nitride is about one to two orders of magnitude higher than the resistivity of aluminum (alloy). This is because only the aluminum alloy film functions as a current path in the upper wiring. Further, in the second embodiment, since the titanium nitride films are provided on the upper surface and the bottom surface of the aluminum alloy film, respectively, it is possible to realize an upper layer wiring having higher SM resistance than the first embodiment. Furthermore, E
Even when a void of aluminum (alloy) is generated immediately above (and in the vicinity of) the contact hole due to M, the upper layer wiring according to the first example of the second embodiment is more suitable for the first embodiment. This is more advantageous than the upper layer wiring according to the above embodiment.

FIG. 5 is a schematic plan view of a main manufacturing process of a semiconductor device, and FIG. 6 is a schematic sectional view taken along line AA in FIG.
Referring to FIG. 4 together with FIG. 4, the semiconductor device of the first example of the second embodiment is formed as follows.

First, an insulating film 202a made of a LOCOS type field oxide film having a thickness of, for example, about 0.4 μm and covering the surface of the silicon substrate 201a is formed. On the surface or on the surface of the silicon substrate 201a, the lower wirings 211aa, 211ab,
211ac, 211ad, etc. are formed. In this case, with reference to the surface of the silicon substrate 201a, the insulating film 20
The upper surface and height of the flat portion 2a are approximately 0.2 μm. The film thickness of the lower wiring 211aa and the like (excluding the diffusion layer formed on the surface of the silicon substrate 201a) is, for example, 0.5 mm.
4 μm. A silicon oxide film is formed on the entire surface,
The upper surface of the silicon oxide film is planarized by the P method,
An interlayer insulating film 212a is formed. The difference between the upper surface of the lower wiring 211aa (formed on the upper surface of the flat portion of the insulating film 202a) and the upper surface of the interlayer insulating film 212a is, for example, 1.0.
μm. By photolithography using anisotropic etching, the interlayer insulating film 212a has a diameter of 0.4 μm and has lower wirings 211aa, 211ab, and 211ab, respectively.
Contact hole 215a reaching 211ac and 211ad
a, 215ab, 215ac, and 215ad are formed (FIG. 4). Note that when the lower wiring includes a lower wiring (for example, a diffusion layer formed on the surface of the silicon substrate 201a) having an upper surface having a height difference of 0.4 μm or more from the upper surface of the lower wiring 211aa, It is preferable to form contact holes reaching these lower wirings by photolithography different from lithography.

Next, a titanium nitride film is formed on the entire surface including the contact holes 215aa and the like by a sputtering method (preferably collimation sputtering method). Lower layer wiring 211
In order for the titanium nitride film to function as a barrier conductor film with respect to aa or the like, the thickness of the titanium nitride film is preferably about 50 nm on the upper surface of the lower wiring 211aa or the like at the bottom of the contact hole 215aa or the like. . When a diffusion layer is included in the lower wiring, a titanium film is preferably formed in advance under the titanium nitride film. continue,
By blanket CVD method, a film thickness of 400 nm
A tungsten film of about 500 nm is formed.

Subsequently, a CMP method is applied until the above-mentioned tungsten film and titanium nitride film on the upper surface of the interlayer insulating film 212a are completely removed, and a tungsten film 232a and a titanium nitride film A contact plug 216a made of 231a is formed. The upper end of the contact plug 216a is substantially flat, and furthermore, the interlayer insulating film 212a
[FIG. 4].

Next, a second titanium nitride film (which is a second barrier conductor film) having a thickness of 50 nm is formed on the entire surface by, for example, a sputtering method. A 400 nm-thick aluminum alloy film (containing copper) is formed on the entire surface, and a 25 nm to 50 nm-thick (third barrier conductor film) third titanium nitride film is formed on the entire surface by, for example, a sputtering method. Is done. Further, a silicon oxide film is formed on the entire surface by the CVD method. Unlike the first embodiment, in the second embodiment, this aluminum alloy film is formed on the surface of the second titanium nitride film (without the aluminum film covering the contact plug). Therefore, a high-temperature sputtering method can be adopted.

Anisotropic etching is performed on the silicon oxide film using a photoresist film (not shown) as a mask, and silicon oxide film caps 246aa and 246 are formed.
ab, 246ac, 246ad are formed. Further, using the photoresist film as a mask, anisotropic etching using a mixed gas of chlorine and boron chloride as an etching gas is performed on the third titanium nitride film, the aluminum alloy film, and the second titanium nitride film. For the titanium nitride films 244aa, 244ab, 244ac, and 244.
ad, and aluminum alloy films 243aa, 243ab,
243ac, 243ad, and a titanium nitride film 241aa,
241ab, 241ac, and 241ad are formed [FIGS. 4, 5A, and 6A].

In anisotropic etching using a mixed gas of chlorine and boron chloride, contact plug 216a
Although the titanium nitride film 231a that directly covers the side surfaces of the contact holes 215aa and the like should be etched off considerably vigorously due to the microloading effect, it is practically hardly etched (deposition due to etching caused by etching). It is speculated that the cause is unknown.) If the first titanium nitride film is formed by the collimation sputtering method as described above, such a problem can be scarcely feared. If the first barrier conductor film is formed of a titanium / tungsten film, this fear can be avoided more reliably. Even if the titanium nitride film 231a is slightly etched away to form a void along the side wall such as the contact hole 215aa, the void is filled by selective growth of the aluminum film in a later step.

After the photo resist film is removed,
0.8μ corresponding to each contact hole 215aa
A photoresist film 252a having an opening of m □ is formed. For example, when two contact holes are located closest to each other, such as a contact hole 215aa and a contact hole 215ab, this photoresist film 252 is used.
Openings corresponding to these contact holes in FIG. 5A are connected [FIGS. 5 (b) and 6 (b)].

Subsequently, the above-mentioned photoresist film 252a is formed.
The exposed side surface of the laminated conductor film (pattern) including the titanium nitride film 241aa, the aluminum alloy film 243aa, the titanium nitride film 244aa, and the like, and the exposure of the contact plug 216a are performed by selective LPCVD of the aluminum film using the mask as a mask. An aluminum film 247aa and the like are selectively formed on the upper surface thus formed. LPC at this time
Since the VD method uses the photoresist film 252a as a mask, it needs to be performed at a substrate temperature of about 100 ° C. to 150 ° C. -It is preferable to use a vaporized gas of aluminum hydride. Thereafter, the photoresist film 252a is removed, and an alloy heat treatment at about 450 ° C. is performed (FIG. 4).

In the manufacturing method according to the first embodiment of the second embodiment, the processing method of the laminated conductor film (pattern) constituting the upper wiring is required in the first embodiment. Such controllability is unnecessary.

FIG. 7A is a schematic plan view of a semiconductor device.
7B and FIG. 7C, which are schematic cross-sectional views taken along line AA and line BB in FIG. 7A, a second embodiment of the second embodiment of the present invention is shown. The semiconductor device according to the example is also a semiconductor device having a multilayer wiring according to a 0.4 μm design rule (and process technology) in which the minimum processing dimension is 0.4 μm and the alignment margin is 0.05 μm. The main difference between the semiconductor device of the first embodiment and the semiconductor device according to the first embodiment is that the upper surface of the upper wiring immediately above the contact hole (contact plug) and in the vicinity of the upper end is formed of an aluminum film instead of the third barrier conductor film. And is as follows. 7B and 7C, only the semiconductor substrate and the conductor film are hatched to avoid complication, and the hatching for the insulator film is omitted.

For example, on the surface of the silicon substrate 201b, via the insulating film 202b, the lower wirings 211ba, 211b
b, 211bc, 211bd, etc. are provided. The insulating film 202b has a thickness of, for example, about 0.4 μm.
An insulating film 202b made of a COS type field oxide film
Does not necessarily have to be flat. Furthermore, the lower wiring in the first example of the second embodiment is also limited to the wiring provided on the surface of the silicon substrate 201b (when the upper surface of each lower wiring has the same height). Instead, a diffusion layer or the like constituting a semiconductor element provided on the surface of the silicon substrate 201b may be included. The minimum line width and the minimum interval of these lower wirings 211ba and the like are each 0.4 μm, and the minimum wiring pitch is 0.8 μm. When the lower wiring 211ba or the like is not a diffusion layer, the film thickness of the lower wiring 211ba or the like is, for example, 0.4 μm.

The lower wirings 211ba, 211bb, 211
The upper surface of the insulating film 202b including bc, 211bd and the like is covered with an interlayer insulating film 212b made of a silicon oxide film. The upper surface of the interlayer insulating film 212b is flat, and for example, the thickness of the interlayer insulating film immediately above the lower wiring 211ba is 0.1 mm.
95 μm. The upper surface of the interlayer insulating film 212b has a thickness of 25
It is directly covered with a silicon nitride film 213 of about 0 nm. Silicon nitride film 213 and interlayer insulating film 212b
And the lower wirings 211ba and 211ba, respectively.
Contact holes 215ba, 215bb, 215bc, 215bd reaching 11bb, 211bc, 211bd are provided. The diameter of each of the contact holes 215ba and the like is 0.4 μm, and the closest contact holes (for example, the contact hole 215ba and the contact hole 215bb)
Is also 0.4 μm, and the minimum arrangement pitch of the contact holes is 0.8 μm. The width of the gap formed by the side surface of the lower wiring 211ba and the side surface of the contact hole 215ba is a value equal to or less than the alignment margin, and is at most 0.05 μm (50 nm).

Contact holes 215ba, 215bb, 2
15bc and 215bd are contact plugs 2 respectively.
16b. Contact plug 21
The upper end of 6b substantially coincides with the upper surface of the silicon nitride film 213. The contact plug 216b is formed by stacking a tungsten film 232b on a first barrier conductor film, for example, a titanium nitride film 231b. For example, when the lower wiring includes a diffusion layer, the lower wiring is a film in which a titanium nitride film is laminated on a titanium film. The thickness of the titanium nitride film 231b on the upper surface of the lower wiring 211ba is preferably at least about 50 nm in order to function as a barrier conductor film. The thickness of the titanium nitride film 231b at the portion directly covering the side surface such as the contact hole 215ba is at most a fraction of the thickness of the titanium nitride film 231b at the portion provided on the upper surface of the lower wiring 211ba. It is. In the second embodiment, it is not preferable that the first barrier conductor film is made of a titanium / tungsten film.

Contact holes 215ba, 215bb, 2
On the upper ends of the contact plugs 216b provided on the bases 15bc and 215ad, titanium nitride films 241ba and 241ba having a thickness of about 50 nm, which are second barrier conductor films, respectively.
1bb, 241bc and 241bd are directly connected. These titanium nitride films 241ba, 241bb, 2
41bc and 241bd are the silicon nitride films 21 respectively.
3 directly over the upper surface of the reached silicon film 213 with the form of directly covering the upper surface. These titanium nitride films 241ba, 241bb, 241bc, 241bd
Are 0.4 μm each. The second barrier conductor film is preferably a titanium film, a titanium nitride film, or a laminated film of a titanium film and a titanium nitride film, and is not preferably a titanium-tungsten film. These titanium nitride films 241ba, 241b
b, 241bc, and 241bd have the appearance of directly covering the respective upper surfaces, and have aluminum alloy films 243ba, 243bb,
243bc and 243bd are provided. The film thickness of the aluminum alloy film 243ba or the like is, for example, 0.4 μm, for example, 0.5 wt. % Of copper alloy.

The contact holes 215ba and 215
Except for the range right above the upper ends of bb, 215bc, and 215bd and the range of 0.2 μm from immediately above the upper ends, the upper surfaces of the aluminum alloy films 243ba, 243bb, 243bc, and 243bd are third barrier conductor films, for example, each having a thickness of 25 nm to 50 nm titanium / tungsten film 245b
a, 245bb, 245bc, 245bd. Further, a titanium / tungsten film 145 is formed.
ba, 145bb, 145bc, 145bd
Silicon oxide film caps 246ba, 246b, respectively
b, 246bc, and 246bd. Furthermore, a silicon oxide film cap 246ba,
Titanium / tungsten film ba, aluminum alloy film 24
3ba and the side surface of the laminated film composed of the titanium nitride film 241ba, the silicon oxide film cap 246bb, the titanium
A side surface of a stacked film including the tungsten film bb, the aluminum alloy film 243bb, and the titanium nitride film 241bb;
Side surface of a stacked film composed of a silicon oxide film cap 246bc, a titanium / tungsten film bc, an aluminum alloy film 243bc and a titanium nitride film 241bc, and a silicon oxide film cap 246bd and a titanium / tungsten film b
d, the side surfaces of the laminated film composed of the aluminum alloy film 243bd and the titanium nitride film 241bd are each directly covered with a silicon oxide film spacer 248b having a thickness of, for example, about 50 nm. In the second example of the second embodiment, it is preferable that the third barrier conductor film is a titanium / tungkuten film.

For example, a laminated conductor film (pattern) composed of an aluminum alloy film 243ba and a titanium nitride film 244ba is formed in the contact hole 215ba by the contact plug 21 filling the contact hole 215ba.
The upper end of 6b is not always completely covered. This is a photo
This is due to misalignment in lithography, and is not covered by this laminated conductor film.
The maximum width of the exposed portion of the plug 216b is (alignment
(Equal to the margin) is about 50 nm.

In portions not covered by the silicon oxide film cap 246ba and the silicon oxide film spacer 248b, the upper and side surfaces of the laminated conductor film (pattern) composed of the aluminum alloy film 243ba and the titanium nitride film 244ba and the laminated conductor film The upper end of the contact plug 216b filling the contact hole 215ba exposed without being covered with the body film (pattern) has a thickness of 50 nm to 10 nm.
It is directly covered with a 0 nm aluminum film 247ba. The upper wiring 221ba is formed of an aluminum film 247.
ba, a titanium / tungsten film 247ba, an aluminum alloy film 243ba, and a titanium nitride film 241ba. In a portion not covered with the silicon oxide film cap 246bb and the silicon oxide film spacer 248b, a laminated conductor film (pattern) including the aluminum alloy film 243bb and the titanium nitride film 244bb
And the upper end of the contact plug 216b filling the contact hole 215bb exposed without being covered with the laminated conductor film (pattern).
It is directly covered by a 100 nm aluminum film 247bb. The upper wiring 221bb is formed of the aluminum film 2
47bb, titanium / tungsten film 247bb, aluminum alloy film 243bb, and titanium nitride film 241bb
It is composed of Silicon oxide film cap 246b
c and the silicon oxide film spacer 248b, the top and side surfaces of the laminated conductor film (pattern) composed of the aluminum alloy film 243bc and the titanium nitride film 244bc, and the portion covered with the laminated conductor film (pattern). The upper end of the contact plug 216b filling the contact hole 215bc exposed without being touched has a film thickness of 50.
is directly covered with an aluminum film 247bc of nm to 100 nm. The upper wiring 221bc includes an aluminum film 247bc, a titanium / tungsten film 247bc,
Aluminum alloy film 243bc and titanium nitride film 24
1bc. Silicon oxide film cap 2
46bd and an aluminum alloy film 243bd in a portion not covered with the silicon oxide film spacer 248b.
And side surfaces of the laminated conductor film (pattern) made of the silicon nitride film 244bd and the contact hole 215 exposed without being covered by the laminated conductor film (pattern)
The upper end of the contact plug 216b filling the bd is an aluminum film 247bd having a thickness of 50 nm to 100 nm.
Directly covered by The upper layer wiring 221 bd is made of an aluminum film 247 bd, a titanium / tungsten film 24.
7bd, an aluminum alloy film 243bd and a titanium nitride film 241bd.

In the second example of the second embodiment, the aluminum films 247aa, 247ab, 247ac, 2 in the first example of the second embodiment are used.
The function of 47ad is replaced by aluminum film 247ba, 2
47bb, 247bc, and 247bd respectively.

FIG. 8 and FIG. 7, which are schematic cross-sectional views of the main manufacturing steps of the semiconductor device and are schematic cross-sectional views taken along the line BB of FIG. The semiconductor device of the second embodiment is formed as follows.

First, an insulating film 202b made of a LOCOS type field oxide film having a thickness of, for example, about 0.4 μm and covering the surface of the silicon substrate 201b is formed. On the surface or on the surface of the silicon substrate 201b, the lower wirings 211ba, 211bb, (for example, via the insulating film 202b) are provided.
211bc, 211bd, etc. are formed. The film thickness of the lower wiring 211ba and the like (excluding the diffusion layer formed on the surface of the silicon substrate 201b) is, for example, 0.4 μm. A silicon oxide film is formed on the entire surface, and the upper surface of the silicon oxide film is flattened by the CMP method.
Is formed. The upper surface of the lower wiring 211ba (formed on the upper surface of the flat portion of the insulating film 202b) and the interlayer insulating film 2
The difference from the upper surface of 12b is, for example, 0.95 μm. CV
By the method D, a film thickness 50 covering the upper surface of the interlayer insulating film 212b is formed.
A silicon nitride film 213 of about nm is formed. By photolithography using anisotropic etching, the laminated insulating film composed of the silicon nitride film 213 and the interlayer insulating film 212b has a diameter of 0.4 μm and contacts reaching the lower wirings 211ba, 211bb, 211bc, 211bd, respectively. Holes 215ba, 215bb, 215b
c, 215bd are formed (FIG. 7). Note that the lower wiring (for example, the silicon substrate 201b) has an upper surface having a height difference of 0.4 μm or more from the upper surface of the lower wiring 211ba.
In this case, it is preferable to form a contact hole reaching the lower wiring by photolithography different from the above photolithography.

Next, a titanium nitride film is formed on the entire surface including the contact holes 215ba and the like by a sputtering method (preferably collimation sputtering method). Lower layer wiring 211
In order for the titanium nitride film to function as a barrier conductor film with respect to ba or the like, the thickness of the titanium nitride film is preferably about 50 nm on the upper surface of the lower wiring 211ba or the like at the bottom of the contact hole 215ba or the like. . When a diffusion layer is included in the lower wiring, a titanium film is preferably formed in advance under the titanium nitride film. continue,
By blanket CVD method, a film thickness of 400 nm
A tungsten film of about 500 nm is formed.

Subsequently, a CMP method is applied until the above-mentioned tungsten film and titanium nitride film on the upper surface of the silicon nitride film 213 are completely removed, and the tungsten film 232b and the titanium nitride film 231b contact plug 216b
Are formed. The upper end of the contact plug 216b is substantially flat, and furthermore, the silicon nitride film 21
3 (FIG. 7).

Next, a second titanium nitride film (which is a second barrier conductor film) having a thickness of 50 nm is formed on the entire surface by, for example, a sputtering method, and then, for example, by a high-temperature sputtering method at a temperature of about 400 ° C. A 400 nm-thick aluminum alloy film (containing copper) is formed on the entire surface, and a 25 nm to 50 nm-thick (third barrier conductor film) third titanium nitride film is formed on the entire surface by, for example, a sputtering method. Is done. Further, a silicon oxide film is formed on the entire surface by the CVD method. Unlike the first embodiment, in the second embodiment, this aluminum alloy film is formed on the surface of the second titanium nitride film (without the aluminum film covering the contact plug). Therefore, a high-temperature sputtering method can be adopted.

Anisotropic etching using a fluorine-based etching gas is sequentially performed on the silicon oxide film and the titanium / tungsten film using a photo resist film (not shown) as a mask. Cap 24
6ba, 246bb, 246bc, 246bd and titanium / tungsten films 245ba, 245bb, 245b
c, 245bd are formed. Further, using the photoresist film as a mask, anisotropic etching using a mixed gas of chlorine and boron chloride as an etching gas is sequentially performed on the aluminum alloy film and the second titanium nitride film, and Alloy films 243ba and 243
bb, 243bc, 243bd and the titanium nitride film 241
ba, 241bb, 241bc and 241bd are formed.

During anisotropic etching using a mixed gas of chlorine and boron chloride, contact plug 216b
The titanium nitride film 231b that directly covers the side surfaces of the contact holes 215ba and the like should be etched off considerably vigorously by the micro-loading effect, but is hardly actually etched. Even if the titanium nitride film 231b is slightly etched away to form a gap along the side wall such as the contact hole 215ba, the gap is filled by selective growth of the aluminum film in a later step.

After the photo-resist film is removed,
50n film thickness over the entire surface by CVD method with excellent step coverage
An about m silicon oxide film 248 is formed [FIG.
(A)]. This silicon oxide film 248 is etched back to form a silicon oxide film spacer 248b.

Next, each contact hole 215ba
A photoresist film 252b having an opening of 0.8 .mu.m.quadrature. Is formed. For example, contact hole 21
When two contact holes are located closest to each other, such as 5ba and a contact hole 215bb, openings corresponding to these contact holes in the photoresist film 252b are connected. Using the photoresist film 252b as a mask, wet etching with buffered hydrofluoric acid is performed, and a silicon oxide film spacer 248b is formed.
And silicon oxide film caps 246ba, 246bb,
246bc, 246bd and titanium / tungsten film 2
45ba, 245bb, 245bc and 245bd are removed [FIG. 8 (b)]. During this wet etching, the upper surface of the interlayer insulating film 212b is
3 and is not etched. Also,
Since the first and second barrier conductor films are each made of a titanium nitride film, the titanium nitride film 231b and the titanium nitride film 2
41ba, 241bb, 241bc and 241bd are not etched.

Next, after the photo-resist film 252b is removed, the laminated conductor film (pattern) including the aluminum alloy film 243aa and the titanium nitride film 244aa is exposed by the selective LPCVD method of the aluminum film. Side and top and contact plug 216
An aluminum film 247ba and the like are selectively formed on the exposed upper surface of b. In this case, the LPCVD method can be performed at a higher substrate temperature (for example, 250 ° C.) than in the first embodiment. Thereafter, the photoresist film 252a is removed, and an alloy heat treatment is performed at about 450 ° C. (FIG. 7).

In the first and second embodiments, the purpose is achieved by adopting the aluminum film by selective growth, respectively, but the present invention is not limited to these. In the third embodiment of the present invention, a means is provided in which a concave portion overlapping the contact hole is provided on the surface of the interlayer insulating film to effectively widen the upper end of the contact hole.

FIG. 9A is a schematic plan view of a semiconductor device.
9 (b) and 9 (c), which are schematic cross-sectional views taken along lines AA and BB of FIG. 9 (a), according to an example of the third embodiment of the present invention. Semiconductor devices,
A semiconductor device having a multilayer wiring according to a 0.4 μm design rule (and process technology) with a minimum processing dimension of 0.4 μm and an alignment margin of 0.05 μm;
It is as follows. 9 (b) and 9 (c).
In the schematic cross-sectional views of FIGS. 1A and 1B, only the semiconductor substrate and the conductive film are hatched to avoid complication, and the hatching on the insulator film is omitted.

For example, on the surface of the silicon substrate 301, the lower wirings 311a, 311b, 31
1c, 311d, etc. are provided. The insulating film 30
Reference numeral 2 denotes a LOCOS type field oxide film having a thickness of, for example, about 0.4 μm, and the upper surface of the insulating film 302 is not necessarily required to be flat. Further, the lower wiring in the present example of the third embodiment is also limited to the wiring provided on the surface of the silicon substrate 301 (when the upper surfaces of the respective lower wirings have the same height). Instead, a diffusion layer or the like constituting a semiconductor element provided on the surface of the silicon substrate 301 may be included. The minimum line width and minimum interval of these lower wirings 311a and the like are each 0.4 μm, and the minimum wiring pitch is 0.8 μm. Lower layer wiring 31
If 1a is not a diffusion layer, these lower wirings 311a
The film thickness is 0.4 μm, for example.

The lower wirings 311a, 311b, 311c,
The upper surface of the insulating film 302 including 311d and the like is covered with an interlayer insulating film 312 made of a silicon oxide film. The upper surface of the interlayer insulating film 312 is flat.
The thickness of the interlayer insulating film immediately above 1a is 1.0 μm. Lower interlayer wirings 311a and 311,
Contact holes 315 reaching 1b, 311c, 311d
a, 315b, 315c, 315d and these contact holes 315a, 315b, 315c, 315d overlap, and these contact holes 315a, 315b, 315
c, 315d, 314b, 314c, 314c having an appearance extending in the longitudinal direction of the upper wiring connected to 315d.
14d. These recesses 314a, 3
14b, 314c, and 314d each have a length in the longitudinal direction of the upper layer wiring of, for example, 0.6 μm, a width in a direction perpendicular to the longitudinal direction of 0.4 μm, respectively. Are, for example, respectively 0.2 μm. Contact holes 315a, 315
b, 315c and 315d are concave portions 314a and 31 respectively.
4b, 314c, and 314d have a form penetrating a part of the bottom surface. The diameter of the contact holes 315a and the like is 0.4 μm, the interval between the closest contact holes (for example, the contact holes 315a and 315b) is 0.4 μm, and the minimum arrangement pitch of the contact holes is 0.8 μm. Becomes The width of the gap formed by the side surface of the lower wiring 311a and the side surface of the contact hole 315a is a value equal to or less than the alignment margin, and is at most 0.
05 μm (50 nm).

Recess 314a and contact hole 315a
Recess 314b and contact hole 315b, recess 314c and contact hole 315c, recess 314d
The contact holes 315d are filled with contact plugs 316, respectively. The upper end of the contact plug 316 substantially coincides with the upper surface of the interlayer insulating film 312 and is substantially flat. The contact plug 316 is formed by stacking a tungsten film 332 on, for example, a titanium nitride film 331 which is a first barrier conductor film. The first barrier conductor film is not limited to a titanium nitride film, but may be a titanium-tungsten film. For example, when the lower wiring includes a diffusion layer, the first barrier conductor film may be formed of a titanium film and a titanium nitride film. Become. Bottom of recess 314a and lower wiring 3
The thickness of the titanium nitride film 331 on the upper surface of 11a is at least 50 to function as a barrier conductor film.
It is preferably about nm. Contact hole 315a
The thickness of the titanium nitride film 331 in the portion directly covering the side surface is approximately a fraction of the thickness of the titanium nitride film 331 in the portion provided on the upper surface of the lower wiring 311a.

Recess 314a and contact hole 315a
Plug 316 and recess 314b provided in
And a contact provided in the contact hole 315b.
Plug 316, recess 314c and contact hole 315
c, contact plug 316 and recess 314
and a titanium nitride film 341a having a thickness of about 50 nm, which is a second barrier conductor film, is formed on the upper end of the contact plug 316 provided in the contact hole 315d.
341b, 341c, and 341d are directly connected. These titanium nitride films 341a, 341b, 341
Each of c and 341d has a form directly covering the upper surface of the interlayer insulating film 212a and extends on the upper surface of the interlayer insulating film 212a. These titanium nitride films 341
The minimum line width and minimum interval of a, 341b, 341c, and 341d are each 0.4 μm. The second barrier conductor film is not limited to a titanium nitride film,
It may be a titanium film, a laminated film of a titanium film and a titanium nitride film, or a titanium-tungsten film. The upper surface of each of the titanium nitride films 341a, 341b, 341c, and 341d has a form directly covering the respective upper surfaces, and has an aluminum alloy film 343 having the same shape as these titanium nitride films.
a, 343b, 343c, and 343d.
The thickness of the aluminum alloy film 343a or the like is, for example, 0.4 μm.
m, for example, 0.5 wt. % Of copper alloy.

These aluminum alloy films 343a and 343a
The upper surfaces of 43b, 343c, and 343d are titanium barrier films 344a, 344b, 344c, and 344d, for example, each having a thickness of 25 nm to 50 nm, which are third barrier conductor films.
Directly covered by The third barrier conductor film is not limited to a titanium nitride film, but may be a titanium-tungsten film. Recess 314a and contact hole 31
Upper layer wiring 3 connected to lower layer wiring 311a via 5a
21a is a titanium nitride film 341a, an aluminum alloy film 3
An upper wiring 321b composed of a titanium nitride film 341b, an aluminum alloy film 343b, and a titanium nitride film 344b is formed by a concave portion 314c. The upper wiring 321c connected to the lower wiring 311c through the contact hole 315c is composed of a titanium nitride film 341c, an aluminum alloy film 343c, and a titanium nitride film 344c, and is connected to the lower wiring 311d through the recess 314d and the contact hole 315d. The upper layer wiring 321d to be formed is composed of a titanium nitride film 341d, an aluminum alloy film 343d and a titanium nitride film 344d.

The upper wiring 321a does not always completely cover the upper end of the contact plug 316 filling the recess 314a and the contact hole 315a in the recess 314a and the contact hole 315a. This is due to misalignment in photolithography, and the maximum width of the exposed portion of the contact plug 316 that is not covered by the laminated conductor film is (alignment
(Equal to the margin) is about 50 nm. However, even if the contact area between the upper wiring 321a and the contact plug 316 is minimized in consideration of the misalignment, (0.6−0.05) × (0.4−0.05)
Since μm = 0.1925 μm ² , this contact area is larger than (0.4 μm) ² . For this reason, the present example of the third embodiment also has the same effects as those of the first and second embodiments.

FIG. 10 is a schematic plan view of a main manufacturing process of the semiconductor device, FIG. 11 is a schematic sectional view taken along line AA of FIG. 10, and FIG. 12 is a schematic sectional view taken along line BB of FIG.
Referring to FIG. 9 together with FIG. 9, the semiconductor device according to the example of the third embodiment is formed as follows.

First, an insulating film 302 made of a LOCOS type field oxide film having a thickness of, for example, about 0.4 μm and covering the surface of the silicon substrate 301 is formed. On the surface or on the surface of the silicon substrate 301 (for example, the insulating film 302
Via) lower wirings 311a, 311b, 311c, 3
11d and the like are formed. In this case, the silicon substrate 301
The upper surface and the height of the flat portion of the insulating film 302 are approximately 0.2 μm with reference to the surface of. Lower wiring 3 (excluding the diffusion layer formed on the surface of silicon substrate 301)
The film thickness of 11a or the like is, for example, 0.4 μm. A silicon oxide film is formed on the entire surface, and the upper surface of the silicon oxide film is flattened by a CMP method to form an interlayer insulating film 212a. The difference between the upper surface of the lower wiring 311a (formed on the upper surface of the flat portion of the insulating film 302) and the upper surface of the interlayer insulating film 212a is, for example, 1.0 μm.

The lower wirings 311a, 311b, 311c,
Each of the upper wirings connected to these contact holes has a length of 0.6 μm in the longitudinal direction including the region where the contact holes reaching 311d are formed, and has a length of 0.4 μm in the direction perpendicular to these. Concave portions 314a and 314 having a width and a depth of about 0.2 μm
b, 314c, 314d are formed on the surface of the interlayer insulating film 312 by photolithography using anisotropic etching [FIGS. 9, 10 (a), 11 (a), 1].
2 (a)]. The length in these recesses 314a and the like is
It is not limited to 0.6 μm.

By photolithography using anisotropic etching, recesses 314a, 314b, and 314 are formed in interlayer insulating film 212a to have a diameter of 0.4 μm, respectively.
Contact holes 315a, 315b, 315c, and 315d that penetrate a part of the bottom surface of c and 314d and reach the lower wirings 311a, 311b, 311c, and 311d, respectively are formed [FIGS. 9, 10B and 11B. b), FIG.
(B)]. Note that when the lower wiring includes a lower wiring (for example, a diffusion layer formed on the surface of the silicon substrate 301) having an upper surface having a height difference of 0.4 μm or more from the upper surface of the lower wiring 311a, It is preferable to form contact holes reaching these lower wirings by photolithography different from lithography.

Next, a titanium nitride film is formed on the entire surface including the contact holes 315a and the like by a sputtering method (preferably collimation sputtering method). Lower layer wiring 311a
In order for the titanium nitride film to function as a barrier conductor film, the thickness of the titanium nitride film is 50 n
m (at this time, the concave portion 314a
The thickness of the titanium nitride film on the bottom surface of the above also becomes about 50 nm). When a diffusion layer is included in the lower wiring, a titanium film is preferably formed in advance under the titanium nitride film. Subsequently, a tungsten film having a thickness of about 400 nm to 500 nm is formed on the entire surface by blanket CVD. Subsequently, a CMP method is applied until the tungsten film and the titanium nitride film on the upper surface of the interlayer insulating film 312 are completely removed, and the tungsten film 332 and the nitride film Contact made of titanium film 331
A plug 316 is left formed. Contact plug 3
The upper end of 16 is substantially flat, and furthermore, almost coincides with the upper surface of the interlayer insulating film 312 (FIG. 9).

Next, a second titanium nitride film (which is a second barrier conductor film) having a thickness of 50 nm is formed on the entire surface by, for example, a sputtering method, and is entirely formed by, for example, a high-temperature sputtering method at a temperature of about 400 ° C. A 400 nm-thick aluminum alloy film (containing copper) is formed on the entire surface, and a 25 nm to 50 nm-thick (third barrier conductor film) third titanium nitride film is formed on the entire surface by, for example, a sputtering method. Is done.

Using a photoresist film (not shown) as a mask, a mixed gas of chlorine and boron chloride is etched.
Anisotropic etching using a gas is sequentially performed on the third titanium nitride film, the aluminum alloy film, and the second titanium nitride film, and the titanium nitride films 344a, 344b,
344c, 344d, and aluminum alloy film 343a,
343b, 343c, 343d and a titanium nitride film 341
a, 341b, 341c, and 341d are formed, and upper wirings 321a, 321b, 321c, and 321d are formed. After the photoresist film is removed, 450
An alloying heat treatment is performed at about ℃ (FIG. 9).

[0091]

As described above, according to the present invention, in the semiconductor device having the multilayer wiring including the borderless contact hole, the aluminum film is provided by selective growth on the upper end of the contact plug filling the contact hole. The contact plug and the upper wiring are formed by selectively growing the aluminum film on the side surface of the upper wiring at least directly above and near the upper end of the contact hole or by providing a recess connected to the contact hole in the interlayer insulating film. The reduction of the contact area is suppressed. As a result, in a semiconductor device having a multi-layer wiring in which a contact plug is mainly composed of a tungsten film and an upper wiring is mainly composed of an aluminum alloy film, while suppressing an increase in coupling capacitance between adjacent upper wirings, it is possible to reduce the coupling capacitance of the upper wiring. It is easy to suppress the deterioration of the EM resistance and further suppress the increase in power consumption.

[Brief description of the drawings]

FIGS. 1A and 1B are a schematic plan view and a schematic sectional view illustrating an example of the first embodiment of the present invention. FIGS.

FIG. 2 is a schematic cross-sectional view of the manufacturing process of the example of the first embodiment, and is a schematic cross-sectional view taken along line AA in FIG. 1 (a).

FIG. 3 is a schematic cross-sectional view of the manufacturing process of the example of the first embodiment, taken along line AA in FIG.

FIG. 4 is a schematic plan view and a schematic cross-sectional view for explaining a first example of the second embodiment of the present invention.

FIG. 5 is a schematic plan view for explaining main manufacturing steps of the first example of the second embodiment.

FIG. 6 is a schematic cross-sectional view for describing main manufacturing steps of the first example of the second embodiment, and is a cross-sectional schematic view taken along line AA of FIG. 5;

FIG. 7 is a schematic plan view and a schematic cross-sectional view for explaining a second example of the second embodiment of the present invention.

8 is a schematic cross-sectional view for explaining main manufacturing steps of the second example of the second embodiment, and is a schematic cross-sectional view taken along line BB of FIG. 7;

FIG. 9 is a schematic plan view and a schematic cross-sectional view illustrating an example of the third embodiment of the present invention.

FIG. 10 is a schematic plan view for explaining main manufacturing steps of the example of the third embodiment.

FIG. 11 is a schematic cross-sectional view for explaining main manufacturing steps of the one example of the third embodiment, and is a schematic cross-sectional view along the line AA in FIG. 10;

12 is a schematic cross-sectional view for explaining main manufacturing steps of the one example of the third embodiment, and is a schematic cross-sectional view taken along line BB of FIG. 10;

[Explanation of symbols]

101, 201a, 201b, 301 Silicon substrate 102, 202a, 202b, 302 Insulating film 111a to 111d, 211aa to 211ad, 211
ba to 211bd, 311a to 311d Lower wiring 115a to 115d, 215aa to 215ad, 215
ba to 215bd, 315a to 315d Contact holes 116, 216a, 216b, 316
Plugs 121a to 121d, 221aa to 221ad, 221
ba to 221bd, 321a to 321d Upper layer wiring 131, 131a, 144, 144a to 144d, 23
1a, 231b, 241aa to 241ad, 241ba
To 241bd, 244aa to 244ad, 331, 34
1a to 341d, 344a to 344d Titanium nitride film 132, 132a, 231a, 232b, 332 Tungsten film 143, 143a to 143d, 243aa to 243a
d, 243ba to 243bd, 343a to 343d
Aluminum alloy films 142a to 142d, 247aa to 247ad, 247
ba-247bd aluminum film 213 silicon nitride film 246aa-246ad, 246ba-246bd
Silicon oxide film cap 248 Silicon oxide film spacer 252a, 252b Photoresist film 314a-314d Recess

Claims (21)

[Claims] The surface of a semiconductor substrate or a lower wiring provided on the surface of the semiconductor substrate is covered with an interlayer insulating film having a flat upper surface, and the interlayer insulating film has a diameter equal to a minimum processing dimension. A contact hole reaching the lower wiring is provided, the contact hole is filled with a contact plug including at least a tungsten film, and at least a bottom portion of the contact plug directly connected to the lower wiring. Comprises a barrier conductor film, an upper wiring connected to the lower wiring via the contact plug has an aluminum film selectively directly covering an upper end of the contact plug, and a required thickness. Directly covering the upper surface of the interlayer insulating film with a minimum line width and a minimum interval equal to the minimum processing dimension;
A semiconductor device comprising at least an aluminum alloy film directly connected to the aluminum film immediately above the upper end of the plug. 2. The semiconductor device according to claim 1, wherein an upper end of said contact plug substantially coincides with an upper surface of said interlayer insulating film. 3. The method according to claim 1, wherein the upper surface of the aluminum alloy film is a second
3. The semiconductor device according to claim 1, wherein the semiconductor device is directly covered with a second barrier conductor film having a required thickness. 4. A surface of a semiconductor substrate or a lower wiring provided on the surface of the semiconductor substrate is covered with an interlayer insulating film having a flat upper surface, and the interlayer insulating film has a diameter equal to a minimum processing dimension. A contact hole reaching the lower wiring is provided, the contact hole is filled with a contact plug including at least a tungsten film, and at least a bottom portion of the contact plug directly connected to the lower wiring. Comprises a barrier conductor film, and an upper wiring connected to the lower wiring via the contact plug has a required film thickness, a minimum line width equal to a minimum processing dimension, and a minimum interval. An aluminum alloy film provided on the upper surface of the interlayer insulating film, and the aluminum alloy film immediately above and near the upper end of the contact plug; Side semiconductor device characterized by comprising directly covering the aluminum film contains at least a. 5. A second barrier conductor film having a second required thickness is provided between a bottom surface of the aluminum alloy film and the interlayer insulating film, and further includes a second barrier conductor film. A film is directly connected to an upper end of the contact plug; an upper surface of the aluminum alloy film is directly covered by a third barrier conductor film having a third required thickness; 5. The semiconductor device according to claim 4, wherein the side surfaces of the second and third barrier conductor films are directly covered with the aluminum film immediately above and near the upper end of the semiconductor device. 6. A second barrier conductor film having a second required thickness is provided between a bottom surface of the aluminum alloy film and the interlayer insulating film, and further includes a second barrier conductor film. A film is directly connected to the upper end of the contact plug, and the upper surface of the aluminum alloy film except immediately above and immediately near the upper end of the contact plug has a third required thickness. A side surface of the second barrier conductor film is directly covered by the aluminum film immediately above and near the upper end of the contact plug, and is directly covered by the barrier conductor film. 5. The semiconductor device according to claim 4, wherein the upper surface of the aluminum alloy film is directly covered by the aluminum film. 7. The semiconductor device according to claim 4, wherein an upper end of said contact plug substantially coincides with an upper surface of said interlayer insulating film. 8. A surface of a semiconductor substrate or a lower wiring provided on the surface of the semiconductor substrate is covered with an interlayer insulating film having a flat upper surface, and has a minimum line width and a minimum interval equal to a minimum processing dimension. The upper wiring provided on the upper surface of the interlayer insulating film is connected to the lower wiring via a contact hole having a diameter equal to the minimum processing dimension provided in the interlayer insulating film and reaching the lower wiring. The upper surface of the interlayer insulating film at the upper end of the contact hole has a length longer than a minimum processing dimension in a longitudinal direction of the upper wiring, and a direction orthogonal to the longitudinal direction. A recess having a width equal to the minimum processing dimension is provided so as to overlap with the contact hole, and a bottom surface of the recess is provided at a position higher than an upper surface of the lower wiring; Hole arrangement The recess is filled with a contact plug including at least a tungsten film, and at least the bottom of the contact hole in the contact plug directly connected to the lower wiring and the bottom of the recess in the contact plug are formed of a barrier. A semiconductor device comprising a conductor film, wherein the upper wiring further includes an aluminum alloy film having at least a required thickness. 9. A second barrier conductor film having a second required thickness is provided between the bottom surface of the aluminum alloy film and the interlayer insulating film, and further comprises a second barrier conductor film. A body film is directly connected to an upper end of the contact plug, and an upper surface of the aluminum alloy film is directly covered by a third barrier conductor film having a third required thickness. 9. The semiconductor device according to claim 8, wherein: 10. The semiconductor device according to claim 8, wherein an upper end of said contact plug substantially coincides with an upper surface of said interlayer insulating film. 11. A lower wiring on a surface of a semiconductor substrate or on a surface of the semiconductor substrate, covering the lower wiring, forming an interlayer insulating film having a flat upper surface, and having a diameter equal to a minimum processing dimension. Forming a contact hole reaching the entire surface of the interlayer insulating film; forming a first barrier conductor film on the entire surface; forming a tungsten film on the entire surface by vapor phase growth;
The contact plug formed of the tungsten film and the first barrier conductor film filling the contact hole by removing the tungsten film and the first barrier conductor film covering the upper surface of the interlayer insulating film by the P) method. Forming an aluminum film in a self-aligned manner on the upper end of the contact plug by vapor phase epitaxy, forming an aluminum alloy film of a first required thickness on the entire surface by sputtering,
Forming a second barrier conductor film of a second required thickness on the entire surface; and patterning a laminated conductor film comprising at least the second barrier conductor film and an aluminum alloy film by anisotropic etching Forming an upper wiring comprising the aluminum film and a pattern of the laminated conductor film having a minimum line width and a minimum interval equal to a minimum processing dimension. Method. 12. The method according to claim 11, wherein the anisotropic etching for patterning the laminated conductor film including the second barrier conductor film and the aluminum alloy film is ECR plasma etching. A method for manufacturing a semiconductor device. 13. An element excluding aluminum constituting said aluminum alloy film or said element in anisotropic etching for patterning a laminated conductor film comprising said second barrier conductor film and an aluminum alloy film. 13. The method of manufacturing a semiconductor device according to claim 11, wherein said compound is monitored to suppress etching of said aluminum film in said anisotropic etching. 14. A lower wiring layer is formed on the surface of the semiconductor substrate or on the surface thereof, the lower wiring layer is formed to cover the lower wiring layer, and an interlayer insulating film having a flat upper surface is formed. Forming a contact hole reaching the first interlayer insulating film by sputtering, forming a first barrier conductor film over the entire surface by sputtering, and forming a tungsten film over the entire surface by vapor deposition.
The contact plug made of the tungsten film and the first barrier conductor film filling the contact hole is formed by removing the tungsten film and the first barrier conductor film covering the upper surface of the interlayer insulating film by a CMP method. Forming a second barrier conductor film having a first required thickness on the entire surface, forming an aluminum alloy film having a second required thickness on the entire surface by sputtering, and forming a third barrier conductive film on the entire surface. Third of required film thickness
Forming a barrier conductor film, further forming an insulating film over the entire surface by vapor phase epitaxy, patterning the insulating film by anisotropic etching,
Further, the laminated conductor film including the third barrier conductor film, the aluminum alloy film, and the second barrier conductor film is patterned by anisotropic etching, and a minimum line width and a minimum interval equal to the minimum processing size are determined. Forming a pattern made of the laminated conductor film having an opening portion just above the upper end of the contact plug and in the vicinity of the upper end, and including the pattern made of the laminated conductor film, Forming a photo-resist film covering the upper surface of the contact plug, and performing a chemical vapor deposition method using the photo-resist film as a mask. Forming an aluminum film on the side surface in a self-aligned manner, and forming an upper layer wiring composed of the aluminum film and a pattern of the laminated conductor film. A method of manufacturing a semiconductor device. 15. The method according to claim 14, wherein the sputtering method for forming the first barrier conductor film is a collimation sputtering method. 16. The method according to claim 16, wherein the source gas in the chemical vapor deposition of the aluminum film is trimethyl aluminum (A
16. The semiconductor device according to claim 14, comprising a vaporized gas of l (CH ₃ ) ₃ ) or a vaporized gas of ヂ · methyl aluminum hydride (Al · H (CH ₃ ) ₂ ). Production method. 17. An interlayer insulating film formed on a surface of a semiconductor substrate or on a surface thereof, covering the lower layer wiring, having a flat upper surface, forming an interlayer insulating film made of a silicon oxide film, and forming an upper surface of the interlayer insulating film. Forming a contact hole having a diameter equal to the minimum processing dimension, penetrating the silicon nitride film and the interlayer insulating film, and reaching the lower wiring; and forming a contact hole on the entire surface by sputtering. 1 titanium nitride film is formed,
A tungsten film is formed on the entire surface by vapor phase epitaxy, and CM
Forming a contact plug made of the tungsten film and the first titanium nitride film filling the contact hole by removing the tungsten film and the first titanium nitride film covering the upper surface of the silicon nitride film by a P method; Forming a second titanium nitride film of a first required thickness on the entire surface, forming an aluminum alloy film of a second required thickness on the entire surface by sputtering, and forming a third required film on the entire surface Forming a thick titanium / tungsten film and further forming a first silicon oxide film on the entire surface by vapor phase epitaxy; and patterning the first silicon oxide film by anisotropic etching to form a silicon oxide film cap. Is formed, and the laminated conductor film including the titanium / tungsten film, the aluminum alloy film, and the second titanium nitride film is patterned by anisotropic etching. Forming a pattern made of the laminated conductor film having a minimum line width and a minimum interval equal to the minimum processing size; forming a second silicon oxide film on the entire surface; Forming a silicon oxide film spacer covering the side surface of the pattern made of the laminated conductive film by etching back the silicon film; and having an opening just above the contact plug and in the vicinity of the upper end of the contact plug. Forming a photo-resist film covering the upper surface of the interlayer insulating film including the pattern made of the laminated conductive film, and etching the silicon oxide film cap and silicon oxide by etching with a buffered hydrofluoric acid solution using the photo-resist film as a mask; Removing the film spacer and the titanium / tungsten film; removing the photo-resist film; and performing chemical vapor deposition on the contact plug. Forming an aluminum film in self-alignment with the side surface of the second titanium nitride film and the side surface and the upper surface of the aluminum alloy film just above and near the upper end of the aluminum film. Forming an upper layer wiring composed of a pattern having the following pattern: 18. The method according to claim 17, wherein the sputtering method for forming the first titanium nitride film is a collimation sputtering method. 19. A source gas in the chemical vapor deposition method of the aluminum film is a gaseous gas of trimethyl aluminum, a gaseous gas of メ チ ル · methyl aluminum hydride or a gaseous tri-iso-butyl aluminum (A
19. The method of manufacturing a semiconductor device according to claim 17, comprising a vaporized gas of 1 (CH ₂ .CH (CH ₃ ) ₂ ) ₃ ). 20. A surface of a semiconductor substrate or a lower wiring provided on the surface of the semiconductor substrate is covered with an interlayer insulating film having a flat upper surface, and has a minimum line width and a minimum interval equal to a minimum processing dimension. The upper wiring provided on the upper surface of the interlayer insulating film is connected to the lower wiring via a contact hole having a diameter equal to the minimum processing dimension provided in the interlayer insulating film and reaching the lower wiring. A method of manufacturing a semiconductor device, comprising: forming the lower wiring on a surface or on the surface of the semiconductor substrate; forming an interlayer insulating film having a flat upper surface so as to cover the lower wiring; On the surface of the interlayer insulating film in a region overlapping with a region where the upper end of the contact hole is to be formed on the surface of the film, a length longer than a minimum processing dimension in a longitudinal direction in which the upper layer wiring is to be formed. , Forming a recess having a width equal to the minimum processing dimension in a direction perpendicular to the hand direction and further having a bottom at a position higher than the upper surface of the lower wiring; and penetrating at least a part of the bottom of the recess, Forming a contact hole having a diameter equal to a processing dimension and reaching the lower wiring in the interlayer insulating film; forming a first barrier conductor film on the entire surface by sputtering; Forming a tungsten film,
The contact hole and the concave portion are filled by removing the tungsten film and the first barrier conductor film covering the upper surface of the interlayer insulating film by a CMP method, and the contact comprising the tungsten film and the first barrier conductor film is removed. A step of forming a plug; forming a second barrier conductor film of a first required thickness on the entire surface; forming an aluminum alloy film of a second required thickness on the entire surface by sputtering; To the third required film thickness
A third barrier conductor film,
Patterning a laminated conductor film made of an aluminum alloy film and a second barrier conductor film by anisotropic etching to form the upper layer wiring. 21. The method according to claim 20, wherein the sputtering method for forming the first barrier conductor film is a collimation sputtering method.