JPH10242220A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH10242220A JPH10242220A JP4402997A JP4402997A JPH10242220A JP H10242220 A JPH10242220 A JP H10242220A JP 4402997 A JP4402997 A JP 4402997A JP 4402997 A JP4402997 A JP 4402997A JP H10242220 A JPH10242220 A JP H10242220A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor device
- bumps
- lead
- plating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特に金(Au)バンプ電極に対し、リードを接合する半
導体装置に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device for joining a lead to a gold (Au) bump electrode.
【0002】[0002]
【従来の技術】従来、半導体装置の電極にリードを接合
する工程の自動化が進められ、適当な搬送テープに貼付
されたリードの端部と、半導体基板上に形成されたAu
バンプ電極とを接合する方式、いわゆるテープキャリア
(TCP)方式が広く採用されている。2. Description of the Related Art Conventionally, automation of a process of bonding a lead to an electrode of a semiconductor device has been advanced, and an end portion of the lead attached to an appropriate carrier tape and an Au formed on a semiconductor substrate have been developed.
A method of bonding with a bump electrode, a so-called tape carrier (TCP) method, has been widely adopted.
【0003】図3は従来の一例を説明するための半導体
装置の断面図である。図3に示すように、従来の半導体
装置は、半導体基板1上に被着したAuバンプ2と、銅
(Cu)材の表面に錫(Sn)めっき層5を施したCu
リード部4とを備え、このAuバンプ2にCuリード部
4を接合している。FIG. 3 is a cross-sectional view of a semiconductor device for explaining an example of the related art. As shown in FIG. 3, a conventional semiconductor device includes an Au bump 2 attached on a semiconductor substrate 1 and a Cu (Cu) material in which a tin (Sn) plating layer 5 is formed on a surface of a copper (Cu) material.
The Cu bump 4 is joined to the Au bump 2.
【0004】かかるAuバンプ2とCuリード部4を接
合するには、Snめっきを施したCuリード部4をAu
バンプ2に溶着する方法が主に使用されているが、この
ような金属の組合わせでは、リード部4のSnメッキ層
5とAuバンプ2により、接触部(つまり、接点)Au
−Sn合金を形成して接合している。In order to join the Au bump 2 and the Cu lead 4, the Sn-plated Cu lead 4 must be
A method of welding to the bumps 2 is mainly used. In such a combination of metals, a contact portion (that is, a contact) Au is formed by the Sn plating layer 5 of the lead portion 4 and the Au bump 2.
-An Sn alloy is formed and joined.
【0005】しかし、このような金属、Au−Snの溶
けが悪く、リード部4の不着の大きな要因となってい
る。[0005] However, the melting of such a metal and Au-Sn is poor, which is a major cause of the non-adhesion of the lead portion 4.
【0006】また、Auバンプ2,Snメッキリード部
4と、Au−Sn合金とは、濡れ性が悪く、これも両者
の不着の不着の要因となっている。Further, the Au bumps 2, the Sn plating lead portions 4, and the Au—Sn alloy have poor wettability, which is also a factor of non-adhesion of the two.
【0007】[0007]
【発明が解決しようとする課題】上述した従来の半導体
装置は、リード部とバンプの熱圧着時のAu−Snの溶
け不足によリ、リード不着を発生するという欠点があ
る。The above-described conventional semiconductor device has a disadvantage that lead non-adhesion occurs due to insufficient melting of Au-Sn at the time of thermocompression bonding of a lead portion and a bump.
【0008】また、従来の半導体装置は、リードがSn
めっきしているのに対し、バンプはSnめっきしていな
いため、Au−Sn合金の濡れ不足が生じ、このために
リードそのものの不着率が高くなるという欠点がある。In the conventional semiconductor device, the lead is Sn
In contrast to the plating, the bumps are not Sn-plated, so that the Au—Sn alloy is insufficiently wetted, resulting in a high non-adhesion rate of the lead itself.
【0009】本発明の目的は、かかるバンプとリード部
の不着を低減するとともに、生産性および信頼性を向上
させることのできる半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device capable of reducing the non-adhesion between the bump and the lead portion and improving the productivity and reliability.
【0010】[0010]
【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に被着するとともに、上面にSnめっき層
を形成したAuバンプと、表面にSnめっき層を形成し
たリード部とを有し、前記Auバンプに前記リード部を
熱圧着により接合する際、両者の接触部およびその近傍
にAu−Sn共晶を形成するように構成される。According to the present invention, there is provided a semiconductor device comprising:
When having an Au bump having an Sn plating layer formed on the upper surface and a lead portion having an Sn plating layer formed on the surface while being attached on the semiconductor substrate, and bonding the lead portion to the Au bump by thermocompression bonding , And an Au-Sn eutectic is formed at the contact portion between them and the vicinity thereof.
【0011】また、本発明の半導体装置における前記A
uバンプは、露出している表面全体にSnめっき層を形
成するように構成される。In the semiconductor device of the present invention, the A
The u bump is configured to form a Sn plating layer over the entire exposed surface.
【0012】[0012]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【0013】図1(a),(b)はそれぞれ本発明の一
実施の形態を説明するための半導体装置のリードとバン
プの接合前後の断面図である。まず、図1(a)に示す
ように、本実施の形態の半導体装置は、Auバンプ2と
Cuリード部4とを有し、両者の接合前においては、半
導体基板1上に被着されたAuバンプ2が上面にSnめ
っき層3を形成しており、一方Cuリード部4が表面に
Snめっき層5を形成している。ここで、Snめっき層
3は、Auバンプ2の上面にのみ形成しているが、バン
プ2の側面を絶縁膜などで被覆してめっきを施せばよ
い。FIGS. 1A and 1B are cross-sectional views of a semiconductor device before and after joining a lead and a bump, respectively, for explaining an embodiment of the present invention. First, as shown in FIG. 1A, the semiconductor device of the present embodiment has an Au bump 2 and a Cu lead portion 4 and is attached on the semiconductor substrate 1 before joining the two. The Au bump 2 forms the Sn plating layer 3 on the upper surface, while the Cu lead portion 4 forms the Sn plating layer 5 on the surface. Here, the Sn plating layer 3 is formed only on the upper surface of the Au bump 2, but the side surface of the bump 2 may be covered with an insulating film or the like and plated.
【0014】ついで、図1(b)に示すように、Auバ
ンプ2にCuリード部4を熱圧着により接合する際、両
者の接触部にAu−Sn共晶6を形成する。またこのA
u−Sn共晶6は、両者の接触部に加えて、その近傍周
囲にまで形成される。このとき、Cuリード部4のSn
めっき層5において、Au−Sn共晶6にならない部
分、すなわち上側部分は、熱圧着の際の熱により一時的
に溶融し、その後冷却して固着する。Next, as shown in FIG. 1 (b), when the Cu lead portion 4 is bonded to the Au bump 2 by thermocompression bonding, an Au-Sn eutectic 6 is formed at the contact portion between the two. This A
The u-Sn eutectic 6 is formed not only at the contact portion between the two but also around the vicinity thereof. At this time, the Sn of the Cu lead 4
In the plating layer 5, a portion that does not become the Au-Sn eutectic 6, that is, an upper portion is temporarily melted by heat at the time of thermocompression bonding, and then cooled and fixed.
【0015】このように、Cuリード部4とAuバンプ
2をAu−Sn共晶6により融着すると、それぞれの表
面に低融点金属であるSnをめっきしているため、融着
しやすくなるとともに、Au−Snの流れを良くするこ
とができるので、濡れ性を向上させることができる。As described above, when the Cu lead portion 4 and the Au bump 2 are fused by the Au-Sn eutectic 6, the respective surfaces are plated with Sn, which is a low-melting metal, so that the fusion is facilitated. , Au—Sn can be improved, and the wettability can be improved.
【0016】図2は本発明の他の実施の形態を説明する
ための半導体装置のバンプ側の断面図である。図2に示
すように、本実施の形態は、半導体装置におけるAuバ
ンプ2が、上面だけでなく側面を含む露出している表面
全体にSnめっき層3を形成したものである。この場合
は、バンプ2の側面を絶縁膜で被覆せずにSnめっきを
施せば良い。FIG. 2 is a sectional view on the bump side of a semiconductor device for explaining another embodiment of the present invention. As shown in FIG. 2, in the present embodiment, the Au plating 2 in the semiconductor device has the Sn plating layer 3 formed on the entire exposed surface including the side surface as well as the upper surface. In this case, Sn plating may be applied without covering the side surface of the bump 2 with the insulating film.
【0017】これにより、Auバンプ2の側面にもAu
−Sn共晶が流れ易くなり、リード部の剥し強度がさら
に増大する。As a result, the Au bumps 2 are also formed on the side surfaces of the Au bumps 2.
-Sn eutectic flows more easily, and the peel strength of the lead portion further increases.
【0018】[0018]
【発明の効果】以上説明したように、本発明の半導体装
置は、AuバンプおよびCuリード部の表面にそれぞれ
Snめっき層を形成することにより、Au−Snの流れ
が良くなるので、AuバンプにCuリード部を熱圧着し
たときの半田濡れ性を良くすることができ、両者の不着
を低減することができるという効果がある。As described above, in the semiconductor device of the present invention, the Au-Sn flow is improved by forming the Sn plating layers on the surfaces of the Au bumps and the Cu lead portions, respectively. It is possible to improve the solder wettability when the Cu lead portion is thermocompression-bonded, and it is possible to reduce non-adhesion between the two.
【0019】また、本発明の半導体装置は、Au−Sn
の流れ不足による接続不良が減るため、生産性および信
頼性を向上させることができるという効果がある。Further, the semiconductor device according to the present invention is preferably composed of Au-Sn
This reduces the number of connection failures due to the shortage of flow, thereby improving productivity and reliability.
【図1】本発明の一実施の形態を説明するための半導体
装置のリードとバンプの接合前後の断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention before and after bonding a lead and a bump.
【図2】本発明の他の実施の形態を説明するための半導
体装置のバンプ側の断面図である。FIG. 2 is a sectional view on a bump side of a semiconductor device for explaining another embodiment of the present invention;
【図3】従来の一例を説明するためのリード,バンプ接
合前の半導体装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device before bonding leads and bumps for explaining an example of the related art.
1 半導体基板 2 Auバンプ 3 Snめっき層 4 Cuリード部 5 Snめっき層 6 Au−Sn共晶 Reference Signs List 1 semiconductor substrate 2 Au bump 3 Sn plating layer 4 Cu lead portion 5 Sn plating layer 6 Au-Sn eutectic
Claims (2)
にSnめっき層を形成したAuバンプと、表面にSnめ
っき層を形成したリード部とを有し、前記Auバンプに
前記リード部を熱圧着により接合する際、両者の接触部
およびその近傍にAu−Sn共晶を形成することを特徴
とする半導体装置。An Au bump having an Sn plating layer formed on an upper surface thereof and a lead having an Sn plating layer formed on a surface thereof, wherein the Au bump has a lead portion formed thereon. A semiconductor device, wherein an Au-Sn eutectic is formed at a contact portion between the two and at the vicinity thereof when joining by crimping.
体にSnめっき層を形成した請求項1記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the Au bump has an Sn plating layer formed on the entire exposed surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4402997A JP2848373B2 (en) | 1997-02-27 | 1997-02-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4402997A JP2848373B2 (en) | 1997-02-27 | 1997-02-27 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10242220A true JPH10242220A (en) | 1998-09-11 |
JP2848373B2 JP2848373B2 (en) | 1999-01-20 |
Family
ID=12680225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4402997A Expired - Fee Related JP2848373B2 (en) | 1997-02-27 | 1997-02-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2848373B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008078240A (en) * | 2006-09-19 | 2008-04-03 | Toyota Motor Corp | Method for connecting wiring for semiconductor element and semiconductor device |
-
1997
- 1997-02-27 JP JP4402997A patent/JP2848373B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008078240A (en) * | 2006-09-19 | 2008-04-03 | Toyota Motor Corp | Method for connecting wiring for semiconductor element and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2848373B2 (en) | 1999-01-20 |
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