JPH10242145A - Multilayer wiring structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring structure which realizes a highly integrated semiconductor device having a small size chip, without causing the voltage drop or electromigration. SOLUTION: On a semiconductor substrate at least a lower and upper layer regions are formed through layer insulation film 15, 16, one of a power wiring 12 and ground wiring 14 is formed on the lower layer regions and the other is formed on the upper layer regions, thus forming a multilayer wiring structure. On either lower or upper layer regions an independent wiring 17 is formed in addition to the wiring formed there and has a continuity at its both sides with the wiring on the other regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure in a semiconductor device, and more particularly, to a multilayer wiring structure in which voltage drop and electromigration of a semiconductor device are suppressed.

[0002]

2. Description of the Related Art As semiconductor devices such as LSIs become more highly integrated, the width and spacing of wirings also tend to be reduced. Due to such a tendency, forming a single layer of wiring has become a limit.
A so-called multilayer wiring structure having three layers or the like has been adopted.

In such a multilayer wiring structure, for example, a three-layer structure, as shown in FIG. 3A, a power supply wiring 2 is provided on a first layer, a signal wiring 3 is provided on a second layer, and a third layer is provided on a substrate 1. And the ground wiring 4 is formed and arranged. Here, interlayer insulating films 5 and 6 are formed between the wirings 2, 3, and 4, so that the wirings 2, 3, and 4 do not conduct with each other, and do not affect each other. It has become. In addition, these wirings 2, 3, and 4 are usually arranged in parallel in a plan view as shown in FIG. 3B for convenience of layout design of the semiconductor device.

[0004]

In recent years, since higher integration has been demanded in semiconductor devices, the width and spacing of wirings have been increasingly narrowed. . As a result, if the wiring is narrowed, a voltage drop or electromigration occurs in the semiconductor device.
On the other hand, in order to prevent a voltage drop or electromigration, it is necessary to enlarge the wiring, but in this case, simply enlarging the wiring area naturally impairs the high integration of the semiconductor device. .

The present invention has been made in view of the above circumstances, and an object of the present invention is to enable high integration of a semiconductor device, that is, downsizing of a chip size without causing a voltage drop or electromigration. An object of the present invention is to provide a multilayer wiring structure.

[0006]

In a multi-layer wiring structure in a semiconductor device, for example, when a power supply wiring is formed in a lower layer region and a ground wiring is formed in an upper layer region, a position immediately below the ground wiring is usually set in the lower layer region. In the upper layer area, the position immediately above the power supply wiring is an unused area.

Therefore, in the multilayer wiring structure of the present invention, at least the lower layer region and the upper layer region are formed on the semiconductor substrate via the interlayer insulating film, and one of the power supply wiring and the ground wiring is formed in the lower layer region. In a multi-layer wiring structure of a semiconductor device in which the other of a power supply wiring and a ground wiring is formed in an upper layer area, the wiring formed in one of the lower layer area and the upper layer area is different from the wiring formed in the area. Another means for solving the problem is that an independent independent wiring is formed, and the independent wiring is conducted on both sides of the independent wiring with a wiring formed on the other of the lower layer region and the upper layer region.

According to this multilayer wiring structure, an independent wiring is formed by utilizing the unused portion, and the independent wiring is made conductive with the wiring immediately above or below the independent wiring, thereby expanding the wiring area. Without this, the wiring, that is, the power supply wiring or the ground wiring has substantially the cross-sectional area obtained by adding the cross-sectional area of the independent wiring to the cross-sectional area of the wiring itself, and the resistance is reduced accordingly.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring structure according to the present invention will be described in detail. FIGS. 1, 2A and 2B are diagrams showing an embodiment of a multilayer wiring structure according to the present invention. In these drawings, reference numeral 10 denotes a multilayer wiring structure. This multilayer wiring structure 10 has a three-layer structure, and is formed on a substrate (base) 11 made of a wafer or the like on which various semiconductor device components (not shown) are formed as shown in FIG. It is. A power supply wiring 12 is formed in a first layer (lower region in the present invention) on the substrate 11, a signal wiring 13 is formed in a second layer, and a ground wiring 14 is formed in a third layer (upper region in the present invention). Are formed.

Interlayer insulating films 15 and 16 are formed between the wirings 12, 13 and 14. These interlayer insulating films 15,
Although not shown, through holes 16 are formed in the substrate 16 for conducting between the signal wiring 13 and the ground wiring 14 and a semiconductor device component (not shown) of the substrate 11. Also, these wirings 12, 13, 14 are:
Similar to the conventional device shown in FIG. 3B, the semiconductor devices are arranged in parallel in a plan view for the sake of layout design of the semiconductor device.

Further, in this multilayer wiring structure 10, FIG.
As shown in (a) and (b), the ground wiring 1 is provided on the third layer.
4, that is, an independent wiring 17 independent of the ground wiring 14 is formed. This independent wiring 17
The power supply wiring 12 is formed immediately above the power supply wiring 12 of the first layer and substantially in parallel with the power supply wiring 12.
Is conducted.

That is, between the independent wiring 17 and the power supply wiring 12, a through hole 18 is formed in the interlayer insulating film 15 and a wiring material 19 is buried therein. An island-shaped connecting conductive portion 20 is formed in (ie, the second layer), and a through hole 21 is formed in the interlayer insulating film 16, and a wiring material 22 is buried therein. With such a configuration, the power supply wiring 12 and the independent wiring 17 are electrically connected to each other via the wiring material 19, the connecting conductive portion 20, and the wiring material 22, as shown in FIG. In addition,
Formation of through holes 18 and 21 and wiring materials 19 and 2
2 is simultaneously formed by the same process as the formation of the through holes for the signal wiring 13 and the ground wiring 14 and the filling. The formation of the connection conductive portion 20 is performed in the same process as the formation of the signal wiring 13.

In the multilayer wiring structure 10 having such a structure, the current flowing into the power supply wiring 12 flows between both ends of the independent wiring 17, that is, between the conductive parts of the power supply wiring 12 and the independent wiring 17. It flows to both 12 and independent wiring 17. Therefore, as shown in FIG. 1, when both the width of the power supply wiring 12 and the width of the independent wiring 17 are x μm, the width of the power supply wiring 12 is substantially 2 × μm between both ends of the independent wiring 17. . Therefore, assuming that the power supply wiring 12 and the independent wiring 17 have the same thickness, the power supply wiring 12 has a cross-sectional area substantially doubled, so that the wiring material 19 in the through hole 18, the connection conductive part 20, If the influence of the resistance of the wiring material 22 in the through hole 21 on the current density is ignored, the substantial resistance of the power supply wiring 12 is reduced to about ２.

Therefore, in the multilayer wiring structure 10, the substantial resistance of the power supply wiring 12 can be reduced without increasing the area of each of the first, second and third wiring areas as compared with the prior art. The voltage drop can be reduced by about 1 without hindering the miniaturization of the chip size of the semiconductor device.
/ 2. In addition, since the limit value of the electromigration can be approximately doubled, the occurrence of the electromigration can be suppressed.

In the above embodiment, the multilayer wiring structure of the present invention is applied to a three-layer structure. However, the present invention is not limited to this, and may have a two-layer structure or a structure having four or more layers. Of course, it can be applied to things. Also,
In the above-described embodiment, the power supply wiring 12 is formed in the first layer, the signal wiring 13 is formed in the second layer, and the ground wiring 14 is formed in the third layer. However, in what layer are these wirings 12, 13, and 14 formed? It can be changed as appropriate. Further, in the above embodiment,
The independent wiring 17 is connected to the power supply wiring 12, and the power supply wiring 12
The actual resistance was reduced, for example, as shown in FIG.
In FIG. 3A, an independent wiring (not shown) is formed in the first layer so as to be located immediately below the ground wiring 14, and is connected to the ground wiring 14 so that the substantial resistance of the ground wiring 14 is reduced. You may.

[0016]

As described above, according to the multilayer wiring structure of the present invention, an independent wiring is formed in one of the lower layer region and the upper layer region, independently of the wiring formed in that region. Is electrically connected to the wiring formed on the other of the lower layer region and the upper layer region on both sides thereof.For example, an independent wiring is formed in an unused portion of the lower layer region or the upper layer region, and By conducting with the wiring above or below, the lower layer area,
The substantial resistance of the wiring conducting to the independent wiring can be reduced without increasing the area of the wiring region in the upper layer region as compared with the related art. Therefore, in the multilayer wiring structure of the present invention, the voltage drop can be reduced without preventing the chip size of the semiconductor device from being reduced. Also,
As a result, the limit value of electromigration can be increased, so that occurrence of electromigration can be suppressed.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing a schematic configuration of an embodiment of a multilayer wiring structure according to the present invention.

FIGS. 2A and 2B are diagrams showing a schematic configuration of the multilayer wiring structure shown in FIG. 1, wherein FIG. 2A is a side sectional view and FIG.

3A and 3B are diagrams showing a schematic configuration of an example of a conventional multilayer wiring structure, where FIG. 3A is a side sectional view and FIG. 3B is a plan view.

[Explanation of symbols]

 Reference Signs List 10 multilayer wiring structure 12 power supply wiring 14 ground wiring 15, 16 interlayer insulating film 17 independent wiring

Claims (1)

[Claims] At least a lower region and an upper region are formed on a semiconductor substrate via an interlayer insulating film, and one of a power supply wiring and a ground wiring is formed in the lower layer region,
A multilayer wiring structure of a semiconductor device in which the other of a power supply wiring and a ground wiring is formed in an upper layer region, wherein one of the lower layer region and the upper layer region includes the wiring formed in the region. A multilayer wiring structure, wherein separate independent wiring is formed, and the independent wiring is electrically connected to the wiring formed on the other of the lower layer region and the upper layer region on both sides thereof.