JPH10239384A - Package for failure analysis of semiconductor integrated circuit device and its analyzing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable analyzing a semiconductor integrated circuit device from the circuit surface side and analyzing the device from the surface side opposite to the circuit surface, without mounting again the semiconductor integrated circuit. SOLUTION: This package for failure analysis contains a semiconductor integrated circuit device 10, a package 20, a mounting surface which is formed in the package 20 and mounts the semiconductor integrated circuit device 10, and a through hole 25 which is formed in the mounting surface and exposes the main surface of the device 10. The through hole 25 exposes the circuit surface 11 and the opposite mounting surface 12 of the device 10. The through hole 25 has a dimension larger than or equal to that of a region to be analyzed in the circuit surface 11 of the device 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a package for analyzing a failure of a semiconductor integrated circuit device and a method of analyzing the package.
In particular, the present invention relates to a package for failure analysis of a semiconductor integrated circuit device, which can easily analyze the semiconductor integrated circuit device, and a method of analyzing the package.

[0001]

2. Description of the Related Art Conventionally, this type of semiconductor integrated circuit device has a semiconductor integrated circuit device mounted on a package in order to facilitate mounting of the semiconductor integrated circuit device on a wiring board and analysis of the semiconductor integrated circuit device. This is because it is difficult to apply an electric signal with a semiconductor integrated circuit device alone.

A pin grid array (PGA) package which is an example of a mounting structure of a conventional semiconductor integrated circuit device is disclosed in a book "Practical Course VLSI" published by Nikkei BP.
Packaging Technology (1) ", edited by Susumu Kayama and Kunihiko Naruse, p. 170.

Referring to FIG. 6, a PGA described in the above-mentioned document is described.
The package 2 includes a laminated plate 3 in which a ceramic layer and a wiring layer are laminated, and a plurality of pins 4 for electrical connection. A concave portion 5 is provided in the center of the laminated plate, and the semiconductor integrated circuit device 1 is bonded and mounted on the bottom of the concave portion 5.

[0004]

A transistor on the circuit surface of a semiconductor integrated circuit device generates a small amount of light when a leak failure occurs. Since a silicon substrate used in a semiconductor integrated circuit device transmits infrared light having a wavelength of 1 μm or more, light generated on a circuit surface of the semiconductor integrated circuit device passes through the semiconductor integrated circuit device and reaches a mounting surface. The transistor of the semiconductor integrated circuit device can be analyzed by detecting this weak light from the side opposite to the circuit surface of the semiconductor integrated circuit device with an emission microscope.

However, according to the above-mentioned prior art, even if an attempt is made to perform light emission analysis from a surface opposite to a circuit surface of the semiconductor integrated circuit device in a state where the semiconductor integrated circuit device is mounted on a package, the semiconductor integrated circuit device cannot be analyzed. The surface opposite to the circuit surface has a problem that light emitted from the circuit surface covered by the package is not transmitted. For this reason, there is a problem that the semiconductor integrated circuit device must be mounted again in order to perform light emission analysis with the emission microscope from the side opposite to the circuit surface of the semiconductor integrated circuit device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a package for failure analysis of a semiconductor integrated circuit device, which can perform both analysis from the circuit surface of the semiconductor integrated circuit device and analysis from the surface opposite to the circuit surface. More specifically, the analysis from the circuit surface side of the semiconductor integrated circuit device and the analysis from the surface side opposite to the circuit surface can be performed without remounting the semiconductor integrated circuit device.

[0007]

According to the present invention, there is provided a package for failure analysis of a semiconductor integrated circuit device, comprising: a semiconductor integrated circuit device, a mounting board, and the semiconductor integrated circuit mounted on the mounting board. And a through hole provided in the mounting board so as to expose a part of the lower surface of the circuit device to the outside.

In another aspect of the present invention, a peripheral portion of a lower surface of the semiconductor integrated circuit device and a peripheral portion of the through hole of the mounting substrate are fixed. And

Furthermore, another package for analyzing a failure of a semiconductor integrated circuit device according to the present invention includes an external connection terminal provided on a surface opposite to a surface of the mounting substrate on which the semiconductor integrated circuit device is mounted. Including.

[0010] A failure analysis package for another semiconductor integrated circuit device according to the present invention includes an external connection terminal provided on the same surface as the surface of the mounting substrate on which the semiconductor integrated circuit device is mounted. .

Further, in another package for analyzing a failure of a semiconductor integrated circuit device according to the present invention, the through hole has a size larger than or equal to a size of a region to be analyzed on a circuit surface of the semiconductor integrated circuit device. It is characterized by the following.

Further, another package for failure analysis of a semiconductor integrated circuit device according to the present invention includes a semiconductor integrated circuit device, a mounting substrate on which the semiconductor integrated circuit device is mounted, and the semiconductor integrated circuit provided on the mounting substrate. The semiconductor integrated circuit device includes a recess for accommodating the device, and a through hole provided in the recess to expose a lower surface of the semiconductor integrated circuit device.

A method for analyzing a semiconductor integrated circuit device according to the present invention is a method for analyzing a semiconductor integrated circuit device in which a semiconductor integrated circuit device is mounted on a mounting substrate having a through hole exposing a lower surface of the semiconductor integrated circuit device and analyzed. And analyzing the lower surface of the semiconductor integrated circuit device exposed from the through hole with an emission microscope.

According to another method for analyzing a semiconductor integrated circuit device of the present invention, the semiconductor integrated circuit device is mounted on a mounting substrate having a through hole exposing a lower surface of the semiconductor integrated circuit device, and analysis is performed. An analysis method of the device,
Analyzing the lower surface of the semiconductor integrated circuit device exposed from the through-hole with an emission microscope, and irradiating the circuit surface of the semiconductor integrated circuit device with an electron beam for analysis. A method for analyzing a semiconductor integrated circuit device, comprising:

Further, another failure analysis package for a semiconductor integrated circuit device according to the present invention is provided with a through hole for exposing a part of the lower surface of the semiconductor integrated circuit device to the outside when the semiconductor integrated circuit device is mounted. Including mounting boards.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a package for failure analysis of a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a first embodiment of a package for failure analysis of a semiconductor integrated circuit device according to the present invention is as follows.
A concave portion 24 is provided in the package 20, and a through hole 25 is provided inside the concave portion 24. The semiconductor integrated circuit device 10 is mounted on the package 20.

The semiconductor integrated circuit device 10 has a circuit surface 11 and a mounting surface 12.
Implemented in

The package 20 includes an insulating layer 21 and a wiring layer 2.
2 are laminated. The wiring layer 22 forms a wiring inside the package. The material of the insulating layer 21 is preferably ceramic. This is because when the package 20 on which the semiconductor integrated circuit device 10 is mounted is analyzed by an electron beam (EB) tester described later, no gas is generated when the package 20 is placed in a vacuum state. The material of the wiring layer 22 is preferably nickel, copper, aluminum, gold, or the like. This is because the electric conduction characteristics are good.

A plurality of pins 23 are provided on the lower surface of the package 20.
Has been planted. The pins 23 are electrically connected to the wiring layer 21 inside the package.

The input / output terminals of the semiconductor integrated circuit device 10 and the wiring layer 22 of the package 20 are connected to bonding wires 24
Connected by

Referring to FIGS. 1 and 2, a package 20 has a recess 24 in which the semiconductor integrated circuit device 10 is housed.
Is provided. The recess 24 is provided with a through hole 25. The through-hole 25 exposes the mounting surface 12 of the semiconductor integrated circuit device 10.

The through hole 25 has a size larger than or equal to the size of the region to be analyzed on the circuit surface 11 of the semiconductor integrated circuit device 10. More specifically, the through hole 2
5 exposes a region on the mounting surface 12 opposite to the region to be analyzed on the circuit surface 11. The analyzed area is an area including a logic circuit to be analyzed.

The semiconductor integrated circuit device 10 is mounted on a package 20 around the mounting surface 12. The peripheral portion of the mounting surface 12 and the peripheral portion of the through hole 25 of the package 20 are bonded with a resin adhesive.

No shield member such as a cover or a cap is provided above the circuit surface 11 of the semiconductor integrated circuit device 10, and the circuit surface 11 is left exposed.

Next, an embodiment of a failure analysis package for a semiconductor integrated circuit device according to the present invention will be described with reference to the drawings.

Referring to FIG. 1, a package 20 is formed by laminating a green sheet on which a wiring pattern to be a wiring layer 22 is printed as an insulating layer 21. The thickness of the green sheet is 200 micrometers, and a wiring pattern is printed thereon. Wiring thickness 100
Micrometer nickel is plated with copper with a thickness of 10 micrometers. A via is provided in the green sheet to electrically connect each wiring. In the present embodiment, the package 20 is formed by laminating and sintering four layers of green sheets provided with wiring.

The outer shape of the semiconductor integrated circuit device 10 is 15 mm square. The package 20 is provided with a 17 mm square recess 24 for accommodating the semiconductor integrated circuit device 10. A 13 mm square through hole 25 is provided at the center of the recess 24. The through hole 25 penetrates to the back surface of the package 20.

A pin 23 having a length of 6 mm and a diameter of 0.5 mm is provided on the back surface of the package. The material of the pin is copper, and the surface is plated with gold.

Next, a method of analyzing a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the drawings.

An electron beam (hereinafter, referred to as EB) tester is used when a failure occurs in a semiconductor integrated circuit device or when a time series change of an electric signal in the semiconductor integrated circuit device is examined.

Referring to FIG. 3, an EB tester 100 includes a vacuum pump 101, an electron gun 102, and an electron lens 103.
, A secondary electron detector 104, a waveform observation device 105,
And a tester 106. The tester 106 and the signal pins and the power pins of the package 20 on which the semiconductor integrated circuit device 10 is mounted are connected by signal lines 107 and power lines 108, respectively.

A signal provided from the tester 106 via the signal line 107 is input to a signal pin of the package 20 and applied to the semiconductor integrated circuit device 10 via a wiring inside the package 20. The voltage of the wiring inside the semiconductor integrated circuit device 10 changes according to the applied signal.

The vacuum pump 101 maintains the measurement environment of the semiconductor integrated circuit device 10 mounted on the package 20 in a vacuum. In this state, the electron beam is emitted from the electron gun 102 to the semiconductor integrated circuit device 10. Semiconductor integrated circuit device 10
The secondary electrons emitted from are detected by the secondary electron detector 104, and the waveform is observed by the waveform observation device 105. The semiconductor integrated circuit device 10 is analyzed using this waveform.

Next, light emission analysis by the emission microscope from the mounting surface side of the semiconductor integrated circuit device 10 will be described. The light emission analysis by the emission microscope can detect a defect of the transistor of the semiconductor integrated circuit device 10.

When a transistor in the semiconductor integrated circuit device 10 has a leak failure, a small amount of light is generated. Since the silicon substrate used in the semiconductor integrated circuit device 10 transmits infrared light having a wavelength of 1 micrometer or more, light emitted on the circuit surface of the semiconductor integrated circuit device 10 passes through the semiconductor integrated circuit device 10 and reaches the mounting surface. I do. The weak light is detected from the surface opposite to the circuit surface of the semiconductor integrated circuit device 10 by the emission microscope.

Referring to FIG. 4, the microscope 201 and the surface opposite to the circuit surface of the semiconductor integrated circuit device 10 exposed from the through hole 25 of the package 20 are arranged so as to face each other. A signal is supplied from a power supply 203 or a signal control device 204 to pins of the package 20 on which the semiconductor integrated circuit device 10 is mounted. At this time, the semiconductor integrated circuit device 1
If there is a leak point in the 0 transistor, weak light emission occurs.

Light emitted from the circuit surface of the semiconductor integrated circuit device 10 is magnified by a microscope 201 and cooled by a cooled CCD camera 20.
2 is incident. The cooled CCD camera 202 is cooled to -40 ° C. The cooled CCD camera 202 observes weak light emission by accumulating weak light.

As described above, in the present embodiment, since the through hole 25 for exposing the surface opposite to the circuit surface of the semiconductor integrated circuit device 10 is provided in the package 20, light emission analysis of the semiconductor integrated circuit device 10 can be performed by the emission microscope. In this case, it is not necessary to remount the semiconductor integrated circuit device 10 in another package, and the analysis can be performed while the semiconductor integrated circuit device 10 is mounted in the package 20.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. The feature of the second embodiment resides in that solder balls are provided on the lower surface of the package.

Referring to FIG. 5, a solder ball 26 is provided on the lower surface of the package 20. The solder balls are connected to wiring inside the package 20. Package 2
The material of the insulating layer 27 constituting 0 is an organic resin. More specifically, the material of the insulating layer 27 is an epoxy resin.
Other configurations are the same as in the first embodiment.

In the above-described embodiment, an example of the cavity-up structure in which the surface where the opening of the package is provided and the surface where the pins for external connection and the solder balls are connected are different from each other has been described. A cavity-down structure in which the surface on which the portion is provided and the surface to which pins for external connection or solder balls are connected may be the same.

[0043]

As is apparent from the above description, according to the present invention, a through hole for exposing a surface opposite to the circuit surface of the semiconductor integrated circuit device is provided in the package, so that the semiconductor integrated circuit device is viewed from the circuit surface side. There is an effect that the analysis and the analysis from the side opposite to the circuit surface can be performed without mounting the semiconductor integrated circuit device again.

[Brief description of the drawings]

FIG. 1 is a perspective view of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an analysis method using an EB tester according to the present invention.

FIG. 4 is a diagram showing an analysis method using an emission microscope of the present invention.

FIG. 5 is a sectional view of a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional PGA package.

[Explanation of symbols]

 Reference Signs List 10 semiconductor integrated circuit device 20 package 21 insulating layer 22 wiring layer 23 pin 24 recess 25 through hole 26 bonding wire 27 solder ball 28 insulating layer 100 EB tester 101 vacuum pump 102 electron gun 103 electron lens 104 secondary electron detector 105 waveform observation Device 106 Tester 201 Microscope 202 Cooled CCD camera 203 Power supply 204 Signal control device

Claims (9)

[Claims] 1. A semiconductor integrated circuit device, comprising: a mounting substrate; and a through hole provided in the mounting substrate to expose a part of a lower surface of the semiconductor integrated circuit device mounted on the mounting substrate to the outside. A package for analyzing a failure of a semiconductor integrated circuit device, characterized in that: 2. A package for analyzing a failure of a semiconductor integrated circuit device according to claim 1, wherein a peripheral portion of a lower surface of said semiconductor integrated circuit device and a peripheral portion of said through hole of said mounting substrate are fixed. . 3. The semiconductor integrated circuit device according to claim 1, further comprising an external connection terminal provided on a surface opposite to a surface of said mounting substrate on which said semiconductor integrated circuit device is mounted. Package for failure analysis. 4. The failure of the semiconductor integrated circuit device according to claim 1, further comprising an external connection terminal provided on a surface on the same side as a surface of the mounting substrate on which the semiconductor integrated circuit device is mounted. Analysis package. 5. The semiconductor integrated circuit device according to claim 1, wherein said through hole has a size larger than or equal to a size of a region to be analyzed on a circuit surface of said semiconductor integrated circuit device. Analysis package. 6. A semiconductor integrated circuit device, a mounting substrate on which the semiconductor integrated circuit device is mounted, a concave portion provided on the mounting substrate for housing the semiconductor integrated circuit device, and a semiconductor integrated circuit provided in the concave portion. A through hole for exposing a lower surface of the device; and a failure analysis package for the semiconductor integrated circuit device. 7. An analysis method for a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is mounted on a mounting substrate having a through hole exposing a lower surface of the semiconductor integrated circuit device, and the analysis is performed. An analysis method for a semiconductor integrated circuit device, wherein the lower surface of the semiconductor integrated circuit device is analyzed by an emission microscope. 8. A method for analyzing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is mounted on a mounting substrate having a through hole exposing a lower surface of the semiconductor integrated circuit device and analysis is performed, the method comprising: A semiconductor integrated circuit device comprising: a step of performing analysis by an emission microscope on a lower surface of the semiconductor integrated circuit device; and a step of irradiating an electron beam on a circuit surface of the semiconductor integrated circuit device to perform analysis. Analysis method. 9. A failure of the semiconductor integrated circuit device, comprising a mounting substrate provided with a through hole for exposing a part of a lower surface of the semiconductor integrated circuit device to the outside when the semiconductor integrated circuit device is mounted. Analysis package.