JP2973646B2 - Mounting structure of bare chip LSI - Google Patents
Mounting structure of bare chip LSIInfo
- Publication number
- JP2973646B2 JP2973646B2 JP3266596A JP26659691A JP2973646B2 JP 2973646 B2 JP2973646 B2 JP 2973646B2 JP 3266596 A JP3266596 A JP 3266596A JP 26659691 A JP26659691 A JP 26659691A JP 2973646 B2 JP2973646 B2 JP 2973646B2
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- chip lsi
- circuit
- conductor
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Combinations Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多層構成された回路基
板の内部にベアチップＬＳＩを密封実装させるベアチッ
プＬＳＩの実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bare chip LSI mounting structure for sealingly mounting a bare chip LSI inside a multilayer circuit board.
【０００２】最近、ＬＳＩ（Large Scale Integrated C
ircuit）の高速化、高発熱化、などに対応させる高密度
実装構造（これを実現させるための回路基板技術、封止
技術、放熱技術、などの合成による）の検討が進められ
ており、簡易な構成で要求される特性を満足するととも
に、コストパフォーマンスに優れたベアチップＬＳＩの
実装技術を開発することが要望されている。Recently, LSI (Large Scale Integrated C)
The high-density mounting structure (circuit board technology, encapsulation technology, heat dissipation technology, etc. for realizing this) is being studied to respond to higher speeds and higher heat generation of ircuit). There is a demand to develop a bare chip LSI mounting technology that satisfies the characteristics required by a simple configuration and is excellent in cost performance.
【０００３】[0003]
【従来の技術】図２に、従来のベアチップＬＳＩの実装
構造を、図（ａ）に回路基板面上とした樹脂封止の断面
図、図（ｂ）に回路基板内部としてキャップ封止した断
面図、にそれぞれ示す。2. Description of the Related Art FIG. 2 is a cross-sectional view of a conventional bare chip LSI mounting structure with resin sealing on a circuit board surface, and FIG. The figure shows each.
【０００４】図（ａ）は、一般的なＣＯＢ（Chip on Bo
ard ）実装であり、ベアチップＬＳＩ９の底面を回路基
板１５の表面に位置決めして接着させ、ベアチップＬＳ
Ｉ９の表面の接続端子と回路基板１５表面の表面回路パ
ターン１２とをワイヤボンディングにより回路接続し、
これらの表面を覆うようにして回路基板１５上に電気的
絶縁性を有する封止用樹脂９９を盛り上げて固化させ、
全体を完全に埋没封止させるといった簡易な構成であ
る。FIG. 1A shows a general COB (Chip on Bo).
ard) mounting, the bottom surface of the bare chip LSI 9 is positioned and adhered to the surface of the circuit board 15, and the bare chip LS
The connection terminal on the surface of I9 and the surface circuit pattern 12 on the surface of the circuit board 15 are connected to each other by wire bonding,
A sealing resin 99 having electrical insulation is raised and solidified on the circuit board 15 so as to cover these surfaces,
It is a simple configuration such that the whole is completely buried and sealed.
【０００５】図（ｂ）は、回路モジュールの薄型化の要
求に対応させる実装例であり、回路基板１５の内部に、
途中内層の段部２６と、さらに内層の底面と、を露出さ
せるように開口形成される段付凹部２５を設け、段付凹
部２５の内層底面にベアチップＬＳＩ９の底面を接着固
定させるとともに、段部２６の面に内層導体により形成
されている図示省略の回路端子とベアチップＬＳＩ９表
面の接続端子とを、それぞれワイヤボンディングによっ
て回路接続させ、段付凹部２５の開口表面の周囲、すな
わち回路基板の表面上をキャップ５５によって覆い密封
するようにして接着させ開口面を封止させるものであ
る。FIG. 1B shows an example of mounting to meet the demand for a thinner circuit module.
A stepped recess 25 is formed so as to expose the step 26 of the inner layer and the bottom of the inner layer, and the bottom surface of the bare chip LSI 9 is bonded and fixed to the inner layer bottom of the step 25. A circuit terminal (not shown) formed by an inner layer conductor on the surface of the substrate 26 and a connection terminal on the surface of the bare chip LSI 9 are respectively connected to the circuit by wire bonding, and the periphery of the opening surface of the stepped recess 25, that is, on the surface of the circuit board Is covered and sealed by a cap 55 to seal the opening surface.
【０００６】[0006]
【発明が解決しようとする課題】上記、従来のベアチッ
プＬＳＩの実装構造は、いずれもが、回路基板１５面上
のベアチップＬＳＩ９の実装領域に他の回路配線をする
ことができないため完全なデッドスペースとなり、回路
構成を高密度実装ないしは小型化することができないと
いった問題がある。In any of the above-mentioned conventional bare chip LSI mounting structures, since no other circuit wiring can be made in the mounting area of the bare chip LSI 9 on the circuit board 15, a complete dead space is required. Therefore, there is a problem that the circuit configuration cannot be mounted at a high density or reduced in size.
【０００７】また、ベアチップＬＳＩ９が周辺からのＥ
ＭＩ（Electro Magnetic Interference ；電磁波障害）
などの影響をうけないよう保護する必要に対する構造上
からも問題がある。The bare chip LSI 9 is connected to the E
MI (Electro Magnetic Interference)
There is also a problem from the structural point of view that it is necessary to protect it from being affected by such factors.
【０００８】動作状態におけるベアチップＬＳＩ９から
生じる発熱を除去し温度を低下させる放熱性は、回路基
板１５が有機系材料の場合熱伝導性が低いことから、積
極的に熱伝導させて放熱させるように、ベアチップＬＳ
Ｉ９の底面側の回路基板１５を貫通させるスルーホール
を設け、このスルーホール内に伝熱用の金属を密封介在
させる対策を適用するが、期待するほどの放熱効果が得
られない。When the circuit board 15 is made of an organic material, its heat conductivity is low, so that the heat generated from the bare chip LSI 9 in the operating state is reduced and the temperature is reduced. , Bare chip LS
Although a through-hole for penetrating the circuit board 15 on the bottom surface side of the I9 is provided, and a countermeasure for sealingly interposing a metal for heat transfer in the through-hole is applied, a heat radiation effect as expected cannot be obtained.
【０００９】などの問題点がある。There are problems such as:
【００１０】本発明は、以上のような従来技術の問題点
にかんがみて、回路モジュールの小型化、高密度実装化
ならびに高放熱化の実現が図られ、かつＥＭＩ対策も講
じ得ることができるベアチップＬＳＩの実装構造を提供
することを発明の課題とするものである。SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention provides a bare chip capable of realizing miniaturization, high-density mounting and high heat radiation of a circuit module, and taking EMI measures. It is an object of the present invention to provide an LSI mounting structure.
【００１１】[0011]
【課題を解決するための手段】上記課題を解決するため
の本発明手段の構成要旨は、第１の構成要旨によれば、
多層構成の回路基板に、内層導体が露出させられてなる
底面とこの底面の途中の段部とにより開口形成されてな
る段付凹部と、この段付凹部の開口周囲面上に接地回路
に接続された環状の導体パターンと、をそなえてなり、
上記底面の内層導体上にベアチップＬＳＩをダイボンデ
ィング接続させるとともに、ベアチップＬＳＩの端子と
対向するよう途中の段部上に形成された内層導体による
回路端子とを回路接続させ、一面側が全導体面で他面側
が絶縁層を介して回路パターンの形成されてなるキャッ
プの全導体面を、段付凹部の開口面上を覆わせ周囲の環
状の導体パターンと接着し封止させることにある。According to a first aspect of the present invention, there is provided a gist of the present invention for solving the above-mentioned problems.
A stepped recess formed by a bottom surface where the inner layer conductor is exposed and a step portion in the middle of the bottom surface on a multilayer circuit board, and a ground circuit is connected to the periphery of the opening of the stepped recess. With a ring-shaped conductor pattern,
A bare chip LSI is die-bonded onto the inner layer conductor on the bottom surface, and a circuit terminal is connected to a circuit terminal formed by an inner layer conductor formed on an intermediate step so as to face the terminal of the bare chip LSI. The other surface is to cover the entire conductive surface of the cap on which the circuit pattern is formed with the insulating layer interposed therebetween and to adhere to and seal the peripheral annular conductive pattern by covering the opening surface of the stepped recess.
【００１２】また、本発明手段の第２の構成要旨によれ
ば、第１の構成要旨におけるベアチップＬＳＩをダイボ
ンディング接続させる回路基板の段付凹部底面の内層導
体の周辺にスルーホールを設け、回路基板の金属カバー
または回路基板を収容する金属ケースから突設される金
属ピンをスルーホールに挿入接続させることにある。According to a second aspect of the present invention, a through hole is provided around the inner layer conductor on the bottom surface of the stepped concave portion of the circuit board for die-bonding the bare chip LSI in the first aspect. An object of the present invention is to insert and connect a metal pin projecting from a metal cover of a board or a metal case accommodating a circuit board into a through hole.
【００１３】さらには、本発明手段の第３の構成要旨に
よれば、第１の構成要旨におけるキャップの回路パター
ンの形成された面に表面実装型部品を実装させることに
ある。Further, according to a third aspect of the present invention, there is provided a surface mount type component mounted on a surface of a cap on which a circuit pattern is formed in the first aspect.
【００１４】[0014]
【作用】上記本発明の構成要旨によると、第１の構成要
旨では、多層構成の回路基板の内層導体が露出させられ
てなる底面と途中の段部とにより開口構成される段付凹
部内にベアチップＬＳＩを実装させ、段付凹部の開口面
をキャップで覆い密封状態に封止させることにより、ベ
アチップＬＳＩはダイボンディング接続された内層導体
面とキャップの全導体面とにより上下面が導体層によっ
て覆われる。According to the gist of the present invention, in the first gist of the present invention, the multi-layer circuit board has a stepped recess formed by an exposed bottom surface and an intermediate step portion. By mounting the bare chip LSI and covering the opening surface of the stepped recess with a cap and sealing it tightly, the upper and lower surfaces of the bare chip LSI are formed by the conductive layer by the inner conductor surface connected by die bonding and the entire conductor surface of the cap. Covered.
【００１５】このベアチップＬＳＩの上面を覆うキャッ
プの全導体面は、回路基板表面の環状の導体パターンを
介して回路基板の接地回路に接続されることから接地電
位となるので、ＥＭＩに対する十分な遮蔽効果が得られ
る。Since the entire conductor surface of the cap covering the upper surface of the bare chip LSI is connected to the ground circuit of the circuit board via the annular conductor pattern on the surface of the circuit board and thus has the ground potential, sufficient shielding against EMI is achieved. The effect is obtained.
【００１６】このキャップの表面側には、回路基板の表
面回路パターンと接続し得る回路パターンが形成される
ことから、ベアチップＬＳＩの実装領域上にも回路配線
が可能となる。Since a circuit pattern that can be connected to the surface circuit pattern of the circuit board is formed on the front side of the cap, circuit wiring can be performed on the mounting area of the bare chip LSI.
【００１７】ベアチップＬＳＩから生じる発熱を放熱さ
せるには、ベアチップＬＳＩの底面がダイボンディング
接続される内層導体が広範囲な拡がり面を有することか
ら、その導体厚さ、および面積を適正化して選択するこ
とにより好適な放熱効果が得られる。In order to dissipate the heat generated from the bare chip LSI, since the inner layer conductor to which the bottom surface of the bare chip LSI is die-bonded has a widespread surface, the thickness and area of the conductor must be optimized and selected. Thus, a more suitable heat radiation effect can be obtained.
【００１８】第２の構成要旨では、第１の構成要旨の作
用に加えて、ベアチップＬＳＩの底面がダイボンディン
グ接続により実装される内層導体と接続されたスルーホ
ールに挿入接続される、金属カバーないしは金属ケース
に突設される金属ピンにより、内層導体に伝達される発
熱は、スルーホールから金属ピンを介して外部の広面積
な金属カバーまたは金属ケースに伝熱され外部空間など
へ放熱される。この金属カバーまたは金属ケースなど
は、回路基板と同等以上に十分な大きさを有することか
ら、十分な放熱量が得られる。According to the second constitution, in addition to the operation of the first constitution, the bottom surface of the bare chip LSI is inserted and connected to a through hole connected to an inner layer conductor mounted by die bonding. Heat generated by the metal pins protruding from the metal case and transmitted to the inner conductor is transferred from the through holes to the external metal cover or metal case through the metal pins and is radiated to the external space. Since the metal cover or the metal case has a sufficient size equal to or larger than that of the circuit board, a sufficient heat radiation amount can be obtained.
【００１９】第３の構成要旨では、第１の構成要旨の作
用に加えて、キャップ表面の回路パターンに回路部品を
搭載実装させるような回路構成とすることにより回路機
能を得ることができ、回路の実装密度を向上させ得る。According to the third aspect, in addition to the function of the first aspect, a circuit function can be obtained by adopting a circuit configuration in which circuit components are mounted and mounted on a circuit pattern on the surface of the cap. Can be improved.
【００２０】このように、本発明は回路モジュールの小
型化、高密度実装化ならびに高放熱化を図ることが可能
であり、かつＥＭＩ対策も講じられるベアチップＬＳＩ
の実装構造である。As described above, according to the present invention, a bare chip LSI capable of reducing the size of a circuit module, achieving high-density mounting, and achieving high heat dissipation, and taking measures against EMI.
This is the mounting structure.
【００２１】[0021]
【実施例】以下、本発明のベアチップＬＳＩの実装構造
を上記構成の要旨にもとづいた実施例により、図を参照
ながら具体的かつ詳細に説明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a mounting structure of a bare chip LSI according to the present invention.
【００２２】図１は、本発明ベアチップＬＳＩの実装構
造の一実施例であり、要部のみを示す側断面図である。
図示されるように多層構成の回路基板１の基材はセラミ
ック基材であり、表面層ならびにそれぞれの層間には導
体層および導体層からなる回路配線のパターンが形成さ
れている。FIG. 1 is a side sectional view showing only an essential part of an embodiment of a mounting structure of a bare chip LSI according to the present invention.
As shown in the figure, the substrate of the multilayer circuit board 1 is a ceramic substrate, and a conductor layer and a circuit wiring pattern composed of the conductor layer are formed between the surface layers and the respective layers.
【００２３】これらの導体層が露出させられてなる、底
面の内層導体３と底面の途中の段部２１とにより開口形
成されてなる段付凹部２と、段付凹部２の開口周囲面上
に接地回路に接続された角形の環状の導体パターン１１
と、途中の段部２１上にはベアチップＬＳＩ９のそれぞ
れの端子と対向位置に内層導体による回路端子４と、が
形成されている。A stepped concave portion 2 formed by the inner layer conductor 3 on the bottom surface and a step portion 21 on the bottom surface formed by exposing these conductor layers, and a stepped concave portion 2 on an opening peripheral surface of the stepped concave portion 2. Square annular conductor pattern 11 connected to a ground circuit
In addition, the circuit terminal 4 made of an inner layer conductor is formed on the intermediate step 21 at a position facing each terminal of the bare chip LSI 9.
【００２４】段付凹部２底面の内層導体３は回路配線層
の厚さよりも適宜に厚手であり、回路基板１のほぼ全面
に広がる大きさの面積を有する。また、段付凹部２の周
辺には、回路基板１を貫通するとともに内層導体３に接
続される金属導体層が内面に形成された複数のスルーホ
ール６が設けられる。The inner conductor 3 on the bottom surface of the stepped recess 2 is appropriately thicker than the thickness of the circuit wiring layer, and has an area large enough to cover almost the entire surface of the circuit board 1. Around the stepped recess 2, there are provided a plurality of through holes 6 which penetrate the circuit board 1 and have a metal conductor layer formed on the inner surface connected to the inner conductor 3.
【００２５】ベアチップＬＳＩ９の底面を、段付凹部２
底面の内層導体３の面に位置決めしてダイボンディング
により接着固定させるとともに、ベアチップＬＳＩ９上
面の端子と段部２１面上の回路端子４とをワイヤボンデ
ィングにより接続させる。The bottom surface of the bare chip LSI 9 is
The terminal on the inner layer conductor 3 on the bottom surface is bonded and fixed by die bonding, and the terminal on the upper surface of the bare chip LSI 9 and the circuit terminal 4 on the surface of the step portion 21 are connected by wire bonding.
【００２６】段付凹部２の開口上面を覆うキャップ８
は、銅材の薄板の片面を合成樹脂の絶縁層と、その絶縁
層の表面に導体層とを積層形成させ、この導体層に回路
パターン５２を形成させたものである。したがって、一
面側が全導体面５１で他面側が回路パターン５２の形成
されたものとなっている。A cap 8 for covering the upper surface of the stepped recess 2
Is obtained by laminating a copper-based thin plate on one side with a synthetic resin insulating layer and a conductor layer on the surface of the insulating layer, and forming a circuit pattern 52 on the conductor layer. Therefore, one surface side has the entire conductor surface 51 and the other surface side has the circuit pattern 52 formed thereon.
【００２７】以上のように構成される回路基板１の段付
凹部２周囲表面の導体パターン１１上に、キャップ８の
全導体面５１側の周囲を重ねるように位置決めし、これ
らの部分を半田付け接着することより、段付凹部２の内
部、すなわちベアチップＬＳＩ９の実装部分は密封され
る。The cap 8 is positioned on the conductor pattern 11 on the peripheral surface of the stepped recess 2 of the circuit board 1 configured as described above so that the periphery of the entire conductor surface 51 side of the cap 8 is overlapped, and these portions are soldered. By bonding, the inside of the stepped recess 2, that is, the mounting portion of the bare chip LSI 9 is sealed.
【００２８】ついで、キャップ５上面の回路パターン５
２の端部と対向する回路基板１の表面回路パターン１２
とを、ワイヤボンディングにより回路接続させることに
より回路基板モジュールが単体として完成される。Next, the circuit pattern 5 on the upper surface of the cap 5
Surface circuit pattern 12 of circuit board 1 facing the end of
Are connected to each other by wire bonding to complete the circuit board module as a single unit.
【００２９】この実施例の場合、回路パターン５２側を
単なる配線のみの回路パターンとすることなく回路機能
をそなえた回路パターン面となし、ここに表面実装型部
品９１を搭載し半田付けして実装させるようにしてい
る。In the case of this embodiment, the circuit pattern 52 side is not a circuit pattern consisting of only wiring but a circuit pattern surface having a circuit function, and a surface mount type component 91 is mounted thereon and mounted by soldering. I try to make it.
【００３０】この回路基板１を覆う金属カバー（または
金属ケース）７には、スルーホール６に挿入させる銅材
でなる金属ピン７１が、複数のスルーホール６と対応す
る位置ごとにロー付けして突設されている。On a metal cover (or metal case) 7 covering the circuit board 1, metal pins 71 made of copper material to be inserted into the through holes 6 are soldered at positions corresponding to the plurality of through holes 6. It is protruding.
【００３１】図示されるように、金属ピン７１をスルー
ホール６に挿入させ、スルーホール６内の金属導体層と
金属ピン７１とを半田付けして電気的ならびに機械的に
接続して位置固定させる。As shown, the metal pin 71 is inserted into the through hole 6, and the metal conductor layer in the through hole 6 and the metal pin 71 are soldered and electrically and mechanically connected to fix the position. .
【００３２】このような構成とすることで、動作にとも
なうベアチップＬＳＩ９の発熱は、底面から内層導体３
に伝熱されて内層導体３の全面に拡がり、内層導体３か
ら回路基板１を経て周囲の表面から外部へ伝達放熱され
るものと、スルーホール６と金属ピン７１とを介して金
属カバー（または金属ケース）７に伝達され外部へ放熱
されるものとなることから、大幅な熱放散が行なわれ、
ベアチップＬＳＩ９の温度上昇は低く抑えられる。With this configuration, the heat generated by the bare chip LSI 9 due to the operation is reduced from the bottom surface to the inner layer conductor 3.
And the heat spreads over the entire surface of the inner conductor 3 and is transmitted from the inner conductor 3 to the outside through the circuit board 1 to the outside via the circuit board 1, and the metal cover (or the through hole 6 and the metal pin 71). Since it is transmitted to the metal case 7 and radiated to the outside, significant heat dissipation is performed,
The temperature rise of the bare chip LSI 9 can be kept low.
【００３３】以上のようであるが、図示実施例は一実施
例であって本発明においては、各部の形状や材料など
は、このようなことに限定されるものではない。そのほ
か、ベアチップＬＳＩ９と回路端子４、キャップ５の回
路パターン５２と回路基板１の表面回路パターン１２、
などのワイヤボンディングによる接続を、ＴＡＢ（Tape
Automated Bonding）による接続とすることであっても
よいことである。As described above, the illustrated embodiment is an example, and in the present invention, the shape and material of each part are not limited to the above. In addition, the bare chip LSI 9 and the circuit terminal 4, the circuit pattern 52 of the cap 5 and the surface circuit pattern 12 of the circuit board 1,
Connection by wire bonding such as TAB (Tape
Automated bonding may also be used.
【００３４】回路基板１の基材をセラミック基材とした
が、紙や布、ガラスなどの繊維と、合成樹脂材とでなる
基材を積層させることでも可能なことはもちろん、キャ
ップ５も銅材の薄板としたが、これについても回路基板
１と同様基材とし、一面側を全導体面とすることにより
可能であある。Although the base material of the circuit board 1 is a ceramic base material, it is also possible to laminate a base material made of a synthetic resin material with a fiber such as paper, cloth, glass or the like. Although the thin plate is made of a material, it can be formed by using a base material similar to the circuit board 1 and making one surface side the entire conductor surface.
【００３５】[0035]
【発明の効果】以上詳細に述べたように、本発明のベア
チップＬＳＩの実装構造によれば、回路モジュールの小
型化、高密度実装化が得られ、かつ放熱特性の向上、な
らびにＥＭＩ対策も十分に行なわれる実装構造であり、
電気的特性および各種信頼性の向上が得られるなど、そ
の実用上の効果はきわめて顕著なものである。As described above in detail, according to the mounting structure of the bare chip LSI of the present invention, the circuit module can be reduced in size and the density can be increased, the heat radiation characteristics can be improved, and the EMI countermeasures can be sufficiently improved. Mounting structure,
Its practical effects are extremely remarkable, such as improvements in electrical characteristics and various reliability.
【図１】本発明の一実施例の構造断面図である。FIG. 1 is a structural sectional view of an embodiment of the present invention.
【図２】従来例のベアチップＬＳＩの実装構造である。FIG. 2 shows a mounting structure of a conventional bare chip LSI.
１ 回路基板 ２ 段付凹部 ３ 内層導体 ４ 回路端子 ５ キャップ ６ スルーホール ７ 金属カバー ９ ベアチップＬＳＩ １１ 導体パターン １２ 表面回路パターン １５ 回路基板 ２１ 段部 ２５ 段付凹部 ２６ 段部 ５１ 全導体面 ５２ 回路パターン ５５ キャップ ７１ 金属ピン ９１ 表面実装型部品 ９９ 樹脂 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Stepped recess 3 Inner layer conductor 4 Circuit terminal 5 Cap 6 Through hole 7 Metal cover 9 Bare chip LSI 11 Conductor pattern 12 Surface circuit pattern 15 Circuit board 21 Step 25 Stepped recess 26 Step 51 All conductor surface 52 Circuit Pattern 55 Cap 71 Metal pin 91 Surface mount type component 99 Resin
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭64−13755（ＪＰ，Ａ) 特開 昭63−194350（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H05K 1/18 H01L 23/12 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-64-13755 (JP, A) JP-A-63-194350 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H05K 1/18 H01L 23/12
Claims (3)
させられてなる底面と該底面の途中の段部とにより開口
形成されてなる段付凹部と、上記段付凹部の開口周囲面
上に接地回路に接続された環状の導体パターンとをそな
え、 上記底面の内層導体上にベアチップＬＳＩをダイボンデ
ィング接続させるとともにベアチップＬＳＩの端子と対
向するよう途中の段部上に形成された内層導体による回
路端子とを回路接続させ、一面側が全導体面で他面側が
絶縁層を介して回路パターンの形成されてなるキャップ
の全導体面を上記段付凹部の開口面上を覆わせ周囲の環
状の導体パターンと接着し封止させる ことを特徴とする
ベアチップＬＳＩの実装構造。An inner conductor is exposed on a multilayer circuit board.
An opening is formed by the bottom surface formed and the step portion in the middle of the bottom surface.
A stepped recess formed and an opening peripheral surface of the stepped recess
An annular conductor pattern connected to the ground circuit
A bare chip LSI is die-bonded on the inner conductor on the bottom surface.
With the bare chip LSI terminals.
Of the inner conductor formed on the step
Circuit connection with the circuit terminal, one side is the entire conductor surface and the other side is
Cap with circuit pattern formed via insulating layer
Cover the entire conductor surface of
A bare chip LSI mounting structure, wherein the bare chip LSI is bonded and sealed to a conductor pattern in a shape of a circle.
グ接続させる回路基板の段付凹部底面の内層導体の周辺
にスルーホールを設け、回路基板の金属カバーまたは回
路基板を収容する金属ケースから突設される金属ピンを
上記スルーホールに挿入接続させることを特徴とする請
求項１記載のベアチップＬＳＩの実装構造。2. A near the inner conductor of the stepped recess bottom surface of the circuit board to the bare chip LSI die bonding connection
And a metal pin protruding from a metal cover of the circuit board or a metal case for housing the circuit board.
2. The mounting structure of a bare chip LSI according to claim 1, wherein said bare chip LSI is inserted and connected to said through hole .
た面に表面実装型部品を実装させることを特徴とする請
求項１記載のベアチップＬＳＩの実装構造。3. the circuit pattern is formed in the cap
2. The mounting structure of a bare chip LSI according to claim 1, wherein a surface mount type component is mounted on the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3266596A JP2973646B2 (en) | 1991-10-16 | 1991-10-16 | Mounting structure of bare chip LSI |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3266596A JP2973646B2 (en) | 1991-10-16 | 1991-10-16 | Mounting structure of bare chip LSI |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05114776A JPH05114776A (en) | 1993-05-07 |
| JP2973646B2 true JP2973646B2 (en) | 1999-11-08 |
Family
ID=17433010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3266596A Expired - Fee Related JP2973646B2 (en) | 1991-10-16 | 1991-10-16 | Mounting structure of bare chip LSI |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2973646B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538310B2 (en) | 2000-03-15 | 2003-03-25 | Nec Corporation | LSI package with internal wire patterns to connect and mount bare chip to substrate |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2682477B2 (en) * | 1994-11-16 | 1997-11-26 | 日本電気株式会社 | Circuit component mounting structure |
| JPH09199824A (en) * | 1995-11-16 | 1997-07-31 | Matsushita Electric Ind Co Ltd | Printed wiring board and its mounting body |
| JP2842378B2 (en) * | 1996-05-31 | 1999-01-06 | 日本電気株式会社 | High-density mounting structure for electronic circuit boards |
| JP3539467B2 (en) * | 1997-03-25 | 2004-07-07 | ミツミ電機株式会社 | Electronic component module |
| JP4154806B2 (en) * | 1999-06-29 | 2008-09-24 | 三菱電機株式会社 | High frequency module |
| US6392298B1 (en) * | 2000-02-28 | 2002-05-21 | Ericsson Inc. | Functional lid for RF power package |
-
1991
- 1991-10-16 JP JP3266596A patent/JP2973646B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538310B2 (en) | 2000-03-15 | 2003-03-25 | Nec Corporation | LSI package with internal wire patterns to connect and mount bare chip to substrate |
| US6653168B2 (en) | 2000-03-15 | 2003-11-25 | Nec Corporation | LSI package and internal connecting method used therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05114776A (en) | 1993-05-07 |
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