JPH1023102A - Information processing unit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the device cost and to improve the processing speed. SOLUTION: A work station 41 connects to a computer network to which an information server is connected and receives a packet including data sent from the information server, writes the packet data to a RAM 42 in response to a value of a write enable flag of the RAM 42 and changes a write enable flag and a read enable flag in the RAM 42. An encoder 43 reads data of the packet written by the work station 41 from the RAM 42 depending on the value of the read enable flag in the RAm 42 and changes the write enable flag and the read enable flag in the RAM 42. Then the work station 41 writes succeeding data to the RAM 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and method, and more particularly, to a method in which a first information processing unit writes data to a storage unit according to a value of a first area of the storage unit. The value of the first area and the value of the second area of the storage unit are changed, and the second information processing unit reads out the data written to the storage unit according to the value of the second area of the storage unit. After
The present invention relates to an information processing apparatus and method for changing a value of a first area and a value of a second area of a storage unit.

[0002]

2. Description of the Related Art With the recent advance in information processing technology, various information processing apparatuses for performing predetermined processing on data have been developed.

For example, in the case of performing data communication between two information processing units operating with different clock signals, in order to alleviate a difference in processing speed between the two information processing units, the data communication is performed via a memory. In many cases, data is exchanged.

FIG. 15 shows an example of an information processing apparatus having such two information processing units. In this information processing apparatus, a workstation (WS) 61
Upon receiving the data transmitted via the computer network, the data is written in a predetermined storage area of the RAM 62, and when the predetermined amount of data has been written, the corresponding information is transmitted to the encoder 63.
At this time, if necessary, the WS 61 determines the address (address) where the data is written and the length of the data by the encoder 6.
Send to 3.

[0005] When the encoder 63 receives the information, it reads out the data written by the workstation 61 from the RAM 62, and when the reading of the data is completed, transmits the corresponding information to the workstation 61. And the workstation 61
Writes the next data to the RAM 62. At this time, the encoder 63 applies, for example,
When the compression process is completed and the writing of the next data to the RAM 62 by the workstation 61 is completed, the next data is read.

[0006] Thus, the workstation 61
Supplies a predetermined amount of data sequentially to the encoder 63 via the RAM 62.

[0007]

However, in the above-described apparatus, the work station 61 has the RAM 6
2 is transmitted to the encoder 63, and the encoder 63 needs to transmit, to the workstation 61, information corresponding to the end of reading data from the RAM 62. An interface or the like for transmitting or receiving data is required, and it is difficult to reduce the cost of the apparatus.

Further, each time a predetermined amount of data is transmitted or received, the above-mentioned information needs to be transmitted and received, so that it is difficult to increase the data processing speed.

SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and writes information on the end of data writing and the end of data reading into a predetermined storage area of a RAM so that a work station and an encoder can communicate with each other. By eliminating the need for such communication, the cost of the apparatus can be reduced and the processing speed can be improved.

[0010]

According to the first aspect of the present invention, there is provided an information processing apparatus wherein data is written to a fixed-length storage area corresponding to a value of a first area in a fixed-length storage area of a storage means. Then, the first information processing means for changing the value of the first area and the value of the second area of the fixed-length storage area, and the first information processing means corresponding to the value of the second area in the fixed-length storage area of the storage means. Second information processing means for reading the data written in the fixed-length storage area by the first information processing means and then changing the value of the first area and the value of the second area. It is characterized by.

According to a fourth aspect of the present invention, in the information processing method, the first information processing section stores the data in the fixed length storage area of the predetermined storage section in accordance with the value of the first area in the fixed length storage area. Changing the value of the first area and the value of the second area of the fixed-length storage area after writing to the storage area; and 2
After reading the data written to the fixed-length storage area by the first information processing unit in accordance with the value of the area,
Changing the value of the area and the value of the second area.

According to a fifth aspect of the present invention, the information processing apparatus secures a predetermined number of fixed-length storage areas corresponding to the value of the first area in the first fixed-length storage area of the storage means. The number of fixed-length storage areas is written to the second area of the fixed-length storage area, and data is written to each fixed-length storage area. First information processing means for changing the value of the first fixed-length storage area of the first fixed-length storage area of the first fixed-length storage area of the storage means; After reading the number of fixed-length storage areas written in the area No. 2 and reading the data written by the first information processing means from the fixed-length storage areas, the first fixed-length storage area is read. A second method for changing the value of the first area and the value of the third area of the storage area Characterized in that it comprises an information processing means.

[0013] In the information processing method according to the present invention, the first information processing section may correspond to a value of the first fixed length storage area of the first fixed length storage area of the predetermined storage section. After writing the number of fixed-length storage areas in the second area of the storage area, and writing data in each fixed-length storage area,
Changing the value of the first area and the value of the third area of the first fixed-length storage area; and
Reading the number of fixed-length storage areas written in the second area of the first fixed-length storage area corresponding to the value of the third area in the first fixed-length storage area of the storage unit; After reading the data written by the first information processing unit from the fixed-length storage areas of that number, the value of the first area and the value of the third area of the first fixed-length storage area are changed. And a step.

According to a ninth aspect of the present invention, in the information processing apparatus, data is sequentially written to a plurality of fixed-length storage areas in accordance with a value of a first area in the first fixed-length storage area of the storage means. After writing a predetermined value in the second area of the last fixed length storage area, first information processing for changing the value of the first area and the value of the third area of the first fixed length storage area Means, and sequentially writes the data written by the first information processing means from the plurality of fixed length storage areas corresponding to the value of the third area in the first fixed length storage area of the storage means. , After the data reading is completed according to the value of the second area, the first fixed-length storage area of the first fixed-length storage area.
And a second information processing means for changing the value of the third area and the value of the third area.

[0015] In the information processing method according to the twelfth aspect, the first
The information processing unit sequentially writes data into a plurality of fixed-length storage areas corresponding to the value of the first area in the first fixed-length storage area of the predetermined storage unit, and stores the last fixed-length storage area. After writing a predetermined value in the second area of the area, changing the value of the first area and the value of the third area of the first fixed-length storage area; and In accordance with the value of the third area in the first fixed length storage area of the storage unit, the data written by the first information processing unit is sequentially read from the plurality of fixed length storage areas, Changing the value of the first area and the value of the third area of the first fixed-length storage area after the end of data reading in accordance with the value of the area.

According to a thirteenth aspect of the present invention, in the information processing apparatus, a predetermined number of fixed-length storage areas are secured corresponding to the value of the first area in the first fixed-length storage area of the storage means. Are sequentially written from the first fixed-length storage area, and when the end of data is reached, a predetermined value is written in the second area of the next fixed-length storage area, and then the first fixed-length storage area is written. First information processing means for changing the value of the first area and the value of the third area of the storage area; and a plurality of information processing means corresponding to the value of the third area in the first fixed length storage area of the storage means. The data written by the first information processing means is sequentially read from the fixed-length storage area, and the data reading is terminated according to the value of the second area. Second information for changing the value of the first area and the value of the third area Characterized in that it comprises a processing means.

[0017] The information processing method according to claim 16 is characterized in that:
The information processing unit secures a predetermined number of fixed-length storage areas corresponding to the value of the first area in the first fixed-length storage area of the predetermined storage unit, and stores the data in the first fixed-length storage area. Are sequentially written from the storage area, and when the end of data is reached, a predetermined value is written to the second area of the next fixed-length storage area, and then the first area of the first fixed-length storage area is written. Changing the value of the third area and the value of the third area, and the second information processing unit causes the second information processing unit to change a plurality of fixed lengths corresponding to the value of the third area in the first fixed length storage area of the storage unit. The data written by the first information processing unit is sequentially read from the storage area, and the data reading is completed according to the value of the second area, and the first area of the first fixed length storage area is read out. And changing the value of the third region. That.

In the information processing apparatus according to the first aspect, the first information processing means stores data in a fixed length storage area corresponding to a value of the first area in the fixed length storage area of the storage means. Then, the value of the first area and the value of the second area of the fixed-length storage area are changed, and the second information processing means stores the value of the second area in the fixed-length storage area of the storage means. After reading the data written to the fixed-length storage area by the first information processing means in accordance with the value, the first
And the value of the second area are changed.

In the information processing method according to the fourth aspect, the first information processing section stores the data in the fixed length storage area corresponding to the value of the first area in the fixed length storage area of the predetermined storage section. Then, the value of the first area and the value of the second area of the fixed-length storage area are changed, and the second information processing unit causes the second information processing unit to change the value of the second area in the fixed-length storage area of the storage unit. After reading the data written in the fixed-length storage area by the first information processing unit in accordance with the value of the area, the value of the first area and the value of the second area are changed.

In the information processing apparatus according to the fifth aspect, the first information processing means includes a predetermined number of fixed numbers corresponding to the values of the first area in the first fixed length storage area of the storage means. A fixed-length storage area, and writes the number of fixed-length storage areas in the second area of the first fixed-length storage area;
After writing data in each fixed length storage area, the value of the first area and the value of the third area of the first fixed length storage area are changed, and the second information processing means Corresponding to the value of the third area in the first fixed length storage area,
The number of fixed-length storage areas written in the second area of the first fixed-length storage area is read, and data written by the first information processing means is read from the fixed-length storage areas. After reading, the value of the first area and the value of the third area of the first fixed-length storage area are changed.

In the information processing method according to the present invention, the first information processing section may store the first fixed length corresponding to the value of the first area in the first fixed length storage area of the predetermined storage section. After writing the number of fixed-length storage areas in the second area of the long storage area, writing data to each fixed-length storage area, the value of the first area of the first fixed-length storage area and The value of the third area is changed, and the second information processing unit determines that the value of the third area in the first fixed-length storage area of the storage unit corresponds to the value of the second area of the first fixed-length storage area. Read the number of fixed-length storage areas written in the area of
After reading the data written by the first information processing unit from the fixed-length storage areas of that number, the value of the first area and the value of the third area of the first fixed-length storage area are changed. .

In the information processing apparatus according to the ninth aspect, the first information processing means stores the plurality of data in correspondence with the value of the first area in the first fixed length storage area of the storage means. After sequentially writing to the fixed-length storage area and writing a predetermined value to the second area of the last fixed-length storage area, the value of the first area of the first fixed-length storage area and the value of the third area are stored. The second information processing means changes the value from the plurality of fixed-length storage areas corresponding to the value of the third area in the first fixed-length storage area of the storage means. Is sequentially read, and after the data reading is completed in accordance with the value of the second area, the value of the first area and the value of the third area of the first fixed-length storage area To change.

In the information processing method according to the twelfth aspect, the first information processing section stores data corresponding to a value of the first area in the first fixed length storage area of the predetermined storage section. After sequentially writing to a plurality of fixed-length storage areas and writing a predetermined value to a second area of the last fixed-length storage area, the value of the first area of the first fixed-length storage area and the third value are written. The value of the area is changed, and the second information processing unit reads the first information from the plurality of fixed-length storage areas corresponding to the value of the third area in the first fixed-length storage area of the storage unit. The data written by the processing unit is sequentially read, and the second
After finishing reading data according to the value of the area of
The value of the first area and the value of the third area of the first fixed-length storage area are changed.

In the information processing apparatus according to the thirteenth aspect, the first information processing means includes a predetermined number of fixed numbers corresponding to the values of the first area in the first fixed length storage area of the storage means. A data storage area having a predetermined length is secured, data is sequentially written from the first fixed-length storage area, and when the end of data is reached, a predetermined value is stored in a second area of the next fixed-length storage area. After writing, the first fixed-length storage area
And the value of the third area are changed, and the second information processing means corresponds to the value of the third area in the first fixed length storage area of the storage means. The data written by the first information processing means is sequentially read from the storage area, and the data reading is terminated in accordance with the value of the second area, and the first area of the first fixed length storage area is read out. And the value of the third area are changed.

In the information processing method according to the sixteenth aspect, the first information processing unit may store a predetermined number of data in the first fixed length storage area of the predetermined storage unit in correspondence with a value of the first area. , And data is sequentially written from the first fixed-length storage area. When the end of the data is reached, a predetermined value is stored in the second area of the next fixed-length storage area. After writing the first fixed-length storage area,
And the value of the third area are changed, and the second information processing unit causes the second information processing unit to change the value of the plurality of fixed lengths corresponding to the value of the third area in the first fixed length storage area of the storage unit. The data written by the first information processing unit is sequentially read from the storage area, and the data reading is completed according to the value of the second area, and the first area of the first fixed length storage area is read out. And the value of the third area are changed.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the appended claims and the following embodiments, When the features of the present invention are described by adding the corresponding embodiment (but one example) in parentheses, the following is obtained.

That is, in the information processing apparatus according to the first aspect, the first information processing means (for example, the work station 41 in FIG. 2) is replaced by the storage means (for example, the RAM in FIG. 2).
42) corresponding to the value of the first area (for example, the writable flag WR in FIG. 3) in the fixed-length storage area,
After writing the data in the fixed-length storage area, the value of the first area and the value of the second area (for example, the readable flag RD in FIG. 3) of the fixed-length storage area are changed, and the second information is changed. The processing means (for example, the encoder 43 in FIG. 2) stores the data written in the fixed-length storage area by the first information processing means in accordance with the value of the second area in the fixed-length storage area of the storage means. Is read, and then the value of the first area and the value of the second area are changed.

Further, in the information processing apparatus according to the present invention, the first information processing means (for example, the work station 41 in FIG. 2) is replaced with the storage means (for example, the RAM in FIG. 2).
42) In accordance with the value of the first area (for example, the writable flag WR in FIG. 6) in the first fixed length storage area of the first fixed length storage area, a predetermined number of fixed length storage areas are secured. The number of fixed-length storage areas is written in a second area of the storage area (for example, the number of blocks in FIG. 6), data is written in each fixed-length storage area, and then the first fixed-length storage area is written. Of a first region and a third region (eg,
The value of the readable flag RD in FIG. 6 is changed, and the second information processing means (for example, the encoder 43 in FIG. 2) corresponds to the value of the third area in the first fixed-length storage area of the storage means. Then, the number of fixed-length storage areas written in the second area of the first fixed-length storage area is read, and the number of fixed-length storage areas written by the first information processing means is read from the fixed-length storage area. After reading the stored data, the value of the first area and the value of the third area of the first fixed-length storage area are changed.

Further, in the information processing apparatus according to the ninth aspect, the first information processing means (for example, the workstation 41 of FIG. 2) is provided with a storage means (for example, the RA of FIG. 2).
M42), data is sequentially written into a plurality of fixed-length storage areas corresponding to the value of the first area (for example, the writable flag WR in FIG. 9) in the first fixed-length storage area, and the last fixed-length storage area is written. After writing a predetermined value in a second area of the long storage area (for example, the last data block flag LB in FIG. 9), the value of the first area of the first fixed length storage area and the third area ( For example, the readable flag R shown in FIG.
D), the second information processing means (for example, FIG. 2
Encoder 43) sequentially stores the data written by the first information processing means from the plurality of fixed length storage areas in accordance with the value of the third area in the first fixed length storage area of the storage means. Reading, and after ending the data reading in accordance with the value of the second area, changing the value of the first area and the value of the third area of the first fixed-length storage area. I do.

In the information processing apparatus according to the thirteenth aspect, the first information processing means (for example, the work station 41 in FIG. 2) is provided with a storage means (for example, the RAM
According to the value of the first area (for example, the writable flag WR in FIG. 12) of the first fixed-length storage area of 2), a predetermined number of fixed-length storage areas are secured, and data is stored in the storage area.
The data is sequentially written from the first fixed-length storage area, and when the end of the data is reached, the second fixed-length storage area becomes
Area (for example, batch processing end flag FN in FIG. 12)
After a predetermined value is written in the second information, the value of the first area and the value of the third area (for example, the readable flag RD in FIG. 12) of the first fixed-length storage area are changed, and the second information The processing unit (for example, the encoder 43 in FIG. 2) converts the plurality of fixed-length storage areas into the first information processing unit corresponding to the value of the third area in the first fixed-length storage area of the storage unit. Sequentially reads the data written by
Data reading is terminated according to the value of the second area,
The value of the first area and the value of the third area of the first fixed-length storage area are changed.

However, of course, this description does not mean that each means is limited to those described above.

FIG. 1 shows an example of the configuration of a data distribution system. In this system, a receiver 1 sends an instruction to a transmitting station 2 or an information provider 3 via a telephone line using a modem 11 so as to distribute desired data. And the recipient 1
The data distributed according to the instruction is transmitted to the antenna 13
Via the receiving device 12.

When the information provider 2 receives the instruction from the receiver 1 by the modem 21, the information provider 2 outputs the instruction to the server 22 which compresses and holds the specified data. The server 22 transmits the specified data to the transmitting station 3 via a computer network such as the Internet.

The transmitting station 3 receives the data (packet) transmitted from the information provider 2 via the computer network by the information processing apparatus 31 according to one embodiment of the present invention, and transmits the data to, for example, the MPEG2 system. After compression, the compressed data (data to be delivered to the recipient 1)
The data is output to the transmission device 33 via the multiplexer 32. Then, the transmitting device 33 transmits the data to the artificial satellite 4 via the antenna 34, and causes the artificial satellite 4 to distribute the data.

Further, the transmitting station 3 uses the modem 35 to
Is received, the data held by the server 36 of the transmitting station 3 is read out, compressed by the encoder 37, and then supplied to the transmitting device 33 via the multiplexer 32. The signal is transmitted to the artificial satellite 4 via the communication terminal 34.

The artificial satellite 4 receives data from the transmitting station 3 and distributes the data.

FIG. 2 shows the configuration of an information processing apparatus 31 which is a first embodiment of the information processing apparatus of the present invention.

The workstation (WS) 41 (first information processing means) is connected to a computer network to which the information provider 2 is connected.
Receives a packet including data transmitted from the server 22 of the other, and writes the data of the packet to the RAM 42 according to the state of the predetermined storage area (the state of the flag) of the RAM 42 (storage means). .

The RAM 42 holds the data of the packet written by the workstation 41.

FIG. 3 shows an example of allocation of storage areas in the RAM 42. The RAM 42 is managed for each storage area of a fixed length (in this case, 2,048 bytes) longer than the maximum length of a packet. For example, Internet I
In the case of Ethernet (Ethernet), which is one of the media for transmitting packets corresponding to the P protocol, the maximum length of a packet is 1,526 bytes (the data portion excluding the header portion and the like is 1,526 bytes). 500 bytes).

The first address (((i-1) × 2048)) of the i-th fixed-length storage area has a writable flag WR (first bit) and a readable flag RD (second bit). Bit) is stored. The writable flag WR is determined by the RA
M42 holds a value indicating permission or non-permission of writing data to M42.
No. 3 holds a value indicating permission or non-permission of reading data from the RAM 42.

Next, the third ((i-1) .times.2048 + 2) address and the fourth ((i-1) .times.2048 + 3) address of each fixed-length storage area of the RAM 42 have the (first) address. The length (byte length) of the data stored in the (i-th) fixed-length storage area is written.

The packet data is written from the fifth ((i−1) × 2048 + 4) address to the last ((i−1) × 2048 + 2047) address of each fixed-length storage area of the RAM 42. . That is, a maximum of 2,044 bytes of data can be written in each fixed-length storage area. If the data of the packet is short, the area from the address next to the position where the end of the data is written to the last ((i-1) × 2048 + 2047) area is a free area and is not used.

Encoder 43 (second information processing means)
Are stored in the RAM 42 in accordance with the state of the predetermined storage area of the RAM 42 (the state of the flag).
1 reads out the data of the packet written, converts the data of the packet into the data held by the server 22 of the information provider 2, and further compresses the data by, for example, the MPEG2 method. Is output to the multiplexer 32.

Next, referring to the flowchart of FIG.
The operation of the workstation 41 according to the first embodiment will be described.

First, in step S1, the workstation 41 stores the packet data in a storage area (fixed length storage area) (in this case, the fixed length is 2,
048 bytes) is set to zero.

Next, in step S2, the work station 41 reads the data (1 byte) of the address (N × 2048) (hexadecimal (N × 800H)) in the RAM 42. That is, when N = 0, the workstation 41 reads the data at the address 0 of the RAM 42 (FIG. 3).

Then, in step S3, the workstation 41 reads out the first bit (write enable flag WR) of the data at the address (N × 2048).
, It is determined whether or not the value of the flag WR is a value corresponding to “writable”. If it is determined that the value of the flag WR is a value corresponding to “writable”, the process proceeds to step S4. Proceed to.

On the other hand, if it is determined in step S3 that the state is not "writable", the process returns to step S2, and the workstation 41 returns to (N * 204)
8) Read the data at the address. Thus, the workstation 41 sets the value of the writable flag WR to
Until the value corresponding to “writable” is reached in step S2
And it waits in step S3. That is, packet data read processing by the encoder 43 (described later).
Wait until is finished.

In the initial state, no data has been written to the RAM 42, so that the value of the writable flag WR is set to “writable” so that the workstation 41 can write data to the RAM 42 first. And the value of the readable flag RD is
It is set to “readout disabled”.

Then, in step S4, the work station 41 sets the (N × 2048 + 2)
After writing the data length of the packet to be written at the address and the address (N × 2048 + 3),
4) Write the packet data into the storage area after the address. That is, when N = 0, as shown in FIG. 3, the workstation 41 writes the data length at addresses 2 and 3, and then writes the data at address 4 and thereafter.

Next, in step S5, the workstation 41 writes the value corresponding to "write-disabled" into the first bit (write enable flag WR) at the address (N.times.2048) of the RAM 42, and N ×
2048) Write a value corresponding to “Readable” to the second bit (Readable Flag RD) at address.
That is, if N = 0, the workstation 41
A predetermined value is written to the first bit and the second bit at address 0, respectively.

Then, in step S6, the workstation 41 refers to the value of the counter N and
It is determined whether or not all of the storage areas 42 have been used.
If it is determined that the entire storage area of M42 has been used (if it is determined that the next 2,048-byte storage area cannot be secured), the process returns to step S1, and the counter N
Is reset to zero, and the RAM 42 is sequentially used from the beginning.

On the other hand, if the workstation 41 determines in step S6 that a storage area of the next 2,048 bytes can be secured, it increases the counter N by 1 in step S7, and then proceeds to step S2.
Then, in steps S2 to S5, a process of writing the data of the next packet to the next 2,048-byte storage area is performed. For example, when N = 0, the workstation 41 sets the value of the counter N to 1 in step S7, and performs the writing process on the 2,048-byte storage area starting from address 2048 in steps S2 to S5. Do.

In this way, the workstation 41
Writes the packet data in the RAM 42 sequentially into the storage area of 2,048 bytes.

Next, referring to the flowchart of FIG.
The operation of the encoder 43 of the information processing device 31 according to the present embodiment will be described.

First, in step S1, the encoder 43 sets the value of the counter N for designating a storage area (fixed length storage area) from which a packet is read (in this case, the fixed length is 2,048 bytes). Is set to zero.

Next, in step S22, the encoder 43 reads the data (8 bits) of the address (N × 2048) (hexadecimal number (N × 800H)) of the RAM 42. That is, when N = 0, the encoder 43
Reads the data at address 0 of the RAM 42 (FIG. 3).

In step S23, the encoder 43 refers to the value of the second bit (read enable flag RD) of the read data at the address (N × 2048), and sets the value of the flag RD to “read enable”. Is determined as to whether or not the value of the flag RD is a value corresponding to “readable”, the process proceeds to step S2.
Proceed to 4.

On the other hand, if it is determined in step S23 that the state is not "read-only", the process returns to step S22, and the encoder 43 reads out the data at the address (N × 2048) again. Thus, the encoder 43
Waits in steps S22 and S23 until the value of the readable flag RD reaches a value corresponding to “readable”. That is, workstation 4
1 and waits until the packet data writing process is completed.

In the initial state, no data has been written to the RAM 42, so that the value of the writable flag WR is set to “writable” so that the workstation 41 can write data to the RAM 42 first. And the value of the readable flag RD is
It is set to “readout disabled”.

In step S24, the encoder 43 reads the data length from the addresses (N × 2048 + 2) and (N × 2048 + 3) in the RAM 42, and then reads the data length from the storage area after the address (N × 2048 + 4). , Read the packet of that length. That is, when N = 0, the encoder 43 reads the data length from the addresses 2 and 3 and reads the data length from the storage area from the address 4 onward.
The data of that length is read.

Next, in step S25, the encoder 43 writes the value corresponding to "read-out impossible" into the second bit (read-out flag RD) of the address (N.times.2048) in the RAM 42, and sets (N × 204
8) The first bit at address (writable flag W
R), the value corresponding to “writable” is written.

In step S26, the encoder 43 processes the read packet data (converts the packetized data into the original data,
Processing for compressing the data).

Next, in step S27, the encoder 43 refers to the value of the counter N to determine whether or not all the storage areas of the RAM 42 have been used, and determines that all of the storage areas of the RAM 42 have been used. (Step S
24 and when it is determined that the fixed-length storage area processed in step S25 is the last fixed-length storage area in the RAM 42), the process returns to step S21, the counter N is reset to zero, and the first storage area in the RAM 42 The packet is read again.

On the other hand, the encoder 43 determines in step S27
In step S28, if it is determined that the fixed-length storage area processed in steps S24 and S25 is not the last fixed-length storage area, the counter N is incremented by 1 in step S28, and the process returns to step S22. In S22 to S25, a process of reading the data of the next packet from the next 2,048-byte storage area is performed. For example, when N = 0, the encoder 43 sets the value of the counter N to 1 in step S28, and in step S22 to step S25,
A read process is performed for the next storage area starting from address 2048.

In this way, the encoder 43
The data of the packet is sequentially read from each fixed-length storage area of M42, and the data of the packet is processed.

As described above, in the first embodiment, the RAM 42 is managed for each fixed-length storage area, and the writing process and the reading process for the RAM 42 are performed using the writable flag WR and the readable flag RD. By controlling the processing, direct communication between the workstation 41 and the encoder 43 is not required.

Since the data of one packet is written in one fixed-length storage area, there is no need to perform processing such as data division, and the workstation 41 immediately transmits the data received via the computer network. , RAM42.

Next, a second embodiment of the present invention will be described. The second embodiment is the same as the first embodiment except for the method of using the storage area of the RAM 42.
Only the method of using No. 2 will be described.

FIG. 6 shows an example of allocation of storage areas in the RAM 42 according to the second embodiment. The RAM 42 is
It is managed for each fixed-length storage area (block) of 2,048 bytes. Then, a predetermined number (512 in this case)
Area (2 20 bytes =
512 × 2048 or 1 megabyte)
One writing process or one reading process is performed. Then, in the writing process, the area (51
Packet data is written in a predetermined number of blocks of the two blocks). In the reading process, packet data is read from a predetermined number of blocks in the area.

The start address (((j) of the first block of the j-th area (area composed of 512 blocks)
-1) × 2 (20th power) address) has a writable flag WR (first bit) and a readable flag RD
(The second bit) is stored. The writable flag WR is stored in the RAM 4 by the workstation 41.
2, the value indicating permission or non-permission of writing data to the memory 2, and the readable flag RD holds a value indicating permission or non-permission of reading of data from the RAM 42 by the encoder 43.

The third to eighth bits of the first address of the first block of the j-th area and the second address of the first block contain packet data in this area. The number of blocks to be written is written.

Then, the third address of the i-th block of the j-th area (((j-1) × 2 to the power of 20+
(I−1) × 2048 + 2) and the fourth address (((j−1) × 2 to the 20th power + (i−1) × 2048 +)
In (3) address), the data length of the packet to be written in the (i-th) block is written.

The fifth address of the block of the RAM 42 (((j−1) × 2 to the 20th power + (i−1) × 2048 +
The data of this (i-th) packet is written from address 4) to the last address (address ((j-1) × 2 to the 20th power + (i-1) × 2048 + 2047)). When the data of the packet is short, the area from the address next to the position where the end of the packet is written to the last address of the block is a free area and is not used.

As described above, in the RAM 42, a total of 512 blocks are used as one area in one writing process or one reading process.

Next, referring to the flowchart of FIG.
The operation of the workstation 41 according to the second embodiment will be described.

First, in step S41, the work station 41 sets the area of the RAM 42 composed of 512 blocks (in this case, 2 to the 20th power byte = 1).
The value of a counter M for counting the number of megabytes is set to zero.

Next, in step S42, the workstation 41 reads out the data (1 byte) of the address (M × 2 to the 20th power) (hexadecimal number M × 100,000H) in the RAM 42, and in step S43, reads out the data. It is determined whether or not the value of the first bit (writable flag WR) is a value corresponding to “writable”, and it is determined that the value of the writable flag WR is a value corresponding to “writable”. If so, the process proceeds to step S44. In other words, if M = 0, the workstation 41
The data at the address is read (FIG. 6).

On the other hand, if it is determined that the value of the writable flag WR is not a value corresponding to “writable”, the process returns to step S42, and the workstation 41 again performs
The data at the address of (M × 2 to the 20th power) is read from the RAM, and in step S43, the write enable flag WR is written.
Is determined to be a value corresponding to “writable”. Thus, the workstation 41 waits until the value of the writable flag WR becomes a value corresponding to “writable”. That is, the workstation 43
Waits until the encoder 43 finishes the reading process and changes the value of the flag.

In the initial state, no data is written in the RAM 42, so that the value of the writable flag WR is set to “writable” so that the workstation 41 can write data to the RAM 42 first. And the value of the readable flag RD is
It is set to “readout disabled”.

Next, in step S44, the workstation 41 stores the packet in the third to eighth bits of the address (M × 2 to the power of 20) and the address of (M × 2 to the power of 20 + 1). Is written as the number L (L ≦ 512) of blocks into which the data is written.

Then, in step S45, the workstation 41 sets the value of the counter N for counting the number of blocks in which the data of the packet is written to zero.

Next, in step S46, the work station 41 sets (M × 2 to the power of 20 + N × 2048 +
2) Address and (M × 2 to the 20th power + N × 2048 + 3)
After writing the data length of the packet to be written in the block at the address, (M × 2 20 + N × 2048 +
4) Write data to the storage area after the address.

For example, if M = 0 and N = 0, the work station 41
After writing the data length of the packet to be written in the first block at addresses 3 and 3, the data is written to the storage area after address 4.

Then, in step S47, the workstation 41 determines whether or not the value of the counter N has reached L-1 (whether or not packet data has been written in L blocks). If it is determined that the packet data has been written to the block, the process proceeds to step S48, where the write enable flag WR at the address (M × 2 to the 20th power) is written.
Is set to a value corresponding to “writable” and the value of the readable flag RD is set to a value corresponding to “readable”.

On the other hand, in step S47, L
If it is determined that the data of the packet has not been written to the blocks, the workstation 41 increases the value of the counter N by 1 in step S49, and returns to step S46 to store the next packet in the next block. Write data. For example, when M = 0 and N = 0, the workstation 41 sets the value of the counter N to 1 and then sets the value of 2050 in step S46 and thereafter.
(= 2048 + 2) address and 2051 (= 2048 +
3) After writing the data length of the packet to be written to the next block at the address, write the next data to the storage area after the address 2052 (= 2048 + 4).

In this way, in steps S45 to S49, after writing the packet data into the L blocks, the writable flag WR and the readable flag RD are set to predetermined values.

Then, in step S50, the workstation 41 refers to the value of the counter M and
It is determined whether all the areas of M42 (area composed of 512 blocks) have been used. If it is determined that all the areas of the RAM 42 have not been used, step S5 is performed.
In step 1, after incrementing the counter M by 1, the process returns to step S42, and the next area (area composed of 512 blocks) is used in the next write processing.

On the other hand, in step S50, the RAM 42
If it is determined that all the areas have been used, step S
Returning to 41, the counter M is reset to zero, and is used from the beginning of the storage area of the RAM 42 in the next writing process.

Thus, the workstation 41
Writes data of a packet sequentially to each block in a predetermined area of the RAM 42 in one write process.

Next, referring to the flowchart of FIG.
The operation of the encoder 43 according to the second embodiment will be described.

First, in step S61, the encoder 43 counts the value of a counter M for counting the number of areas (in this case, 2 @ 20 bytes = 1 megabyte) of the RAM 42 composed of 512 blocks. Set to zero.

Next, in step S62, the encoder 43 reads the data (1 byte) at the address (M × 2 to the 20th power) of the RAM 42, and in step S63,
It is determined whether or not the value of the second bit (readable flag RD) is a value corresponding to “readable”.
If it is determined that the value of the readable flag RD is a value corresponding to “readable”, the process proceeds to step S64.

On the other hand, if it is determined that the value of the read enable flag RD is not a value corresponding to “read enable”, the process returns to step S62, and the encoder 43 again executes the RAM 4
Data of address 2 (M × 2 to the power of 20) is read out, and in step S63, it is determined whether or not the value of the readable flag RD is a value corresponding to “readable”.
In this way, the encoder 43 waits until the value of the readable flag RD becomes a value corresponding to “readable”. That is, the encoder 43 waits until the workstation 41 ends the writing process.

In the initial state, no data is written in the RAM 42, so that the value of the writable flag WR is set to “writable” so that the workstation 41 can write data to the RAM 42 first. And the value of the readable flag RD is
It is set to “readout disabled”.

Next, in step S64, the encoder 43 calculates the packet number from the third to eighth bits of the address (M × 2 20) and the address (M × 2 20 +1). The number L of blocks to which data is written is read.

Then, in step S65, the encoder 43 sets the value of the counter N for counting the number of blocks from which data is read to zero.

Next, in step S66, the encoder 43 calculates the data written in the block from addresses (M × 2 20 + N × 2048 + 2) and (M × 2 20 + N × 2048 + 3). After reading the length, the data of that length is read from the storage area after the address (M × 2 20 + N × 2048 + 4).
That is, if M = 0 and N = 0, the encoder 4
No. 3 reads the data length from addresses 2 and 3, and reads out the data of that length from the storage area after address 4 (FIG. 6).

In step S67, the encoder 43
Determines whether the value of the counter N is L-1 (whether or not packet data has been read from L blocks). If it is determined that data has been read from L blocks, the process proceeds to step S68. Then, the value of the readable flag RD at the address (M × 2 to the power of 20) is set to a value corresponding to “read disabled”, and the value of the writable flag WR is set to
Set to the value corresponding to "writable".

On the other hand, at step S67, L
If it is determined that data has not been read from this number of blocks, in step S69, the encoder 43 increases the value of the counter N by 1, returns to step S66, and reads the data of the next packet from the next block. .

As described above, after reading the packet data from the L blocks in steps S65 to S69, the writable flag WR and the readable flag RD are set to predetermined values.

Then, in step S70, the encoder 43 processes the read packet.

In step S71, the encoder 43
Refers to the value of the counter M, determines whether all the areas of the RAM 42 (areas composed of 512 blocks) have been used, and determines that all the areas of the RAM 42 have not been used. After the counter M is incremented by 1 in step S72, the process returns to step S62, and the next area (area composed of 512 blocks) is used in the next read processing.

On the other hand, in step S71, the RAM 42
If it is determined that all the areas have been used, step S
Returning to step 61, the counter M is reset to zero, and is used from the beginning of the storage area of the RAM 42 in the next read processing.

As described above, the encoder 43 performs the L operation in the predetermined area of the RAM 42 in one read process.
The packet data is sequentially read from the blocks and processed.

In the above operation, the encoder 43 performs the packet processing in step S70. Instead of the processing in step S70, the encoder 43 performs packet processing for each block after the processing in step S66. May be performed.

As described above, in the second embodiment, the work station 41 and the encoder are managed by managing the RAM 42 for each fixed-length storage area and using the writable flag WR and the readable flag RD. No need for direct communication between 43
Since the write process or the read process for a plurality of blocks is performed at a time, the number of times of referring to each flag is reduced,
Processing speed can be increased.

Next, a third embodiment of the present invention will be described. The third embodiment is the same as the first embodiment except for the method of using the storage area of the RAM 42.
Only the method of using No. 2 will be described.

FIG. 9 shows an example of allocation of storage areas in the RAM 42 according to the third embodiment. The RAM 42 is
It is managed for each fixed-length storage area (block) of 2,048 bytes. And one write process or one
In a single read process, a process of writing data of a predetermined number of packets or a process of reading data of a packet is performed on an area composed of a plurality of (in this case, 512) blocks.

The first address (((j)) of the first block of the j-th area (area composed of 512 blocks)
-1) × 2 (20th power) address) has a writable flag WR (first bit) and a readable flag RD
(The second bit) is stored. The writable flag WR is stored in the RAM 4 by the workstation 41.
2, the value indicating permission or non-permission of writing data to the memory 2, and the readable flag RD holds a value indicating permission or non-permission of reading of data from the RAM 42 by the encoder 43.

Further, the third bit at the head address of each block is used as a final data block flag LB, and the final data block flag LB of the last block to which data is written in one write process is: A value indicating that this is the last block in which data has been written is written. Note that no data is written from the block following the block to the last block (the 512th block).

The fourth to eighth bits of the first address of the first block of each area, the second address of the first block, and the first and second addresses of the blocks other than the first block. Is reserved as a spare area and is not particularly used.

At the third and fourth addresses of each block, the data length of the packet stored in that block is written.

The data of the packet allocated to this block is written in the fifth to last addresses of each block. If the data of the packet is short, the area from the address next to the position where the end of the data is written to the last address of the block is a free area and is not used.

In the storage area of the RAM 42, a total of 512 blocks are stored as one area as 1 area.
It is used in the write process or read process.

Next, the operation of the workstation 41 of the third embodiment will be described with reference to the flowchart of FIG.

First, in step S81, the workstation 41 resets the value of a counter M for counting the number of areas (in this case, 2 to the 20th power byte) of the RAM 42 constituted by 512 blocks to zero. Set.

Next, in step S82, the workstation 41 reads the data (1 byte) at the address (M × 2 to the 20th power) of the RAM 42, and in step S83, the writable flag WR, which is the first bit, is written.
Is determined to be a value corresponding to “writable”, and if it is determined that the value of the writable flag WR is a value corresponding to “writable”, the process proceeds to step S84.

On the other hand, if it is determined that the value of the writable flag WR is not a value corresponding to “writable”, the process returns to step S82, and the workstation 41 again executes
The data at the address (M × 2 to the 20th power) is read from the RAM, and in step S83, the write enable flag WR is read.
Is determined to be a value corresponding to “writable”. Thus, the workstation 41 waits until the value of the writable flag WR becomes a value corresponding to “writable”. That is, the workstation 41
Waits until the encoder 43 finishes the reading process and changes the value of the flag.

In the initial state, no data has been written to the RAM 42, so that the value of the writable flag WR is set to “writable” so that the workstation 41 can write data to the RAM 42 first. And the value of the readable flag RD is
It is set to “readout disabled”.

Next, in step S84, the workstation 41 sets the value of a counter N for counting the number of blocks in which packets are written to zero.

Then, in step S85, the workstation 41 sets (M × 2 to the power of 20 + N × 204)
8) Set the third bit at the address (final data block flag LB) to a value indicating that this block is not the last block. That is, when M = 0 and N = 0, the workstation 41 sets the third bit at address 0 to a predetermined value (that the block is not the last block, as shown in FIG. 9). Value).

In step S86, the workstation 41 writes the length of data to be written in the block at addresses (M × 2 20 + N × 2048 + 2) and (M × 2 20 + N × 2048 + 3). Thereafter, the data of the packet is written into the storage area after the address (M × 2 20 + N × 2048 + 4).

In step S87, the workstation 41 determines whether or not this block is the last block in one write process, and if it is determined that this block is the last block, the process proceeds to step S87.
Go to (88 × 20 × N ×
2048) The value of the last data block flag LB) is set to a value indicating that this block is the last block in one write process.

On the other hand, if it is determined in step S87 that this block is not the last block, in step S89, the workstation 41 returns to step S85 after increasing the value of the counter N by one.
Write the data of the next packet to the next block.

As described above, in steps S85 to S89, packet data is written into a predetermined number of blocks, and the value of the last data block flag LB of the last block is set to a predetermined value.

In step S90, the workstation 41 sets the value of the writable flag WR of the first block to a value corresponding to “writable” and changes the value of the readable flag RD to “readable”. Set to the value corresponding to.

Then, in step S91, the workstation 41 refers to the value of the counter M and
It is determined whether or not all of the available areas (areas composed of 512 blocks) in M42 have been used. If it is determined that not all areas have been used, in step S92, After incrementing the counter M by 1, the process returns to step S82, and the next area is used in the next writing process.

On the other hand, if it is determined in step S91 that all the areas have been used, the process returns to step S81, where the counter M is reset to zero, and the next write processing uses the storage area of the RAM 42 from the beginning.

In this way, the workstation 41
Writes data of a packet sequentially to each block in a predetermined area of the RAM 42 in one write process.

Next, the operation of the encoder 43 of the third embodiment will be described with reference to the flowchart of FIG.

First, in step S101, the encoder 43 sets the value of a counter M for counting the number of areas (in this case, 2 to the 20th power byte) of the RAM 42 constituted by 512 blocks to zero. I do.

Next, in step S102, the encoder 43 reads the data (1 byte) at the address (M × 2 to the 20th power) of the RAM 42, and in step S103, sets the value of the second bit, ie, the value of the readable flag RD. Is determined to be a value corresponding to “Readable”,
If it is determined that the value of the readable flag RD is a value corresponding to “readable”, the process proceeds to step S104.

On the other hand, if it is determined that the value of the readable flag RD is not a value corresponding to “readable”, the process returns to step S 102, and the encoder 43 returns to the RAM again.
The data at address 42 (M × 2 to the power of 20) is read out, and in step S103, it is determined whether or not the value of the readable flag RD is a value corresponding to “readable”. In this way, the encoder 43 waits until the value of the readable flag RD becomes a value corresponding to “readable”. That is, the encoder 43 waits until the workstation 41 completes the reading process and changes the value of the flag.

In the initial state, no data has been written to the RAM 42, so that the value of the writable flag WR is set to “writable” so that the workstation 41 can write data to the RAM 42 first. And the value of the readable flag RD is
It is set to “readout disabled”.

Next, in step S104, the encoder 43 sets the value of a counter N for counting the number of blocks from which data of the packet is read out to zero.

In step S105, the encoder 43 calculates (M × 2 to the power of 20 + N × 2048 + 2)
After reading the length of the data written in the block from the address and the address (M × 2 20 + N × 2048 + 3), (M × 2 20 + N × 2048 + 4)
The data of that length is read from the storage area after the address. That is, when M = 0 and N = 0, the encoder 43 reads the data length from addresses 2 and 3, and reads the data of that length from the storage area after address 4.

At step S106, the encoder 4
3 reads the data at the start address of this block,
By referring to the third bit (final data block flag LB) of the data, it is determined whether or not this block is the last block in one write process, and it is determined that this block is the last block. If it is determined, the process proceeds to step S107, in which the value of the readable flag RD (address (M × 2 20)) of the first block is set to a value corresponding to “read disabled”, and the value of the writable flag WR is set. Is set to a value corresponding to “writable”.

On the other hand, if it is determined in step S106 that this block is not the last block, in step S108, the encoder 43 sets the counter N
Then, the process returns to step S105 to read the data of the next packet from the next block.

As described above, in steps S105, S106 and S108, the data of the packet is read out until the last block is reached while referring to the value of the last data block flag LB of each block.

In step S109, the encoder 43 processes the data of the packet thus read.

In step S110, the encoder 4
3 refers to the value of the counter M to determine whether or not all of the available areas (areas composed of 512 blocks) in the RAM 42 have been used,
When it is determined that all the areas are not used, in step S111, after increasing the counter M by one,
Returning to step S102, in the next reading process,
Use the following areas:

On the other hand, if it is determined in step S110 that all the areas have been used, the process returns to step S101, where the counter M is reset to zero, and the next read processing uses the storage area of the RAM 42 from the beginning.

In this manner, the encoder 43 sequentially reads packets from each block in a predetermined area of the RAM 42 in one read process.

In the above-described operation, the encoder 43 performs the packet processing in step S109, but instead of the processing in step S109, the encoder 43 performs
After the processing in step S105, the packet processing may be performed for each block.

As described above, in the third embodiment, the RAM 42 is managed for each fixed-length storage area, and the workstation 41 and the encoder 41 are managed by using the writable flag WR and the readable flag RD. No need for direct communication between 43
Since the write processing or the read processing for a plurality of blocks is performed at a time, the processing speed can be increased.

Next, a fourth embodiment of the present invention will be described. The fourth embodiment is the same as the first embodiment except for the method of using the storage area of the RAM 42.
Only the method of using No. 2 will be described.

FIG. 12 shows an example of the RAM 42 according to the fourth embodiment. The RAM 42 is managed for each fixed-length storage area (block) of 2,048 bytes. Then, in one writing process or one reading process,
A packet data write process or a packet data read process is performed on an area composed of a plurality of blocks (512 blocks in this case).

At the head address (((j−1) × 2 to the 20th power)) of the head block of the j-th area, a writable flag WR (first bit) and a readable flag RD are set. (The second bit) is stored. The writable flag WR holds a value indicating permission or non-permission of writing of data to the RAM 42 by the workstation 41, and the readable flag RD indicates permission or non-permission of reading of data from the RAM 42 by the encoder 43. Holds the value.

Further, the third bit at the head address of each block is used as a batch processing end flag FN, and after one writing process is completed, the block following the block in which the last data has been written is collected. Processing end flag FN
Is written with a value indicating that one write process has been completed. Data is not written from the block in which the value indicating that one writing process has been completed to the last block in the area is written to the batch processing end flag FN.

The fourth to eighth bits of the first address of the first block and the second address of the first block, and the first and second addresses of the blocks other than the first block are reserved areas. And are not particularly used.

At the third and fourth addresses of each block, the data length of the packet stored in that block is written.

At the fifth to last addresses of each block, data of a packet assigned to the block is written. When the data of the packet is short, the area from the address next to the position where the end of the data is written to the last address of the block is a free area and is not used.

As described above, in the RAM 42, a total of 512 blocks are used as one area in one write process or one read process.

Next, the operation of the workstation 41 of the third embodiment will be described with reference to the flowchart of FIG.

First, in step S121, the work station 41 sets the area of the RAM 42 composed of 512 blocks (in this case, 2 to the power of 20).
Is set to zero.

Next, in step S122, the work station 41 stores (M × 2 to the power of 20) in the RAM.
Data (1 byte) of the address (that is, the first address of the area)
In step S123, it is determined whether the value of the first bit, the writable flag WR, is a value corresponding to “writable”, and the value of the writable flag WR is set to “writable”. If it is determined that the value corresponds to, the process proceeds to step S124.

On the other hand, if it is determined that the value of the writable flag WR is not a value corresponding to “writable”, the process returns to step S122, and the workstation 41 again executes the (M × 2 to the 20th) address of the RAM. Is read, and in a step S123, it is determined whether or not the value of the writable flag WR is a value corresponding to “writable”. In this way, the workstation 41
Waits until the value of the writable flag WR becomes a value corresponding to “writable”.

In the initial state, since no data has been written to the RAM 42, the value of the writable flag WR is set to “writable” so that the workstation 41 can write data to the RAM 42 first. And the value of the readable flag RD is
It is set to “readout disabled”.

Next, in step S124, the workstation 41 sets the value of a counter N for counting the number of blocks in which packet data is written to zero.

Then, in step S125, the workstation 41 sets (M × 2 to the power of 20 + N × 204)
8) Third bit at address (batch processing end flag FN)
(FIG. 12) is set to a value indicating that the writing process has not been completed. That is, when M = 0 and N = 0, the workstation 41 sets a value indicating that the writing process has not been completed to the third bit at address 0.

In step S126, the work station 41 sets (M × 2 to the power of 20 + N × 2048 + 2)
After writing the data length of the packet to be written in the block at the address and the address (M × 2 20 + N × 2048 + 3), (M × 2 20 + N × 2048 + 4)
The data is written to the storage area after the address. That is, M =
0 and N = 0, the workstation 41
Writes the data length at addresses 2 and 3, as shown in FIG. 12, and then writes the data of that length into the storage area after address 4.

At step S127, the workstation 41 increments the value of the counter N by 1, and then proceeds to step S128.

In step S128, the workstation 41 determines whether or not one write process has been completed. If it is determined that the write process has been completed, the process proceeds to step S129, where (M × 2 20 + N × 204
8) The value of the batch processing end flag FN at the address (that is, of the next block) is set to a value indicating that the write processing has been completed.

On the other hand, if it is determined in step S128 that the writing process has not been completed, the process proceeds to step S1.
Returning to step 25, the data of the next packet is written in the next block.

As described above, in steps S125 to S128, packet data is written into a predetermined number of blocks, and when the write processing is completed, the value of the batch processing end flag FN of the next block is changed to the predetermined value. Set to.

In step S130, the workstation 41 sets the value of the writable flag WR of the first block to a value corresponding to "writable" and sets the value of the readable flag RD to "readable". Set to the value corresponding to.

Then, in step S131, the workstation 41 refers to the value of the counter M and
It is determined whether all of the available areas (areas composed of 512 blocks) in the AM 42 have been used, and if it is determined that all the areas have not been used, in step S132, After incrementing the counter M by 1, the process returns to step S122, and the next area is used in the next writing process.

On the other hand, if it is determined in step S131 that all the areas have been used, the process returns to step S121, where the counter M is reset to zero, and the next write processing uses the storage area of the RAM 42 from the beginning.

In this way, the workstation 41
Writes data of a packet sequentially to each block in a predetermined area of the RAM 42 in one write process.

Next, the operation of the encoder 43 of the fourth embodiment will be described with reference to the flowchart of FIG.

First, in step S141, the encoder 43 sets the value of the counter M for counting the number of areas (in this case, 2 to the 20th power byte) of the RAM 42 composed of 512 blocks to zero. I do.

Next, in step S142, the encoder 43 reads the data (1 byte) at the address (M × 2 to the 20th power) of the RAM 42. In step S143, the encoder 43 reads the second bit, ie, the readable flag R.
It is determined whether or not the value of D is a value corresponding to “Readable”. If it is determined that the value of the readable flag RD is a value corresponding to “Readable”, the process proceeds to step S144.

On the other hand, if it is determined that the value of the readable flag RD is not a value corresponding to “readable”, the process returns to step S 142, and the encoder 43 returns to the RAM again.
The data of the address 42 (M × 2 to the power of 20) is read out, and in step S143, it is determined whether or not the value of the readable flag RD is a value corresponding to “readable”. In this way, the encoder 43 waits until the value of the readable flag RD becomes a value corresponding to “readable”.

In the initial state, no data is written in the RAM 42, so that the value of the writable flag WR is set to “writable” so that the workstation 41 can write data to the RAM 42 first. And the value of the readable flag RD is
It is set to “readout disabled”.

Next, in step S144, the encoder 43 sets the value of the counter N for counting the number of blocks from which the data of the packet is read out to zero.

In step S145, the encoder 43 calculates (M × 2 to the power of 20 + N × 2048 + 2)
After reading the data length of the packet written in the block from the address and the address (M × 2 20 + N × 2048 + 3), (M × 2 20 + N × 20)
48 + 4) The data of the length is read from the storage area after the address.

At step S146, the encoder 4
3 increments the value of the counter N by 1 and proceeds to step S1
Go to 47.

In step S147, the encoder 4
3 is (M × 2 to the power of 20 + N × 2048) (ie,
The data at the start address of the block next to the block read in step S145 is read.

In step S148, the encoder 43 refers to the batch processing end flag FN, which is the third bit of the data, and determines that the block read in step S145 is the last block (the last block in which the data is written). It is determined whether or not the block is the last block. If it is determined that the block is the last block, the process proceeds to step S149, where the readability flag RD ((M × 2 to the 20th power) address) of the first block is set. The value is set to a value corresponding to “readout disabled”, and the writable flag W
The value of R is set to a value corresponding to “writable”.

On the other hand, if it is determined in step S148 that the block read in step S145 is not the last block, the process returns to step S145, and the next packet is read from the next block.

As described above, in steps S145 to S148, the data of the packet is read out by referring to the value of the batch processing end flag FN of each block until reaching the last block in which the data is written. .

In step S150, the encoder 43 processes the data of the packet thus read.

At step S151, the encoder 4
3 refers to the value of the counter M to determine whether or not all of the available areas (areas composed of 512 blocks) in the RAM 42 have been used,
If it is determined that all the areas are not used, in step S152, after increasing the counter M by one,
Returning to step S142, in the next reading process,
Use the following areas:

On the other hand, if it is determined in step S151 that all the areas have been used, the process returns to step S141, where the counter M is reset to zero, and the next read processing uses the storage area of the RAM from the beginning.

As described above, the encoder 43 sequentially reads packet data from each block in a predetermined area of the RAM 42 in one read process.

In the above-described operation, the encoder 43 performs the packet processing in step S150, but instead of the processing in step S150,
After the process of step S145, the packet may be processed for each block.

As described above, in the fourth embodiment, the work station 41 and the encoder 41 are managed by managing the RAM 42 for each fixed-length storage area and using the writable flag WR and the readable flag RD. No need for direct communication between 43
Since the write processing or the read processing is performed for a plurality of blocks at a time, the processing speed can be increased.

In the above embodiment, the length of one block is 2,048 bytes and the number of blocks in one area is 512. However, the length of the block and the length of the area are The number is not particularly limited.

Although the above embodiment is applied to a data distribution system, it is needless to say that it can be applied to other systems.

[0192]

As described above, according to the information processing apparatus according to the first aspect and the information processing method according to the fourth aspect,
The first information processing unit writes data to the fixed-length storage area corresponding to the value of the first area in the fixed-length storage area of the predetermined storage unit, and then writes the data in the fixed-length storage area. The first information processing unit changes the value of the first area and the value of the second area, and the second information processing unit responds to the value of the second area in the fixed-length storage area of the storage unit. After reading the data written in the fixed-length storage area, the value of the first area and the value of the second area are changed.
By eliminating the need for communication between the workstation as the first information processing unit and the encoder of the second information processing unit, the cost of the apparatus can be reduced.

According to the information processing apparatus of the fifth aspect and the information processing method of the eighth aspect, the first information processing section stores the first information in the first fixed length storage area of the predetermined storage section. In accordance with the value of the area, the number of fixed-length storage areas is written in the second area of the first fixed-length storage area, and data is written in each fixed-length storage area. The value of the first area and the value of the third area of the storage area are changed, and the second information processing unit responds to the value of the third area in the first fixed-length storage area of the storage unit. The number of fixed-length storage areas written in the second area of the first fixed-length storage area is read, and the data written by the first information processing unit from the fixed-length storage area is read out. Is read, the value of the first area of the first fixed-length storage area and the third Since so as to change the value of the area, a work station and the second is the first information processing unit
By eliminating the need for communication between the encoders of the information processing unit, the cost of the apparatus can be reduced and the processing speed can be improved.

According to the information processing apparatus of the ninth aspect and the information processing method of the twelfth aspect, the first information processing section stores the first fixed-length storage area in the first fixed-length storage area of the predetermined storage section. In accordance with the value of the area, data is sequentially written to a plurality of fixed-length storage areas, a predetermined value is written to a second area of the last fixed-length storage area, and then the first fixed-length storage area is written. Of the first area and the value of the third area are changed, and the second information processing unit sets a plurality of values corresponding to the values of the third area in the first fixed-length storage area of the storage unit. The data written by the first information processing unit is sequentially read from the fixed-length storage area, and after reading the data in accordance with the value of the second area, the data of the first fixed-length storage area is read. Since the value of the first area and the value of the third area are changed, By communication between the workstation and the encoder of the second information processing unit is unnecessary, which is an information processing unit, it is possible to together reduce the cost of the equipment, improve the processing speed.

According to the information processing apparatus of the thirteenth aspect and the information processing method of the sixteenth aspect, the first information processing section stores the first information in the first fixed length storage area of the predetermined storage section. In accordance with the value of the area, a predetermined number of fixed-length storage areas are secured, data is sequentially written from the first fixed-length storage area, and when the end of the data is reached, the next fixed-length storage area is reached. After writing a predetermined value in the second area of the storage area, the value of the first area and the value of the third area of the first fixed-length storage area are changed, and the second information processing unit stores The data written by the first information processing unit is sequentially read from the plurality of fixed-length storage areas in correspondence with the value of the third area in the first fixed-length storage area of the unit, and the second According to the value of the area, the data reading is completed and the first fixed length storage is performed. Since the value of the first area and the value of the third area of the area are changed, communication between the workstation as the first information processing section and the encoder of the second information processing section becomes unnecessary. Thereby, the cost of the apparatus can be reduced and the processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a data distribution system.

FIG. 2 is a block diagram illustrating a configuration of a first embodiment of the information processing apparatus of the present invention.

FIG. 3 is a diagram illustrating an example of allocation of a storage area of a RAM 42 according to the first embodiment.

FIG. 4 is a flowchart illustrating an operation of the workstation 41 according to the first embodiment.

FIG. 5 is a flowchart illustrating the operation of the encoder 43 according to the first embodiment.

FIG. 6 is a diagram illustrating an example of allocation of a storage area of a RAM 42 according to the second embodiment.

FIG. 7 is a flowchart illustrating the operation of a workstation 41 according to the second embodiment.

FIG. 8 is a flowchart illustrating the operation of the encoder 43 according to the second embodiment.

FIG. 9 is a diagram illustrating an example of allocation of a storage area of a RAM according to a third embodiment.

FIG. 10 is a flowchart illustrating an operation of a workstation 41 according to the third embodiment.

FIG. 11 is a flowchart illustrating an operation of an encoder 43 according to the third embodiment.

FIG. 12 is a diagram illustrating an example of allocation of storage areas in a RAM according to a fourth embodiment;

FIG. 13 is a flowchart illustrating an operation of a workstation 41 according to the fourth embodiment.

FIG. 14 is a flowchart illustrating an operation of an encoder 43 according to a fourth embodiment.

FIG. 15 is a block diagram illustrating a configuration example of a conventional information processing apparatus.

[Description of Signs] 1 recipient, 2 information provider, 3 transmitting station, 4
Satellites, 11 modems, 21 modems, 22
Server, 31 information processing device, 41 workstation, 42 RAM, 43 encoder

Claims (16)

[Claims] A storage unit for temporarily storing predetermined data; a first information processing unit for writing data into the storage unit for each fixed-length storage area; A second information processing means for reading data for each long storage area, wherein the first information processing means corresponds to a value of a first area in a fixed length storage area of the storage means. Then, after writing the data to the fixed-length storage area, the value of the first area and the value of the second area of the fixed-length storage area are changed, and the second information processing means includes: After reading data written in the fixed-length storage area by the first information processing means in accordance with the value of the second area in the fixed-length storage area of the storage means, And the second The information processing apparatus characterized by changing the value of frequency. 2. The first information processing means writes a data length in a third area of the fixed-length storage area, and the second information processing means stores the data length in the third area. 2. The information processing apparatus according to claim 1, wherein the data of the length is read by referring to the length of the data. 3. The first information processing means determines a length equal to or less than a length of the fixed-length storage area excluding the first area, the second area, and the third area. 3. The information processing apparatus according to claim 2, wherein the stored data is written to the fixed-length storage area. 4. After the first information processing unit writes data to the fixed-length storage area corresponding to a value of the first area in the fixed-length storage area of the predetermined storage unit, Changing the value of the first area and the value of the second area of the fixed-length storage area; and the second information processing unit executes the second processing in the fixed-length storage area of the storage unit. After reading data written in the fixed-length storage area by the first information processing unit in accordance with the value of the area, the value of the first area and the value of the second area are changed. And an information processing method. 5. A storage unit for temporarily storing predetermined data; a first information processing unit for writing data into the storage unit for each fixed-length storage area; A second information processing means for reading data for each long storage area, wherein the first information processing means comprises: a first area in the first fixed length storage area of the storage means; Corresponding to the value,
A predetermined number of the fixed-length storage areas are secured, the number of the fixed-length storage areas is written in the second area of the first fixed-length storage area, and data is stored in each fixed-length storage area. After writing, the first fixed-length storage area of the first
Changing the value of the third area and the value of the third area, wherein the second information processing means corresponds to the value of the third area in the first fixed length storage area of the storage means, The number of the fixed-length storage areas written in the second area of the first fixed-length storage area is read out, and the number is written by the first information processing means from the fixed-length storage areas. An information processing apparatus for changing the value of the first area and the value of the third area of the first fixed-length storage area after reading the data obtained. 6. The first information processing means writes a length of data in a fourth area of each fixed-length storage area, and the second information processing means writes a data length of each fixed-length storage area. 6. The information processing apparatus according to claim 5, wherein the data of the length is read by referring to a length of the data stored in the fourth area. 7. The fixed-length storage area excluding the first area, the second area, the third area, and the fourth area, wherein the first information processing means has 6. The information processing apparatus according to claim 5, wherein data having a length equal to or less than the length is written to the fixed-length storage area. 8. A first information processing unit, wherein a second area of the first fixed length storage area corresponding to a value of the first area in the first fixed length storage area of the predetermined storage unit is provided. After writing the number of the fixed-length storage areas and writing data to each fixed-length storage area, the value of the first area and the value of the third area of the first fixed-length storage area are written. And the second information processing unit corresponds to the value of the third area in the first fixed length storage area of the storage unit,
Reading the number of the fixed-length storage areas written in the second area of the first fixed-length storage area;
After reading the data written by the first information processing unit from the fixed-length storage areas of that number, the value of the first area and the third area of the first fixed-length storage area are read out. Changing the value of the information processing method. 9. A storage unit for temporarily storing predetermined data; a first information processing unit for writing data to the storage unit for each fixed-length storage area; A second information processing means for reading data for each long storage area, wherein the first information processing means comprises a value of a first area in a first fixed length storage area of the storage means. In response to the above, data is sequentially written to a plurality of fixed-length storage areas, and after a predetermined value is written to a second area of the last fixed-length storage area, the data of the first fixed-length storage area is written. Changing the value of the first area and the value of the third area, the second information processing means corresponding to the value of the third area in the first fixed length storage area of the storage means,
Sequentially reading data written by the first information processing means from the plurality of fixed length storage areas,
According to a feature of the present invention, after reading data is completed, the value of the first area and the value of the third area of the first fixed-length storage area are changed according to the value of the second area. Information processing device. 10. The first information processing means writes a data length in a fourth area of each fixed-length storage area, and the second information processing means writes the data length of each fixed-length storage area. 10. The information processing apparatus according to claim 9, wherein the data of the length is read by referring to the length of the data stored in the fourth area. 11. The first information processing means comprises:
And writing data having a length equal to or less than the length of the fixed-length storage area excluding the second area, the second area, the third area, and the fourth area to the fixed-length storage area. The information processing apparatus according to claim 9, wherein: 12. A first information processing unit sequentially writes data to a plurality of fixed-length storage areas in accordance with a value of a first area in a first fixed-length storage area of a predetermined storage unit. Writing a predetermined value in a second area of the last fixed-length storage area, and then writing the first value in the first fixed-length storage area.
Changing the value of the area and the value of the third area; and the second information processing unit, corresponding to the value of the third area in the first fixed length storage area of the storage unit, The data written by the first information processing unit is sequentially read from a plurality of fixed-length storage areas, and after the data reading is completed in accordance with the value of the second area, the first fixed Changing the value of the first area and the value of the third area of the long storage area. 13. A storage unit for temporarily storing predetermined data; a first information processing unit for writing data to the storage unit for each fixed-length storage area; A second information processing means for reading data for each long storage area, wherein the first information processing means comprises a value of a first area in a first fixed length storage area of the storage means. In response to the above, a predetermined number of fixed-length storage areas are secured, data is sequentially written from the first fixed-length storage area, and when the end of data is reached, the next fixed-length storage area is reached. After writing a predetermined value in the second area, the value of the first area and the value of the third area in the first fixed-length storage area are changed, and the second information processing means The first fixed length storage area of said storage means Corresponding to the value of definitive said third region,
Sequentially reading data written by the first information processing means from the plurality of fixed-length storage areas, and terminating the data reading according to the value of the second area;
An information processing apparatus, wherein a value of the first area and a value of the third area of the first fixed-length storage area are changed. 14. The first information processing means writes a data length in a fourth area of each fixed-length storage area, and the second information processing means stores a data length of each fixed-length storage area. 14. The information processing apparatus according to claim 13, wherein the data of the length is read by referring to the length of the data stored in the fourth area. 15. The first information processing means, wherein:
Area, the second area, the third area, and data having a length equal to or less than the length of the fixed-length storage area excluding the fourth area are stored in the fixed-length storage area. The information processing apparatus according to claim 13, wherein the information is written. 16. The first information processing unit secures a predetermined number of fixed-length storage areas corresponding to a value of a first area in an initial fixed-length storage area of a predetermined storage unit, Data is sequentially written from the first fixed-length storage area. When the end of the data is reached, a predetermined value is written to the second area of the next fixed-length storage area, and then the first fixed-length storage area is written. Changing the value of the first area and the value of the third area of the long storage area, and the second information processing unit executes the third processing in the first fixed length storage area of the storage unit. In accordance with the value of the area, the data written by the first information processing unit is sequentially read out from the plurality of fixed-length storage areas, and the data is read out in accordance with the value of the second area. Finished, the value of the first area of the first fixed length storage area The information processing method characterized by comprising the step of changing the value of pre said third region.