JP3503725B2 - Information processing apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and method, and in particular, after the first information processing unit writes data in the storage unit according to the value of the first area of the storage unit, The value of the first area and the value of the second area of the storage unit are changed, and the second information processing unit reads the data written in the storage unit according to the value of the second area of the storage unit. After
The present invention relates to an information processing apparatus and method for changing a value of a first area and a value of a second area of a storage unit.

[0002]

2. Description of the Related Art With the recent progress in information processing technology, various information processing apparatuses that perform predetermined processing on data have been developed.

For example, when data communication is performed between two information processing units operating with different clock signals, a memory is used to reduce the difference in processing speed between the two information processing units. Therefore, data is often exchanged.

FIG. 15 shows an example of an information processing apparatus having such two information processing units. In this information processing apparatus, the workstation (WS) 61 is
When the data transmitted via the computer network is received, the data is written in a predetermined storage area of the RAM 62, and the writing of a predetermined amount of data is completed, the corresponding information is transmitted to the encoder 63.
At this time, if necessary, the WS 61 determines the address (address) where the data is written and the length of the data by the encoder 6
Send to 3.

When the encoder 63 receives the information, the encoder 63 reads the data written by the workstation 61 from the RAM 62, and when the data reading is completed, the encoder 63 transmits the corresponding information to the workstation 61. And workstation 61
Writes the next data in the RAM 62. At this time, the encoder 63, for example, with respect to the read data,
If the compression process is performed and the writing process of the next data to the RAM 62 by the workstation 61 is completed, the next data is read.

In this way, the workstation 61
Sequentially supplies a predetermined amount of data to the encoder 63 via the RAM 62.

[0007]

However, in the above-mentioned apparatus, the workstation 61 is the RAM 6
Since the information corresponding to the end of the writing of the data to the data No. 2 is transmitted to the encoder 63, and the encoder 63 needs to transmit the information corresponding to the end of the reading of the data from the RAM 62 to the workstation 61. There is a problem that it is difficult to reduce the cost of the device because an interface or the like for transmitting or receiving is required.

Further, the above-mentioned information transmission / reception is required every time a predetermined amount of data is transmitted or received, which makes it difficult to increase the data processing speed.

The present invention has been made in view of such a situation, and the information of the end of data writing and the end of reading is written in a predetermined storage area of the RAM so that the data is written between the workstation and the encoder. By making communication unnecessary, the cost of the device can be reduced and the processing speed can be improved.

[0010]

[0011]

[0012]

According to another aspect of the present invention, there is provided an information processing apparatus, wherein the first information processing means is provided in the storage means and is provided in the first storage area of a plurality of storage areas. According to the value of the first area, the number of storage areas for writing data is written in the second area of the first storage area, and after writing the data in each storage area, The value of the first area and the value of the third area are changed, and the second information processing means sets the second information of the first storage area according to the value of the third area in the first storage area of the storage means. After reading the number of storage areas written in the area and reading the data written by the first information processing means from the number of storage areas, the first fixed-length storage area of the first area is read. Characterized by changing the value and the value of the third region To.

The information processing method according to claim 6 is the first
The information processing unit of the first storage unit, which is provided in a predetermined storage unit
In the second area of the first storage area, depending on the value of the area
Writing the number of storage areas in which data is written, writing the data to each storage area, and then changing the value of the first area and the value of the third area of the first storage area; The information processing unit sets the second storage area of the first storage area according to the value of the third storage area of the first storage area of the storage unit.
The number of storage areas written in the area is read, and the data written by the first information processing unit is read from the number of storage areas, and then the first area of the first fixed-length storage area. And the value of the third region are changed.

The information processing apparatus according to claim 7 is the first
The information processing means of (1) sequentially writes data to the plurality of storage areas in accordance with the value of the first area in the first storage area of the areas configured by the plurality of storage areas, After writing a predetermined value to the second area of the last storage area of the areas configured by the first storage area, the value of the first area and the value of the third area of the first storage area are changed, The second information processing means sequentially reads the data written by the first information processing means from the plurality of storage areas according to the value of the third area in the first storage area of the storage means, and then the second information processing means According to the value of the area, the value of the first area and the value of the third area of the first storage area are changed after the data reading is completed.

The information processing method according to claim 8 is the first
The information processing unit of the first storage unit, which is provided in a predetermined storage unit
Data is sequentially written to the plurality of storage areas according to the value of the area, and a predetermined value is written to the second area of the last storage area of the plurality of storage areas, and then the first Changing the value of the first area and the value of the third area of the storage area, the second information processing unit sets the value of the third area in the first storage area of the storage unit to Accordingly, the data written by the first information processing unit is sequentially read from the plurality of storage areas, and the first storage is performed after the data reading is completed according to the value of the second area. Changing the value of the first region and the value of the third region of the region.

[0016]

[0017]

[0018]

[0019]

[0020] The information processing apparatus according to claim 1, the first information processing means, provided in the storage means, the first region in the first storage area of the area comprised of a plurality of storage areas Depending on the value, the number of storage areas for writing data is written in the second area of the first storage area, after writing the data in each storage area, the value of the first area of the first storage area And change the value of the third area,
The second information processing means reads the number of storage areas written in the second area of the first storage area according to the value of the third area in the first storage area of the storage means,
After reading the data written by the first information processing means from the number of storage areas, the value of the first area and the value of the third area of the first fixed-length storage area are changed.

[0021] An information processing method according to claim 6, the first information processing unit is provided in a predetermined storage unit,
According to the value of the first area in the first storage area of the areas configured by a plurality of storage areas, the number of storage areas for writing data is written in the second area of the first storage area, and each storage area is written. After writing the data to the area, the value of the first area and the value of the third area of the first storage area are changed, and the second information processing unit sets the third value in the first storage area of the storage unit. The number of storage areas written in the second area of the first storage area is read according to the value of the area,
After reading the data written by the first information processing unit from the number of storage areas, the value of the first area and the value of the third area of the first fixed-length storage area are changed.

In the information processing apparatus according to the seventh aspect , the first information processing means includes a first area of a first storage area of a plurality of storage areas provided in the storage means. According to the value, the data is sequentially written to the plurality of storage areas, and after writing the predetermined value to the second area of the last storage area of the plurality of storage areas,
The value of the first area and the value of the third area of the first storage area are changed, and the second information processing means sets a plurality of values in accordance with the value of the third area of the first storage area of the storage means. The data written by the first information processing means is sequentially read from the storage area, and after the reading of the data is completed according to the value of the second area, the value of the first area of the first storage area is read. And the value of the third area is changed.

In the information processing method according to claim 8 , the first information processing section is provided in a predetermined storage section,
Data is sequentially written to the plurality of storage areas according to the value of the first area in the first storage area of the plurality of storage areas, and the last storage area of the plurality of storage areas is written. After writing a predetermined value to the second area of the first fixed-length storage area, the value of the first area and the third area of the first fixed-length storage area are changed, and the second information processing unit The data written by the first information processing unit is sequentially read from the plurality of storage areas according to the value of the third area in the first storage area, and the data of the second area is read according to the value of the second area. After the reading is completed, the value of the first area and the value of the third area of the first storage area are changed.

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

Figure 1 DETAILED DESCRIPTION OF THE INVENTION shows an example of the configuration of a data distribution system. In this system, the receiver 1 sends an instruction to the transmitting station 2 or the information provider 3 via the telephone line using the modem 11 so that desired data may be distributed. Then, the receiver 1 receives the data distributed in response to the instruction at the receiving device 12 via the antenna 13.

When the information provider 2 receives an instruction from the receiver 1 through the modem 21, the information provider 2 outputs the instruction to the server 22 which compresses and holds the instructed data. Then, the server 22 is configured to transmit the instructed data to the transmitting station 3 via a computer network such as the Internet.

The transmitting station 3 is an information processing apparatus 31 which is an embodiment of the present invention, receives data (packet) transmitted from the information provider 2 via a computer network, and receives the data, for example, in the MPEG2 system. After compressing with, the compressed data (data to be delivered to the recipient 1)
The data is output to the transmission device 33 via the multiplexer 32. Then, the transmitting device 33 transmits the data to the artificial satellite 4 via the antenna 34, and causes the artificial satellite 4 to deliver the data.

Further, the transmitting station 3 uses the modem 35 to set the receiver 1
In response to the instruction, the data held by the server 36 of the transmitting station 3 is read out, compressed by the encoder 37, and then the data is supplied to the transmitting device 33 via the multiplexer 32. The data is transmitted to the artificial satellite 4 via 34.

The artificial satellite 4 receives data from the transmitting station 3 and distributes the data.

FIG. 2 shows the configuration of the information processing apparatus 31 which is the first embodiment of the information processing apparatus of the present invention.

The workstation (WS) 41 (first information processing means) is connected to the computer network to which the information provider 2 is connected.
The packet including the data transmitted from the server 22 is received, and the data of the packet is written in the RAM 42 according to the state (flag state) of a predetermined storage area of the RAM 42 (storage means). .

The RAM 42 holds the packet data written by the workstation 41.

FIG. 3 shows an example of allocation of the storage area of the RAM 42. The RAM 42 is managed for each fixed-length storage area (in this case, 2,048 bytes) longer than the maximum packet length. For example, I on the Internet
In Ethernet, which is one of the media for transmitting the packet corresponding to the P protocol, the maximum length of the packet is 1,526 bytes (of which, the data portion excluding the header portion is 1, 500 bytes).

A writable flag WR (first bit) and a readable flag RD (second) at the head address (((i-1) * 2048) address of the i-th fixed-length storage area) The second bit) is stored. The writable flag WR indicates the RA by the workstation 41.
The readable flag RD holds a value indicating permission or prohibition of data writing to M42,
3 holds a value indicating permission or non-permission of reading data from the RAM 42.

Next, at the third ((i-1) × 2048 + 2) address and the fourth ((i-1) × 2048 + 3) address of each fixed-length storage area of the RAM 42, the (third) The length (byte length) of the data to be stored in the (i-th) fixed-length storage area is written.

Then, the packet data is written from the fifth ((i-1) * 2048 + 4) address to the last ((i-1) * 2048 + 2047) address of each fixed-length storage area of the RAM 42. . That is, a maximum of 2,044 bytes of data can be written in each fixed-length storage area. When the packet data is short, the area from the address next to the position where the end of the data is written to the last address ((i-1) × 2048 + 2047) is a free area and is not used.

Encoder 43 (second information processing means)
Corresponds to the state of a predetermined storage area of the RAM 42 (state of the flag) from the RAM 42 to the workstation 4
After reading the packet data written by 1 and converting the packet data into the data held by the server 22 of the information provider 2, the data is further compressed by, for example, the MPEG2 method, and then compressed. Is output to the multiplexer 32.

Next, referring to the flow chart of FIG.
The operation of the workstation 41 of the first embodiment will be described.

First, in step S1, the workstation 41 stores the packet data in a storage area (fixed length storage area) (in this case, the fixed length is 2,
The value of the counter N that specifies 048 bytes) is set to zero.

Next, in step S2, the workstation 41 reads the data (1 byte) at the address (N × 2048) (hexadecimal number (N × 800H)) of the RAM 42. That is, when N = 0, the workstation 41 reads the data at address 0 in the RAM 42 (FIG. 3).

Then, in step S3, the workstation 41 reads out the first bit (writable flag WR) of the data at the address (N × 2048).
Value is checked to determine whether the value of the flag WR is a value corresponding to "writeable", and when it is determined that the value of the flag WR is a value corresponding to "writeable", step S4 Proceed to.

On the other hand, if it is determined in step S3 that it is not in the "write enabled" state, the process returns to step S2, and the workstation 41 again (N × 204).
8) Read the address data. In this way, the workstation 41 determines that the value of the writable flag WR is
Until the value corresponding to "writeable" is reached, step S2
And it waits in step S3. That is, a process of reading packet data by the encoder 43 (described later)
Wait until the end.

In the initial state, since the data is not written in the RAM 42, first, the value of the writable flag WR is set to "writable" so that the workstation 41 can write the data in the RAM 42. ", And the value of the readable flag RD is
It is set to "Unreadable".

Then, in step S4, the workstation 41 stores (N × 2048 + 2) in the RAM 42.
After writing the data length of the packet to be written to the address and the address (N × 2048 + 3), (N × 2048 +
4) Write the packet data in the storage area after the address. That is, when N = 0, as shown in FIG. 3, the workstation 41 writes the data length at addresses 2 and 3, and then writes the data at addresses 4 and thereafter.

Next, in step S5, the workstation 41 writes a value corresponding to "unwritable" into the first bit (writable flag WR) of the address (N × 2048) of the RAM 42, and ( N ×
A value corresponding to "readable" is written in the second bit (readable flag RD) of the address 2048).
That is, when N = 0, the workstation 41
A predetermined value is written in the first bit and the second bit of address 0, respectively.

Then, in step S6, the work station 41 refers to the value of the counter N and refers to the RAM.
It is determined whether all 42 storage areas have been used, and RA
When it is determined that the storage area of M42 is completely used (when it is determined that the storage area of the next 2,048 bytes cannot be secured), the process returns to step S1 and the counter N
Is reset to zero and the RAM 42 is used sequentially from the beginning.

On the other hand, when the workstation 41 determines in step S6 that the next storage area of 2,048 bytes can be secured, it increments the counter N by 1 in step S7, and then, in step S2.
Returning to step S2 to step S5, the process of writing the data of the next packet to the next 2,048 byte storage area is performed. For example, when N = 0, the workstation 41 sets the value of the counter N to 1 in step S7, and in step S2 to step S5, performs writing processing to the 2,048-byte storage area starting from the 2048th address. To do.

In this way, the workstation 41
Sequentially writes the packet data in the RAM 42 into each storage area of 2,048 bytes.

Next, referring to the flowchart of FIG.
The operation of the encoder 43 of the information processing apparatus 31 of this embodiment will be described.

First, in step S1, the encoder 43 determines the value of the counter N that specifies the storage area (fixed length storage area) from which packets are read (in this case, the fixed length is 2,048 bytes). Is set to zero.

Next, in step S22, the encoder 43 reads the data (8 bits) at the address (N × 2048) (hexadecimal number (N × 800H)) of the RAM 42. That is, when N = 0, the encoder 43
Reads the data at address 0 in RAM 42 (FIG. 3).

Then, in step S23, the encoder 43 refers to the value of the second bit (readable flag RD) of the read (N × 2048) data, and the value of the flag RD is "readable". If it is determined that the value of the flag RD is a value corresponding to "readable", then step S2
Go to 4.

On the other hand, if it is determined in step S23 that it is not in the "readable" state, the process returns to step S22, and the encoder 43 again reads the data at the address (N × 2048). In this way, the encoder 43
Waits in steps S22 and S23 until the value of the readable flag RD reaches the value corresponding to "readable". That is, workstation 4
It waits until the writing process of the packet data by 1 is completed.

In the initial state, since the data is not written in the RAM 42, first, the value of the writable flag WR is set to "writable" so that the workstation 41 can write the data in the RAM 42. ", And the value of the readable flag RD is
It is set to "Unreadable".

Then, in step S24, the encoder 43 reads the data length from the (N × 2048 + 2) address and the (N × 2048 + 3) address of the RAM 42, and then from the storage area after the (N × 2048 + 4) address. , Read the packet of that length. That is, when N = 0, the encoder 43 reads the data lengths from the addresses 2 and 3, and from the storage area at the address 4 and thereafter,
Read the data of that length.

Next, in step S25, the encoder 43 writes a value corresponding to "non-readable" into the second bit (readable flag RD) of the (N × 2048) address of the RAM 42, and (N × 204
8) 1st bit of address (writable flag W
In R), write a value corresponding to “writeable”.

In step S26, the encoder 43 processes the read packet data (converts packetized data into original data,
Processing for compressing the data).

Next, in step S27, the encoder 43 refers to the value of the counter N to determine whether or not the entire storage area of the RAM 42 is used, and when it is determined that the entire storage area of the RAM 42 is used. (Step S
24 and the fixed-length storage area processed in step S25 is determined to be the last fixed-length storage area of the RAM 42), the process returns to step S21, the counter N is reset to zero, and the first storage area of the RAM 42 is reset. The packet is read again.

On the other hand, the encoder 43 determines in step S27.
In step S24, when it is determined that the fixed-length storage area processed in step S25 is not the last fixed-length storage area, the counter N is incremented by 1 in step S28, and the process returns to step S22. In S22 to S25, the process of reading the data of the next packet from the storage area of the next 2,048 bytes is performed. For example, when N = 0, the encoder 43 sets the value of the counter N to 1 in step S28, and in steps S22 to S25,
A read process is performed on the next storage area starting from the 2048th address.

In this way, the encoder 43 is
The packet data is sequentially read from the fixed-length storage area of M42, and the packet data is processed.

As described above, in the first embodiment, the RAM 42 is managed for each fixed-length storage area, and the writing process and the reading process with respect to the RAM 42 are performed by using the writable flag WR and the readable flag RD. By controlling the processing, direct communication between the workstation 41 and the encoder 43 is unnecessary.

Since one packet of data is written in one fixed-length storage area, there is no need to perform processing such as data division, and the workstation 41 promptly receives the data received via the computer network. , RAM 42 can be written.

Next, a second embodiment of the present invention will be described. The second embodiment is the same as the first embodiment except the method of using the storage area of the RAM 42, so the RAM 4
Only the usage method of 2 will be described.

FIG. 6 shows an example of allocation of storage areas of the RAM 42 of the second embodiment. RAM42 is
It is managed for each fixed-length storage area (block) of 2,048 bytes. And a predetermined number (in this case 512
Area (2 20 bytes =
1 for 512 x 2048, or 1 megabyte)
Write processing or read processing is performed once. Then, in the writing process, the area (51
The data of the packet is written in a predetermined number of blocks out of the two blocks. In the read process, packet data is read from a predetermined number of blocks in the area.

The start address of the start block of the j-th area (area composed of 512 blocks) (((j
−1) × 2 to the 20th address)), the writable flag WR (first bit) and the readable flag RD
The (second bit) is stored. The writable flag WR is stored in the RAM 4 by the workstation 41.
2 holds a value indicating permission or prohibition of writing of data to 2, and the readable flag RD holds a value indicating permission or prohibition of reading of data from the RAM 42 by the encoder 43.

At the third to eighth bits of the head address of the head block of the j-th area and the second address of the head block, the packet data in this area is stored. The number of blocks to write is written.

Then, the third address of the i-th block in the j-th area (((j-1) × 2 to the 20th power +
(I−1) × 2048 + 2) address and the fourth address (((j−1) × 2 to the 20th power + (i−1) × 2048 +)
At (3) address), the data length of the packet to be written in the (i-th) block is written.

Fifth address of block of RAM 42 (((j-1) × 2 to the 20th power + (i-1) × 2048 +
4) address to the last address (((j-1) * 2 to the 20th power + (i-1) * 2048 + 2047) address), the data of this (i-th) packet is written. When the packet data is short, the area from the address next to the position where the end of the packet is written to the last address of the block is a free area and is not used.

As described above, in the RAM 42, a total of 512 blocks are used as one area in one writing process or one reading process.

Next, referring to the flow chart of FIG.
The operation of the workstation 41 of the second embodiment will be described.

First, in step S41, the workstation 41 determines the area of the RAM 42, which is composed of 512 blocks (in this case, 2 20 bytes = 1)
The value of the counter M that counts the number of megabytes) is set to zero.

Next, in step S42, the workstation 41 reads the data (1 byte) of the address (M × 2 to the 20th power) (hexadecimal number, M × 100000H) of the RAM 42, and in step S43, the data is read. It is determined whether or not the value of the first bit (writeable flag WR) is a value corresponding to “writeable”, and it is determined that the value of the writeable flag WR is a value corresponding to “writeable”. If so, the process proceeds to step S44. That is, when M = 0, the workstation 41 determines 0
The address data is read (Fig. 6).

On the other hand, if it is determined that the value of the writable flag WR is not a value corresponding to "writable", the process returns to step S42, and the workstation 41 again
The data at the address (M × 2 to the 20th power) of the RAM 42 is read out, and the writable flag WR is read in step S43.
It is determined whether the value of is a value corresponding to "writeable". In this way, the workstation 41 waits until the value of the writable flag WR becomes the value corresponding to “writable”. That is, the workstation 43
Waits until the encoder 43 finishes the reading process and changes the value of the flag.

In the initial state, since no data is written in the RAM 42, first, the value of the writable flag WR is set to "writeable" so that the workstation 41 can write the data in the RAM 42. ", And the value of the readable flag RD is
It is set to "Unreadable".

Next, in step S44, the workstation 41 sends a packet to the third bit to the eighth bit of the address (M × 2 20), and the address (M × 2 20 +1). Write the number L of blocks (L ≦ 512) in which the data of (1) is written.

Then, in step S45, the workstation 41 sets the value of the counter N for counting the number of blocks in which the packet data is written to zero.

Next, in step S46, the workstation 41 calculates (M × 2 to the 20th power + N × 2048 +).
2) Address and (M x 2 to the 20th power + N x 2048 + 3)
After writing the data length of the packet to be written in the block to the address, (M × 2 20 + N × 2048 +
4) Write data in the storage area after the address.

For example, when M = 0 and N = 0, the workstation 41 operates as shown in FIG.
After writing the data length of the packet to be written in the first block at the address and the address 3, the data is written in the storage area at the address 4 and thereafter.

Then, in step S47, the workstation 41 determines whether or not the value of the counter N has reached L−1 (whether or not the packet data has been written in the L blocks), and the workstation 41 When it is determined that the packet data is written in the block, the process proceeds to step S48, and the writable flag WR at the address (M × 2 to the 20th power)
Is set to a value corresponding to "write disabled", and the value of the readable flag RD is set to a value corresponding to "read enabled".

On the other hand, in step S47, L
If it is determined that the packet data has not been written to the blocks, the workstation 41 increments the value of the counter N by 1 in step S49, and then returns to step S46 to write the next packet to the next block. Write the data. For example, when M = 0 and N = 0, the workstation 41 sets the value of the counter N to 1 and then, after step S46, 2050.
(= 2048 + 2) and 2051 (= 2048 +)
3) After writing the data length of the packet to be written in the next block in the address, write the next data in the storage area after the address 2052 (= 2048 + 4).

In this way, in steps S45 to S49, after writing the packet data in the L blocks, the writable flag WR and the readable flag RD are set to predetermined values.

Then, in step S50, the workstation 41 refers to the value of the counter M,
If it is determined whether or not all areas of M42 (areas composed of 512 blocks) have been used, and it is determined that all areas of RAM 42 are not used, step S5
In 1, the counter M is incremented by 1, and then the process returns to step S42 to use the next area (area composed of 512 blocks) in the next writing process.

On the other hand, in step S50, the RAM 42
If it is determined that all areas of
Returning to 41, the counter M is reset to zero, and is used from the beginning of the storage area of the RAM 42 in the next writing process.

In this way, the workstation 41
In one writing process, the packet data is sequentially written in each block in a predetermined area of the RAM 42.

Next, referring to the flowchart of FIG.
The operation of the encoder 43 of the second embodiment will be described.

First, in step S61, the encoder 43 sets the value of the counter M for counting the number of areas (in this case, 2 20 bytes = 1 megabyte) of 512 blocks of the RAM 42. Set to zero.

Next, in step S62, the encoder 43 reads the data (1 byte) at the address (M × 2 to the 20th power) of the RAM 42, and in step S63
It is determined whether or not the value of the second bit (readability flag RD) is a value corresponding to “readable”,
When it is determined that the value of the readable flag RD is a value corresponding to "readable", the process proceeds to step S64.

On the other hand, when it is determined that the value of the readable flag RD is not a value corresponding to "readable", the process returns to step S62, and the encoder 43 re-enters the RAM4.
The data at address 2 (M × 2 to the 20th power) is read, and in step S63, it is determined whether or not the value of the readable flag RD is a value corresponding to “readable”.
In this way, the encoder 43 waits until the value of the readable flag RD becomes the value corresponding to “readable”. That is, the encoder 43 waits until the workstation 41 finishes the writing process.

In the initial state, since no data is written in the RAM 42, first, the value of the writable flag WR is set to "writable" so that the workstation 41 can write the data in the RAM 42. ", And the value of the readable flag RD is
It is set to "Unreadable".

Next, in step S64, the encoder 43 reads the packet from the third bit to the eighth bit of the address (M × 2 20), and the address (M × 2 20 +1). The number L of blocks in which data is written is read.

Then, in step S65, the encoder 43 sets the value of the counter N, which counts the number of blocks from which data is read, to zero.

Next, in step S66, the encoder 43 receives the data written in the block from the addresses (M × 2 20 + N × 2048 + 2) and (M × 2 20 + N × 2048 + 3). After the length is read, the data of that length is read from the storage area after the address (M × 2 to the power of 20 + N × 2048 + 4).
That is, when M = 0 and N = 0, the encoder 4
3 reads out the data length from the 2nd and 3rd addresses, and reads out the data of that length from the 4th and subsequent storage areas (FIG. 6).

In step S67, the encoder 43
Determines whether the value of the counter N is L−1 (whether packet data is read from L blocks), and if it is determined that data is read from L blocks, the process proceeds to step S68. Then, the value of the readable flag RD at the address (M × 2 to the 20th power) is set to a value corresponding to “unreadable”, and the value of the writable flag WR is set to
Set to the value corresponding to "writable".

On the other hand, in step S67, L
When it is determined that the data has not been read from the blocks, the encoder 43 increments the value of the counter N by 1 in step S69, and then returns to step S66 to read the data of the next packet from the next block. .

In this way, in steps S65 to S69, after the packet data is read from the L blocks, the writable flag WR and the readable flag RD are set to predetermined values.

Then, in step S70, the encoder 43 processes the read packet.

In step S71, the encoder 43
Refers to the value of the counter M to determine whether or not all the areas of the RAM 42 (areas composed of 512 blocks) are used, and when it is determined that all the areas of the RAM 42 are not used After incrementing the counter M by 1 in step S72, the process returns to step S62, and the next area (area composed of 512 blocks) is used in the next reading process.

On the other hand, in step S71, the RAM 42
If it is determined that all areas of
Returning to 61, the counter M is reset to zero, and is used from the beginning of the storage area of the RAM 42 in the next read processing.

In this way, the encoder 43 can store the L of a predetermined area of the RAM 42 in one read process.
Packet data is sequentially read from each block and processed.

In the above-mentioned operation, the encoder 43 performs the packet processing in step S70. However, instead of the processing in step S70, the packet is processed for each block after the processing in step S66. You may make it perform the process of.

As described above, in the second embodiment, the RAM 42 is managed for each fixed-length storage area, and the writable flag WR and the readable flag RD are used to make the workstation 41 and the encoder. It eliminates the need for direct communication between 43 and 1
Since the writing process or the reading process for a plurality of blocks is performed by the number of times, the number of times each flag is referred to is reduced,
The processing speed can be increased.

Next, a third embodiment of the present invention will be described. The third embodiment is the same as the first embodiment except for the method of using the storage area of the RAM 42, so the RAM 4
Only the usage method of 2 will be described.

FIG. 9 shows an example of allocation of storage areas of the RAM 42 of the third embodiment. RAM42 is
It is managed for each fixed-length storage area (block) of 2,048 bytes. And one writing process or 1
Through a single read process, a predetermined number of packet data write processes or packet data read processes are performed on an area composed of a plurality of (512 in this case) blocks.

The head address (((j
−1) × 2 to the 20th address)), the writable flag WR (first bit) and the readable flag RD
The (second bit) is stored. The writable flag WR is stored in the RAM 4 by the workstation 41.
2 holds a value indicating permission or prohibition of writing of data to 2, and the readable flag RD holds a value indicating permission or prohibition of reading of data from the RAM 42 by the encoder 43.

Further, the third bit of the head address of each block is used as the final data block flag LB, and the final data block flag LB of the final block in which data is written in one writing process, A value indicating that it is the last block in which data is written is written. It should be noted that no data is written from the block next to the block to the last block (512th block).

The fourth to eighth bits of the head address of the head block of each area and the second address of the head block, and the head address and the second address of blocks other than the head The address of is reserved as a spare area and is not particularly used.

At the third and fourth addresses of each block, the data length of the packet stored in that block is written.

The data of the packet assigned to this block is written at the fifth address to the last address of each block. When the packet data is short, the area from the address next to the position where the end of the data is written to the last address of the block is an empty area and is not used.

In the storage area of the RAM 42, a total of 512 blocks are treated as one area, and
It is used in one write process or read process.

Next, the operation of the workstation 41 of the third embodiment will be described with reference to the flowchart of FIG.

First, in step S81, the workstation 41 sets the value of the counter M for counting the number of areas (in this case, 2 20 bytes) of the RAM 42, which is composed of 512 blocks, to zero. Set.

Next, in step S82, the workstation 41 reads the data (1 byte) at the address (M × 2 to the 20th power) of the RAM 42, and in step S83, the writable flag WR which is its first bit.
Is determined to be a value corresponding to "writable", and if it is determined that the value of the writable flag WR is a value corresponding to "writable", the process proceeds to step S84.

On the other hand, if it is determined that the value of the writable flag WR is not a value corresponding to "writable", the process returns to step S82, and the workstation 41 again
The data at the address (M × 2 to the 20th power) of the RAM 42 is read out, and the writable flag WR is read in step S83.
It is determined whether the value of is a value corresponding to "writeable". In this way, the workstation 41 waits until the value of the writable flag WR becomes the value corresponding to “writable”. That is, the workstation 41
Waits until the encoder 43 finishes the reading process and changes the value of the flag.

In the initial state, since no data is written in the RAM 42, first, the value of the writable flag WR is set to "writable" so that the workstation 41 can write the data in the RAM 42. ", And the value of the readable flag RD is
It is set to "Unreadable".

Next, in step S84, the workstation 41 sets the value of the counter N for counting the number of blocks to write the packet to zero.

Then, in step S85, the workstation 41 determines (M × 2 to the 20th power + N × 204).
8) Set the third bit of the address (final data block flag LB) to a value indicating that this block is not the last block. That is, when M = 0 and N = 0, the workstation 41, as shown in FIG. 9, determines that the third bit of the address 0 has a predetermined value (this block is not the last block). Value).

In step S86, the workstation 41 writes the length of the data to be written in the block into the addresses (M × 2 20 + N × 2048 + 2) and (M × 2 20 + N × 2048 + 3). After that, the packet data is written in the storage area starting from the address (M × 2 to the 20th power + N × 2048 + 4).

In step S87, the workstation 41 determines whether or not this block is the last block in one write processing, and if it is determined that this block is the last block, step S87
Proceed to 88 and ((M × 2 20 + N ×
The value of the last data block flag LB (address 2048) is set to a value indicating that this block is the last block in one write process.

On the other hand, when it is determined in step S87 that this block is not the last block, the workstation 41 increments the value of the counter N by 1 in step S89, and then returns to step S85.
The data of the next packet is written in the next block.

In this way, in steps S85 to S89, the packet data is written in a predetermined number of blocks, and the value of the final data block flag LB of the last block is set to a predetermined value.

Further, in step S90, the workstation 41 sets the value of the writable flag WR of the leading block to a value corresponding to "unwritable" and sets the value of the readable flag RD to "readable". Set to the value corresponding to.

Then, in step S91, the workstation 41 refers to the value of the counter M and sets RA
If it is determined whether or not all areas of the available area (area composed of 512 blocks) in M42 are used, and it is determined that all areas are not used, in step S92, After incrementing the counter M by 1, the process returns to step S82 to use the next area in the next writing process.

On the other hand, when it is determined in step S91 that all the areas have been used, the process returns to step S81, the counter M is reset to zero, and the storage area of the RAM 42 is used from the beginning in the next writing process.

In this way, the workstation 41
In one writing process, the packet data is sequentially written in each block in a predetermined area of the RAM 42.

Next, the operation of the encoder 43 of the third embodiment will be described with reference to the flowchart of FIG.

First, in step S101, the encoder 43 sets the value of the counter M, which counts the number of areas (in this case, 2 20 bytes) of the RAM 42, which is composed of 512 blocks, to zero. To do.

Next, in step S102, the encoder 43 reads the data (1 byte) at the address (M × 2 to the 20th power) of the RAM 42, and in step S103, the value of the readable flag RD which is the second bit thereof. Determines whether is a value corresponding to "readable",
When it is determined that the value of the readable flag RD is a value corresponding to "readable", the process proceeds to step S104.

On the other hand, when it is determined that the value of the readable flag RD is not a value corresponding to "readable", the process returns to step S102, and the encoder 43 again stores the RAM.
The data at the address 42 (M × 2 to the 20th power) is read, and in step S103, it is determined whether or not the value of the readable flag RD is a value corresponding to “readable”. In this way, the encoder 43 waits until the value of the readable flag RD becomes the value corresponding to “readable”. That is, the encoder 43 waits until the workstation 41 finishes the reading process and changes the value of the flag.

In the initial state, since no data is written in the RAM 42, first, the value of the writable flag WR is set to "writable" so that the workstation 41 can write the data in the RAM 42. ", And the value of the readable flag RD is
It is set to "Unreadable".

Next, in step S104, the encoder 43 sets the value of the counter N, which counts the number of blocks from which packet data is read, to zero.

Then, in step S105, the encoder 43 determines (M × 2 to the 20th power + N × 2048 + 2).
After reading the length of the data written in the block from the address and the address of (M × 2 20 + N × 2048 + 3), (M × 2 20 + N × 2048 + 4)
Data of that length is read from the storage area after the address. That is, when M = 0 and N = 0, the encoder 43 reads out the length of data from addresses 2 and 3, and reads out the data of that length from the storage areas at addresses 4 and thereafter.

At step S106, the encoder 4
3 reads the data of the first address of this block,
By referring to the third bit (final data block flag LB) of the data, it is determined whether or not this block is the last block in one write processing, and this block is the last block. When it is determined, the process proceeds to step S107, the value of the readable flag RD (address of (M × 2 to the 20th power)) of the first block is set to a value corresponding to “unreadable”, and the value of the writable flag WR Is set to a value corresponding to “writeable”.

On the other hand, when it is determined in step S106 that this block is not the last block, the encoder 43 determines in step S108 that the counter N
After incrementing the value of 1 by 1, the process returns to step S105 to read the data of the next packet from the next block.

In this way, in steps S105, S106 and S108, the packet data is read until the final block is reached while referring to the value of the final data block flag LB of each block.

Then, in step S109, the encoder 43 processes the packet data thus read.

In step S110, the encoder 4
3 refers to the value of the counter M to determine whether or not all areas of the available area (area composed of 512 blocks) in the RAM 42 have been used,
If it is determined that all areas are not used, after incrementing the counter M by 1 in step S111,
Returning to step S102, in the next reading process,
Use the following areas.

On the other hand, if it is determined in step S110 that all the areas have been used, the process returns to step S101, the counter M is reset to zero, and the RAM 42 is used from the beginning in the next read processing.

In this way, the encoder 43 sequentially reads packets from each block in a predetermined area of the RAM 42 in one read process.

In the above-mentioned operation, the encoder 43 performs the packet processing in step S109, but instead of the processing in step S109,
After the processing of step S105, packet processing may be performed for each block.

As described above, in the third embodiment, the RAM 42 is managed for each fixed-length storage area, and the writable flag WR and the readable flag RD are used to make the workstation 41 and the encoder. It eliminates the need for direct communication between 43 and 1
Since the writing process or the reading process for a plurality of blocks is performed once, the processing speed can be increased.

Next, a fourth embodiment of the present invention will be described. The fourth embodiment is the same as the first embodiment except for the method of using the storage area of the RAM 42, so the RAM 4
Only the usage method of 2 will be described.

FIG. 12 shows an example of the RAM 42 of the fourth embodiment. The RAM 42 is managed for each fixed-length storage area (block) of 2,048 bytes. Then, in one writing process or one reading process,
A packet data write process or a packet data read process is performed on an area configured by a plurality of blocks (512 blocks in this case).

At the head address (((j-1) × 2 to the 20th power) of the head block of the j-th area, a writable flag WR (first bit) and a readable flag RD are set. The (second bit) is stored. The writable flag WR holds a value indicating whether the workstation 41 permits or prohibits writing of data to the RAM 42, and the readable flag RD indicates whether the encoder 43 permits or disallows reading of data from the RAM 42. Holds the value.

Further, the third bit of the head address of each block is used as a batch process end flag FN, and after one write process is completed, the block next to the block in which the last data is written is batched. Processing end flag FN
A value indicating that one writing process has been completed is written in. No data is written from the block in which the value indicating that one writing process has been completed is written to the batch process end flag FN to the last block in the area.

The fourth to eighth bits of the head address of the head block, the second address of the head block, and the head and second addresses of blocks other than the head are reserved areas. Is secured and is not used in particular.

At the third and fourth addresses of each block, the data length of the packet stored in that block is written.

At the fifth address to the last address of each block, the data of the packet assigned to that block is written. If the packet data is short, the area from the address next to the position where the end of the data is written to the last address of the block is a free area and is not used.

As described above, in the RAM 42, a total of 512 blocks are used as one area in one writing process or one reading process.

Next, the operation of the workstation 41 of the third embodiment will be described with reference to the flowchart of FIG.

First, in step S121, the workstation 41 is an area of the RAM 42 formed by 512 blocks (in this case, 2 20 bytes).
The value of the counter M that counts the number of is set to zero.

Next, in step S122, the workstation 41 stores the RAM 42 (M × 2 to the 20th power).
Address (that is, the first address of the area) data (1 byte)
Is read, and it is determined in step S123 whether the value of the writable flag WR, which is the first bit, is a value corresponding to “writable”, and the value of the writable flag WR is “writable”. If it is determined that the value corresponds to, the process proceeds to step S124.

On the other hand, when it is determined that the value of the writable flag WR is not a value corresponding to "writable", the process returns to step S122, and the workstation 41 again determines the address (M × 2 to the 20th power) of the RAM 42. Data is read, and it is determined in step S123 whether or not the value of the writable flag WR is a value corresponding to "writable". In this way, the workstation 41
Waits until the value of the writable flag WR becomes a value corresponding to “writable”.

In the initial state, since no data is written in the RAM 42, first, the value of the writable flag WR is "writable" so that the workstation 41 can write the data in the RAM 42. ", And the value of the readable flag RD is
It is set to "Unreadable".

Next, in step S124, the workstation 41 sets the value of the counter N, which counts the number of blocks into which packet data is written, to zero.

Then, in step S125, the workstation 41 determines (M × 2 to the 20th power + N × 204).
8) 3rd bit of address (collective processing end flag FN
(FIG. 12)), a value indicating that the writing process is not completed is set. That is, when M = 0 and N = 0, the workstation 41 sets a value indicating that the writing process is not completed in the third bit of the address 0.

In step S126, the workstation 41 determines (M × 2 to the 20th power + N × 2048 + 2).
After writing the data length of the packet to be written to the block at the address and (M × 2 20 + N × 2048 + 3), (M × 2 20 + N × 2048 + 4)
Data is written in the storage area after the address. That is, M =
If 0 and N = 0, workstation 41
As shown in FIG. 12, after writing the length of data at addresses 2 and 3, the data of that length is written to the storage area at addresses 4 and thereafter.

In step S127, the workstation 41 increments the value of the counter N by 1, and then proceeds to step S128.

In step S128, the workstation 41 determines whether or not one writing process is completed. If it is determined that the writing process is completed, the work station 41 proceeds to step S129, where (M × 2 20 + N). × 204
8) The value of the batch processing end flag FN of the address (that is, of the next block) is set to a value indicating that the writing processing has ended.

On the other hand, when it is determined in step S128 that the writing process is not completed, step S1
Returning to 25, the data of the next packet is written in the next block.

In this way, in steps S125 to S128, the packet data is written into a predetermined number of blocks, and when the writing process is completed, the value of the batch process end flag FN of the next block is set to a predetermined value. Set to.

Further, in step S130, the workstation 41 sets the value of the writable flag WR of the leading block to a value corresponding to "unwritable" and sets the value of the readable flag RD to "readable". Set to the value corresponding to.

Then, in step S131, the workstation 41 refers to the value of the counter M to read R
If it is determined whether or not all areas of the available area (area composed of 512 blocks) in the AM 42 have been used and it is determined that all areas are not used, in step S132, After incrementing the counter M by 1, the process returns to step S122 and the next area is used in the next writing process.

On the other hand, if it is determined in step S131 that all the areas have been used, the process returns to step S121, the counter M is reset to zero, and the next storage area is used from the beginning of the storage area of the RAM 42.

In this way, the workstation 41
In one writing process, the packet data is sequentially written in each block in a predetermined area of the RAM 42.

Next, the operation of the encoder 43 of the fourth embodiment will be described with reference to the flowchart of FIG.

First, in step S141, the encoder 43 sets the value of the counter M, which counts the number of areas (in this case, 2 20 bytes) of the RAM 42, which is composed of 512 blocks, to zero. To do.

Next, in step S142, the encoder 43 reads the data (1 byte) at the address (M × 2 to the 20th power) of the RAM 42, and in step S143, the readability flag R which is the second bit thereof.
It is determined whether or not the value of D is a value corresponding to "readable", and when it is determined that the value of the readable flag RD is a value corresponding to "readable", the process proceeds to step S144.

On the other hand, when it is determined that the value of the readable flag RD is not a value corresponding to "readable", the process returns to step S142, and the encoder 43 again stores the RAM.
The data at the address 42 (M × 2 to the 20th power) is read, and in step S143, it is determined whether or not the value of the readable flag RD is a value corresponding to “readable”. In this way, the encoder 43 waits until the value of the readable flag RD becomes the value corresponding to “readable”.

In the initial state, since no data is written in the RAM 42, first, the value of the writable flag WR is set to "writable" so that the workstation 41 can write the data in the RAM 42. ", And the value of the readable flag RD is
It is set to "Unreadable".

Next, in step S144, the encoder 43 sets the value of the counter N, which counts the number of blocks from which packet data is read, to zero.

Then, in step S145, the encoder 43 calculates (M × 2 to the 20th power + N × 2048 + 2).
After reading the data length of the packet written in the block from the address and the address (M × 2 20 + N × 2048 + 3), (M × 2 20 + N × 20)
The data of that length is read from the storage area after the address 48 + 4).

At step S146, the encoder 4
3 increments the value of the counter N by 1 and executes step S1.
Proceed to 47.

In step S147, the encoder 4
3 is the address (M × 2 to the 20th power + N × 2048) (ie,
The data of the head address of the block next to the block read in step S145) is read.

Then, in step S148, the encoder 43 refers to the batch processing end flag FN which is the third bit of the data, and the block read in step S145 is the last block (the last block in which the data is written). If it is determined that the block is the last block, the process proceeds to step S149 and the read enable flag RD (address (M × 2 20)) of the first block is determined. Set the value to the value corresponding to "Read not possible", and write enable flag W
The value of R is set to a value corresponding to "writeable".

On the other hand, if it is determined in step S148 that the block read in step S145 is not the last block, the process returns to step S145 to read the next packet from the next block.

In this way, in steps S145 to S148, while referring to the value of the batch processing end flag FN of each block, the packet data is read until the last block in which the data is written is reached. .

Then, in step S150, the encoder 43 processes the packet data thus read.

In step S151, the encoder 4
3 refers to the value of the counter M to determine whether or not all areas of the available area (area composed of 512 blocks) in the RAM 42 have been used,
When it is determined that all areas are not used, after incrementing the counter M by 1 in step S152,
Returning to step S142, in the next reading process,
Use the following areas.

On the other hand, if it is determined in step S151 that all the areas have been used, the process returns to step S141, the counter M is reset to zero, and the storage area of the RAM 42 is used from the beginning in the next read processing.

In this way, the encoder 43 sequentially reads the packet data from each block in a predetermined area of the RAM 42 in one read process.

In the above-mentioned operation, the encoder 43 processes the packet in step S150, but instead of the process in step S150,
After the processing of step S145, the packet processing may be performed for each block.

As described above, according to the fourth embodiment, the RAM 42 is managed for each fixed-length storage area, and the writable flag WR and the readable flag RD are used to make the workstation 41 and the encoder. It eliminates the need for direct communication between 43 and 1
Since the writing process or the reading process is performed on a plurality of blocks at once, the processing speed can be increased.

In the above embodiment, the length of one block is 2,048 bytes, and the number of blocks in one area is 512. However, the length of the block and the length of the area are Is not particularly limited.

Further, although the above embodiment is applied to the data distribution system, of course, it can be applied to other systems.

[0192]

[0193]

As described above, according to the information processing apparatus of the first aspect and the information processing method of the sixth aspect ,
The first information processing unit sets the second storage area of the first storage area according to the value of the first storage area of the first storage area of the plurality of storage areas provided in the predetermined storage section. In the area, write the number of storage areas for writing data, write the data in each storage area, and then change the value of the first area and the value of the third area of the first storage area,
The second information processing unit reads the number of storage areas written in the second area of the first storage area according to the value of the third area in the first storage area of the storage unit, and reads the number. After the data written by the first information processing unit is read from the storage area of the first storage area, the value of the first area and the value of the third area of the first storage area are changed. A workstation that is an information processing unit and a second
By eliminating the communication between the encoders of the information processing unit, the cost of the device can be reduced and the processing speed can be improved.

[0194] The information processing apparatus and contract according to claim 7.
According to the information processing method described in claim 8 , the first information processing unit includes a first storage area of the first storage area of a plurality of storage areas provided in the predetermined storage section. Depending on the value, write data to multiple storage areas sequentially,
After writing a predetermined value to the second area of the last storage area of the areas configured by a plurality of storage areas, change the value of the first area and the value of the third area of the first storage area, The second information processing unit sequentially reads the data written by the first information processing unit from the plurality of storage areas according to the value of the third area in the first storage area of the storage unit,
Since the value of the first area and the value of the third area of the first storage area are changed after the data reading is completed according to the value of the second area, the first information processing unit By eliminating the communication between the workstation and the encoder of the second information processing unit, the cost of the device can be reduced and the processing speed can be improved.

[0195]

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a data distribution system.

FIG. 2 is a block diagram showing the configuration of the first embodiment of the information processing apparatus of the present invention.

FIG. 3 is a diagram showing an example of allocation of storage areas of a RAM 42 according to the first embodiment.

FIG. 4 is a flowchart illustrating an operation of the workstation 41 according to the first embodiment.

FIG. 5 is a flowchart illustrating an operation of the encoder 43 according to the first embodiment.

FIG. 6 is a diagram showing an example of allocation of storage areas of a RAM 42 according to a second embodiment.

FIG. 7 is a flowchart illustrating an operation of the workstation 41 according to the second embodiment.

FIG. 8 is a flowchart illustrating an operation of the encoder 43 according to the second embodiment.

FIG. 9 is a diagram showing an example of allocation of storage areas of a RAM 42 according to a third embodiment.

FIG. 10 is a flowchart illustrating an operation of the workstation 41 according to the third embodiment.

FIG. 11 is a flowchart illustrating an operation of the encoder 43 according to the third embodiment.

FIG. 12 is a diagram showing an example of allocation of storage areas of a RAM 42 according to a fourth embodiment.

FIG. 13 is a flowchart illustrating an operation of the workstation 41 according to the fourth embodiment.

FIG. 14 is a flowchart illustrating an operation of the encoder 43 of the fourth embodiment.

FIG. 15 is a block diagram showing a configuration example of a conventional information processing apparatus.

[Explanation of symbols]

1 receiver, 2 information provider, 3 transmitting station, 4
Artificial satellite, 11 modem, 21 modem, 22
Server, 31 information processing device, 41 workstation, 42 RAM, 43 encoder

Claims (8)

(57) [Claims] 1. A storage unit for temporarily storing predetermined data; a first information processing unit for writing data into the storage unit for each predetermined storage region; and a storage region from the storage unit. An information processing apparatus comprising: a second information processing unit for reading data for each, wherein the first information processing unit is a first one of a plurality of storage regions provided in the storage unit. According to the value of the first area in the storage area, after writing the number of the storage areas for writing data in the second area of the first storage area and writing the data in each of the storage areas Changing the value of the first area and the value of the third area of the first storage area, the second information processing means of the third storage area of the first storage area of the storage means. Depending on the value, the first After reading the number of the storage areas written in the second area of the storage area and reading the data written by the first information processing means from the number of the storage areas, the first An information processing apparatus, wherein a value of the first area and a value of the third area of a fixed-length storage area are changed. 2. The information processing apparatus according to claim 1 , wherein the storage area of the storage means is a fixed-length storage area. 3. The first area of the storage area stores information indicating whether or not writing of data to the storage area is permitted, and the third area of the storage area is stored. The information processing apparatus according to claim 1 , wherein information indicating whether or not reading of data from the storage area is permitted is stored in the area. 4. The first information processing means writes the length of data in a fourth area of each storage area, and the second information processing means writes in the fourth area of each storage area. The information processing apparatus according to claim 1 , wherein the stored data length is referred to and the data of that length is read. 5. The length of the fixed-length storage area excluding the first area, the second area, the third area, and the fourth area, The information processing apparatus according to claim 2 , wherein data having a length equal to or less than a length is written in the fixed-length storage area. 6. A first information processing unit, wherein the first information processing unit is provided in a predetermined storage unit, the first region of a plurality of storage regions, which is first Writing the number of the storage areas to which data is written into the second area of the first storage area, writing the data into each of the storage areas, and then writing the value of the first area and the first area of the first storage area. Changing the value of the area of No. 3; and the second information processing unit according to the value of the third area of the first storage area of the storage unit, the second of the second storage area of the first storage area. The number of the storage areas written in the area is read, and the data written by the first information processing unit is read from the number of the storage areas. The first
And a step of changing the value of the area and the value of the third area. 7. Storage means for temporarily storing predetermined data, first information processing means for writing data into the storage means for each predetermined storage area, and the storage area from the storage means. An information processing apparatus comprising: a second information processing unit for reading data for each, wherein the first information processing unit is a first one of a plurality of storage regions provided in the storage unit. Data is sequentially written to the plurality of storage areas according to the value of the first area in the storage area, and a predetermined value is set in the second area of the last storage area of the plurality of storage areas. After writing, the value of the first area and the value of the third area of the first storage area are changed, and the second information processing means sets the third information in the first storage area of the storage means. Depending on the value of the area, the plurality of The data written by the first information processing means is sequentially read from the storage area, and after the data reading is completed according to the value of the second area, the first storage area of the first storage area is read. An information processing apparatus, characterized in that the value of the area and the value of the third area are changed. 8. The first information processing unit stores data according to a value of a first area in the first storage area of a plurality of storage areas provided in a predetermined storage section. Writing sequentially to a plurality of storage areas, writing a predetermined value to a second storage area of the last storage area of the plurality of storage areas, and then writing the first value of the first storage area.
Changing the value of the area and the value of the third area, the second information processing unit according to the value of the third area in the first storage area of the storage unit, a plurality of storage areas From which the data written by the first information processing unit is sequentially read, and in accordance with the value of the second area,
A step of changing the value of the first area and the value of the third area of the first storage area after the reading of the data is completed.