JP2856095B2 - Caching method for cell / packet translation module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a caching method for a cell / packet conversion module, and more particularly to a cell / packet conversion module having a function of converting a packet to a cell, which is used for relaying between LANs via an ATM network. The present invention relates to a caching method in a packet conversion module.

[0002]

2. Description of the Related Art In an ATM network (asynchronous transfer mode), all information is converted into a fixed-length cell of 53 bytes consisting of a 5-byte header and a 48-byte information field and transmitted. The system can process at high speed by taking advantage of the conventional circuit switching network and packet switching network.

FIG. 6 is a schematic block diagram of an ATM switching system. In FIG. 6, when packet information generated in LAN1 is transmitted to LAN2, packet information from LAN1 is given to PC conversion device 3, and PC conversion device 3 transmits the packet information to a communication path (connection). ), And is divided into cells based on the transmission rate determined for each connection. Then, the PC converter 3 adds a header indicating a destination or the like to the head of each of the divided cells, and transmits the cells to the ATM switching network 4. The ATM switching network 4 refers to the contents of the header included in the cell, sorts the cell at high speed, and delivers it to the CP converter 5. The CP converter 5 returns the cell to a packet and sends it out to the LAN 2. If a plurality of connections transmit packets at the same transmission rate, the first packet in the packet matrix for each connection is circulated and transmitted one cell at a time. PC conversion device 3 shown in FIG.
And the CP converter 5 use a caching technique to perform cell / packet conversion. That is, the caching technique uses a database having a limited number of packet information and all packet information in the contents of the cell / packet conversion module that requires packet information as packet management information at the time of cell / packet conversion. This is done by reducing the number of direct searches to. That is, management information for processing all packets is registered in the database, and a part of the management information in the database is stored in the caching memory.

FIG. 7 is a diagram showing the contents of an entry for caching the conventional packet management information. As shown in FIG. 7, in the entry for each packet, an identifier for identifying each packet, information of the packet, and a time stamp indicating the time when the entry was registered are registered. Further, an invalid flag indicating whether the entry is invalid is provided for each entry.

The cell-to-packet conversion module searches the contents of the cache memory every time a cell is divided and a cell is assembled into packets. If the identifier of the packet to which the cell belongs is registered in the cache memory, the packet information is taken out, the packet is divided into cells and transmitted, and the cells are assembled into packets and received. If the identifier of the packet to which the cell belongs is not registered in the cache memory, the information of the packet is read from the database having the packet information of all the packets, the packet is divided into cells and transmitted, and the cells are assembled into packets and received. Is performed.

FIG. 8 is a flow chart for explaining the registration judgment to the cache memory which has been used conventionally. In FIG. 8, when the packet information of the packet is read from the database in step (abbreviated as SP in FIG. 8) SP1, it is determined whether or not there is an entry in which the invalid flag is set in the cache memory in step SP2. If there is an entry with an invalid flag set, the process proceeds to step SP3, and the newly read packet information is registered in the cache memory.
On the other hand, if there is no entry with the invalid flag set,
In step SP4, the entry with the oldest time stamp is deleted. Then, in step SP5, the newly read packet information is registered in the deleted entry area. That is, when the cache memory entry is full, the entry with the oldest time stamp among the registered entries is deleted from the cache memory, and the newly read packet information is registered in the entry.

[0007]

In the above-mentioned conventional method, when a plurality of packets exceeding the number of entries in the cache memory are simultaneously divided and assembled at regular intervals, each packet is divided and assembled one cell at a time in order. Therefore, when the entries in the cache memory are full, it is necessary to delete the entry with the oldest time stamp and register the newly read information. For this reason, a state may occur in which there is no corresponding entry in the cache memory.

For example, when the number of entries in the cache memory is, for example, up to three and four packets A, B, C, and D are to be divided at the same time, if the division interval is constant. For example, it is necessary to repeat division into cells sequentially from the head of each packet in the order of A → B → C → D → A. For this reason, when the packet of D is divided, only the packets of A, B, and C are entered in the cache memory. When the packet information of D is read from the database, the packet of A with the oldest time stamp is obtained. Must be deleted and the packet information of D must be registered. Then, the packet of A is divided again. At this time, since the packet of A is not entered in the cache memory, the packet information is read from the external database. Since this operation is repeated, there is a problem that the cache memory has no effect at all.

SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a method for caching a cell / packet conversion module which can enhance the effect of a cache memory.

[0010]

The invention according to claim 1 is
Includes a database that stores management information for processing packets, and a cache memory that stores some management information among the management information stored in the database, and divides packets into cells or assembles cells as packets. When the cache memory is searched, if the management information of the packet to which the cell belongs is registered, the packet is divided into cells or the cell is assembled as a packet. If the management information is not registered, another management from the database is performed. In the cell / packet conversion module for reading information and storing the information in the cache memory, each area of the cache memory has a certain starting value, and the value is reduced at regular intervals, and when the area is referred to for cell division. Set to the starting value again, and when the value is the specified value, the time-up flag Including a set timer, when another management information is read from the database and stored in the cache memory, the management information is registered in the area where the time-up flag is set, and there is no area where the time-up flag is set. For example, the management information is not registered in the cache memory.

According to a second aspect of the present invention, when the area of the cache memory is full and new data cannot be added, the start value of the timer of the first aspect is reduced, and the value of the timer becomes a predetermined value. Reduce the time gradually.

According to a third aspect of the invention, when the event that the cache memory cannot be registered has not occurred for a certain period of time, the start value of the timer of the second aspect is increased,
The time when the value of the timer becomes a predetermined value is gradually increased.

[0013]

[0014]

[0015]

According to the first aspect of the present invention, each area of the cache memory has a certain start value, the value is reduced at regular intervals, and when the area is referred to for cell division, the start value is again set. A timer is provided for setting a time-up flag when the value is a predetermined value. When another management information is read from the database and stored in the cache memory, the management information is stored in an area where the time-up flag is set. And if the management information is not registered in the cache memory unless there is an area in which the time-up flag is set, even when dividing and assembling a plurality of packets simultaneously at a constant interval,
It can have an effect as a cache memory.

According to the second aspect of the present invention, when the packet information cannot be registered because the cache memory is full, the start value of the timer is gradually reduced, so that a packet having a higher transmission rate is present in the entry of the cache memory. The probability increases, and the effect of the cache can be improved.

According to the third aspect of the invention, when the event that the cache memory cannot be registered does not occur, the time when each packet information is registered in the cache memory is extended by increasing the timer start value of the cache memory, The effect of the cache memory can be improved.

[0018]

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a PC, CP according to an embodiment of the present invention.
It is a block diagram of a converter. In FIG. 1, PC,
The CP converter 30 is connected to the CP connected to the internal bus 31.
U32, database 33 and LAN interface 36
And a cell / packet conversion module 35, and further includes a packet storage memory 34 and an ATM interface 37 connected to the cell / packet conversion module 35. The LAN 1 is connected to the LAN interface 36, and the ATM network 4 is connected to the ATM interface 37. The database 33 stores the packet information of all the packets, and the packet storage memory 34 stores the packet itself. The cell / packet conversion module 35 includes a cache memory 38 in which the caching method according to the present invention is employed.

FIG. 2 is a specific block diagram of the cell / packet conversion module 35 shown in FIG. 2, the cell / packet conversion module 35 includes a cache memory 38, a packet / cell conversion core 40, and a timer start value module 41. The cache memory 38
Packet identifier 381, packet information 382, and timer 3
83, an area for entering an invalid flag 384, and a time-up flag 385. The packet / cell conversion core 40 converts the packet information into cells by referring to the entries registered in the cache memory 38, and the timer start value module 41 responds to a request from the packet / cell conversion core 40, The start value of the timer 383 is increased or decreased.

FIG. 3 is a flowchart for explaining the operation of the packet / cell conversion core 40 shown in FIG.
FIG. 4 is a flowchart for explaining the operation of the timer in the cache memory 38, and FIG. 5 is a flowchart for explaining the operation of the timer start value module 41.

Next, a specific operation of one embodiment of the present invention will be described with reference to FIGS. First, FIG.
The packet received from the LAN 1 through the LAN interface 36 is stored in the packet storage memory 34. The CPU 32 determines from the destination address of the packet whether the packet is for communication with the ATM network 4 or not. If the packet is to be transmitted to the ATM network 4,
The CPU 32 registers the packet information of the packet in the database 33, sends a packet transmission request to the ATM network 4, and transmits the packet identifier to the cell / packet conversion module 3.
Perform by passing to 5. The cell / packet conversion module 35 arranges the identifier of the packet for each connection, divides the packet into cells based on the set rate, and transmits the cells to the ATM network 4.

Here, the cell / packet conversion module 3
The operation of No. 5 for dividing packet information into cells will be described in more detail. When a packet transmission request is given from the CPU 4 to the cell / packet conversion module 35, the packet / cell conversion core 40 executes the processing shown in FIG. That is, the packet / cell conversion core 40 performs step SP
At 11, packet / cell conversion processing is started,
In step SP12, the cache memory 38 is searched to determine whether or not an entry corresponding to the packet to be divided is registered in the cache memory 38. If the entry is registered, the packet information 382 is read from the cache memory 38 at step SP13, and it is determined at step SP50 whether or not the packet is the last cell of the packet. If it is not the last cell, a request to set the timer 383 corresponding to the entry to a start value is given to the timer start value module 41 in step SP14. If the converted cell is the last cell, the entry read in step SP51 is invalidated.

The timer start value module 41 gives the timer start value to the cache memory 38. The timer 383 in the cache memory 38 is set at the step SP21 shown in FIG.
In, a starting value is set. The packet / cell conversion core 40 converts the packet into a cell using the packet information 382 in step SP15 shown in FIG. The converted cells are sent to the ATM network 4 via the ATM interface 37 shown in FIG. Then, the timer 383
In step SP22, the timer value is decremented by one, and in step SP23, it is determined whether the timer value has become 0. If not, the timer value is decremented by one again in step SP22. If the timer value is 0, the time-up flag 385 of the entry is set in step SP24.

When the packet / cell conversion core 40 determines that the entry corresponding to the packet to be divided is not registered in step SP12, all the packet information is registered in step SP16. The packet information corresponding to the packet is read from the database 33. Then, in step SP52, it is determined whether or not the converted cell is the last cell of the packet.
The packet / cell conversion is performed in step 5, and if not the end of the packet, the cache memory 38 is searched in step SP17 to determine whether or not there is an entry for which the invalid flag is set. If there is an entry with an invalid flag set, in step SP18, the newly read packet information is registered in the entry with the invalid flag set, and the invalid flag 384 is cleared. If it is determined in step SP17 that there is no invalid entry, the cache memory 83 is searched in step SP53, and the time-up flag 38
It is determined whether or not there is an entry in which 5 is set. If there is an entry in which the time-up flag 385 is set, the entry in which the time-up flag 385 is set is set in step SP54.
The newly read packet information is registered, and the time-up flag 385 is cleared. Thereafter, the operations of steps SP14 and SP15 are executed in the same manner as described above.

If there is no entry in the cache memory 38 in which the time-up flag 385 is set in step SP53, it means that the entry in the cache memory 38 is full. In this case, a new read is performed in step SP19. In step SP20, the timer start value reduction request is sent to the timer start value module 4
Give to 1.

The timer start value module 41 executes the operation shown in FIG. 5 in response to the timer start value decrease request. That is, the timer start value module 41 has previously set the initial value in step SP31, and has initialized the time in step SP32.
Then, when a decrease request is given from the packet / cell conversion core 40, it is determined in step SP33 that a decrease request has been made, and in step SP34, the timer 38
Decrease the timer start value of 3. Specifically, the timer start value is reduced to, for example, half. It should be noted that the timer start value module 41 determines in step SP35 whether or not an idle state has been maintained for a certain period of time, that is, if the event that registration to the cache memory 38 cannot be performed has not occurred within a certain period of time, the process proceeds to step SP36. In, the start value of the timer is increased. Specifically, the start value of the timer is doubled. As a result, the time during which each piece of packet information is registered in the cache memory 38 is increased, and the effect of caching can be improved.

[0028]

As described above, according to the present invention, each area of the cache memory has a certain starting value, and the value is reduced at regular intervals, and the area is referred to for cell division. When the timer is set to the start value again and a time-up flag is set when the value is a predetermined value, the time-up flag is set when another management information is read from the database and stored in the cache memory. When dividing and assembling a plurality of packets at a certain interval at the same time by registering the management information in the area where the Also, the effect as a cache memory can be obtained.

[0029]

[0030]

[0031]

[Brief description of the drawings]

FIG. 1 is a block diagram of a PC, CP converter according to an embodiment of the present invention.

FIG. 2 is a specific block diagram of a cell packet conversion module shown in FIG. 1;

FIG. 3 is a flowchart for explaining an operation of the packet / cell conversion core shown in FIG. 2;

FIG. 4 is a flowchart illustrating the operation of a timer in a cache memory.

FIG. 5 is a flowchart for explaining the operation of a timer start value module.

FIG. 6 is a schematic block diagram of a conventional ATM switching system.

FIG. 7 is a diagram showing entries of a cache memory in a conventional cell / packet conversion module.

FIG. 8 is a flowchart for explaining a conventional cell / packet conversion module registration determination in a cache memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 LAN 4 ATM network 30 PC converter 31 Internal bus 32 CPU 33 Database 34 Packet storage memory 35 Cell / packet conversion module 36 LAN interface 37 ATM interface 38 Cache memory 40 Packet / cell conversion core 41 Timer start value module

Claims (3)

(57) [Claims] 1. A database for storing management information for processing a packet, and a cache memory for storing a part of management information among the management information stored in the database, wherein the packet is stored in a cell. When dividing or assembling a cell as a packet, the cache memory is searched. If the management information of the packet to which the cell belongs is registered, the packet is divided into cells or the cell is assembled as a packet, and the management information is registered. If not, in the cell-packet conversion module for reading another management information from the database and storing it in the cache memory, each area of the cache memory has a certain start value, and the value is reduced at regular time intervals. Is set to the starting value again when is referenced for cell splitting,
A timer for setting a time-up flag when the value is a predetermined value; and when reading out another management information from the database and storing the same in the cache memory, the management information is stored in an area where the time-up flag is set. Characterized in that the management information is not registered in the cache memory unless there is an area in which a time-up flag is set. 2. When the area of the cache memory is full and new management information cannot be added, the start value of the timer is reduced, and the time when the value of the timer becomes a predetermined value is gradually shortened. 2. The method according to claim 1, wherein the caching is performed on the cell packet conversion module. 3. If the event that the cache memory cannot be registered has not occurred for a certain period of time, the start value of the timer is increased, and the time when the value of the timer becomes a predetermined value is gradually increased. 3. The method according to claim 2, wherein the length is increased.