JP2013135383A - Packet buffer device and packet buffer control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize increase in the extra circuit scale incident to increase in the data memory for storing packets, even if the number of packets to be stored is increased.SOLUTION: A packet buffer device 10 includes a memory 12, a write block buffer 13A, and a read block buffer 14A. A packet control unit 11 stores input packet data sequentially in the write block buffer 13A, stores the packet boundary information indicating the end position of packet data in the write block buffer 13A therein, writes the data of a predetermined volume in the memory 12 at a moment in time when it is stored, reads the data from the memory 12 in response to an output instruction and stores that data in a read block buffer 14A, and then reads and outputs each packet data contained in that data on the basis of the packet boundary information contained in that data.

Description

  The present invention relates to a packet processing technique, and more particularly to a packet buffer control technique for storing an input packet in a memory and extracting and outputting the packet from the memory in response to an output instruction.

With the spread of optical communication networks such as FTTH (Fiber To The Home), the communication speed in the data communication line has been greatly increased, and packet communication devices that transmit and receive packets such as network adapters, especially by buffering packets. In the packet buffer device to be processed, improvement of the processing capability is being studied.
Conventionally, such a packet buffer device has been proposed in which packet processing is improved by hardware processing (see, for example, Non-Patent Document 1).

FIG. 15 is a block diagram showing a configuration of a conventional packet buffer device. FIG. 16 is an explanatory diagram showing the operation of the conventional packet buffer device.
15 includes a buffer control unit 51, a data memory 52, and a job memory 53.
The packet buffer device 50 includes a plurality of queues (FIFO memories), stores input variable-length packets in the queue, and stores the packets stored in the queue according to input output instruction information. Is taken out from the queue and output.

The data memory 52 has a different address area for each queue, and has a function of storing packet data of the queue in the area corresponding to the queue.
The job memory 53 has a different address area for each queue, and has a function of storing a fixed-length packet job (job information) generated for each input packet in the area corresponding to the queue. . The packet job includes packet boundary information for specifying the boundary position of each packet in the data memory 52.
The data memory 52 and the job memory 53 are controlled as FIFO buffers by the buffer control unit 51.

The buffer control unit 51 has a function of writing packet data of the packet to the data memory 52 in response to the input of a variable-length packet, and a function of generating a packet job based on the writing and writing the packet job to the job memory 53. have. The packet job includes an address value in which the top of the packet data is stored in the data memory.
Further, the buffer control unit 51 reads a packet job from the job memory 53 according to the input of the output instruction information, and reads the packet data of the corresponding packet from the data memory 52 based on the packet job. Output function.

In such a packet buffer device 50, for example, the buffer control unit 51 is configured by an LSI chip (RENA-CHIP), and the data memory 52 is a DDR-SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory). Each queue is constituted by an internal memory arranged in the LSI of the buffer control unit 51.
Accordingly, the input packet data is stored in the DDR-SDRAM by the buffer control unit 51. At this time, the packet job including the storage position of the packet data in the DDR-SDRAM is stored in the internal memory by the buffer control unit 51. Also, the pad data is read from the DDR-SDRAM and output in accordance with the output instruction information.

NTT Journal 2006 vol. 18 No. 7 “RENA-CHIP Hardware Configuration Technology”, http://www.ntt.co.jp/journal/0607/files/jn200607022.html

  In such a conventional technique, in addition to the data memory 52 for storing packets, a job memory 53 for storing a fixed-length packet job for each packet is required. Since the packet has a variable length, when a short packet is continuously input, the amount of data stored in the memory for data is at least increased.

For this reason, in order to be able to use up the data memory 52 no matter how long the packet is input, the number of packets stored when the data memory is filled with only the shortest packet. The job memory 53 having a capacity sufficient to store the packet job is required.
In general, a large capacity memory such as SDRAM is used for the data memory 52. However, the job memory 53 does not require as much capacity as the data memory. Since the use of dedicated SDRAM increases the circuit scale, SRAM is generally used.

  The reason for dividing the memory between the data memory 52 and the job memory 53 is to increase the bandwidth utilization efficiency of the data memory 52. When reading from the SDRAM, it is necessary to wait for a certain time after issuing the read command and receive data corresponding to the read command from the SDRAM. Therefore, if the SDRAM performs the operation of receiving the previous reading result and performing the next reading, the bandwidth of the SDRAM interface cannot be used effectively due to the waiting time.

That is, since it is necessary to know the storage position of the packet data before reading the packet data stored in the memory, the packet data is read after reading the storage position.
At this time, if both the storage location information and the packet data are stored in the same SDRAM, a read command is issued to the memory in order to read the storage location information from the memory. Receiving storage location information from the memory, and then issuing a read command to the memory to read packet data based on the storage location information, and receiving the packet data from the memory after a certain waiting time; It becomes the procedure.

For this reason, it takes twice as long to read the packet data of one packet from the memory, so that the bandwidth utilization efficiency of the memory is lowered. Therefore, in order to increase the bandwidth utilization efficiency, a job memory 53 using an SRAM having a short time from the start of reading to completion is provided separately from the SDRAM which is the data memory 52.
The SRAM has a feature that the area per bit is larger than that of the SDRAM, but reading from the memory can be performed in a short time. By reading the packet job from the job memory 53 on the SRAM in a short time and reading the packet data from the data memory 52 on the SDRAM based on the packet job information, the bandwidth utilization efficiency of the SDRAM is increased.

  However, since the area per bit of the SRAM is larger than that of the SDRAM, the circuit scale is increased. Therefore, according to the above-described prior art, it is necessary to use an SRAM in addition to the SDRAM. Therefore, when the capacity of the data memory 52 is increased for the purpose of increasing the number of packets to be accumulated, the SRAM is associated with this. As a result, the capacity of the job memory 53 increases, resulting in a problem that the circuit scale increases excessively.

  The present invention is for solving such problems, and even when the number of packets to be accumulated is increased, packet buffer control capable of suppressing an increase in an extra circuit scale accompanying an increase in data memory for accumulating packets. The purpose is to provide technology.

  In order to achieve such an object, a packet buffer device according to the present invention has a plurality of blocks each having a fixed-length storage area, and writes and reads data for each block, and at least the blocks A write block buffer for holding data for a minute, a read block buffer for holding data for at least the block, and packet data of input variable-length packets are sequentially stored in the write block buffer, and When block management information including packet boundary information indicating the end position of each packet data stored in the write block buffer is stored in the write block buffer, and when a predetermined amount of data is stored in the write block buffer , Write the data to the memory unit, Next, the data is read from the memory unit and stored in the read block buffer, and each packet data included in the data is read and output based on the packet boundary information of the block management information included in the data A packet control unit.

  Also, in one configuration example of the packet buffer device according to the present invention, when the packet control unit stores the packet data in the write block buffer, the packet block device has insufficient free space in the write block buffer. When all of the data cannot be stored, after the data stored in the write block buffer is written to the memory unit, the remaining packet data is stored from the top of the write block buffer.

  Also, in one configuration example of the packet buffer device according to the present invention, the block is divided into a plurality of words each having a fixed length of a plurality of bytes, and the packet control unit is provided in the write block buffer. When storing the block management information, the block management information is stored from the first word of the word in the write block buffer, and when writing the packet data to the write block buffer, the last byte of the block management information When selecting the word for storage in order from the next word of the first word storing the packet, and storing the packet data in the selected word, each byte of the packet data is stored in order from the first byte of the word, The end of a given packet is started from the byte following the byte storing the last byte of the packet data. When the block is stored and the block management information is stored in the write block buffer, the block includes a boundary determination bit string indicating the presence / absence of the last byte of the packet data in each word instead of the packet boundary information Management information is stored.

  Also, in one configuration example of the packet buffer device according to the present invention, when the packet control unit reads the packet data from the block, the block management information is first obtained from the head word of the block, Based on the boundary determination bit string of the management information, the presence / absence of the end byte of the packet data in the block is determined, and when the end byte does not exist, the memory unit is requested to read the next block, When the tail byte does not exist, the packet data is read sequentially from the next word after the top word.

  Also, in one configuration example of the packet buffer device according to the present invention, the buffer control unit is configured for a partition corresponding to the queue specified by the queue input instruction information among the partitions configured by the plurality of blocks. By writing the packet data, the packet data is accumulated in the queue, and by reading the packet data from the partition corresponding to the queue specified by the queue output instruction information in the memory unit, When the packet data is taken out from the queue and the writing of the packet data to the partition is completed, after the free partition is connected to the partition as a connected partition, the writing of the packet data to the free partition is continued. When the reading of the packet data from the partition expires, the partition is freed Thereby releasing a picture, in which so as to continue the reading of the packet data from the connection section which is connected to the compartment.

  The packet buffer control method according to the present invention stores an input packet in a queue (FIFO memory), and extracts and outputs a packet from the queue in response to an output instruction. A plurality of blocks each having a fixed-length storage area, a memory unit for writing and reading data for each block, a write block buffer for holding at least the data for the blocks, and at least the blocks And a read block buffer that holds the data for a minute, and the packet control unit sequentially stores the packet data of the input variable-length packet in the write block buffer and stores each packet data in the write block buffer. Packet indicating the end position of packet data A step of storing block management information including boundary information in the write block buffer, and when a predetermined amount of data is stored in the write block buffer, the data is written to the memory unit and inputted output In response to an instruction, the data is read from the memory unit, stored in the read block buffer, and each packet data included in the data is read based on the packet boundary information of the block management information included in the data. Output step.

  According to the present invention, fixed-length block management information including packet boundary information generated for each input packet is concatenated with the packet data and stored in the queue of the memory unit. For this reason, unlike the prior art, it is not necessary to provide a job memory including an SRAM for accumulating fixed-length packet jobs (job information) separately from the queue. Therefore, even when the number of packets to be accumulated is increased, it is possible to suppress an increase in an extra circuit scale accompanying an increase in the data memory for accumulating packets.

It is a block diagram which shows the structure of the packet buffer apparatus concerning 1st Embodiment. It is explanatory drawing which shows the packet data storage state in the memory part concerning 1st Embodiment. FIG. 6 is a state transition diagram illustrating a write operation according to the first embodiment. FIG. 6 is a state transition diagram illustrating a read operation according to the first embodiment. It is an example of composition of a memory part concerning a 2nd embodiment. It is a block diagram which shows the structure of the packet buffer apparatus concerning 3rd Embodiment. It is a structural example of a memory part (block division). It is explanatory drawing which shows the packet data storage state in the memory part concerning 3rd Embodiment. FIG. 10 is a state transition diagram illustrating a write operation according to a third embodiment. FIG. 10 is a state transition diagram showing a block write operation according to a third embodiment. FIG. 10 is a state transition diagram illustrating a read operation according to a third embodiment. FIG. 10 is a state transition diagram illustrating a block read operation according to a third embodiment. It is a state transition diagram which shows division connection operation | movement. It is a state transition diagram showing a partition release operation. It is a block which shows the structure of the conventional packet buffer apparatus. It is explanatory drawing which shows operation | movement of the conventional packet buffer apparatus.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a packet buffer device 10 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the packet buffer device according to the first embodiment.

This packet buffer device 10 is used in a packet communication device that transmits and receives packets, and has a function of storing an input packet in a queue (FIFO memory) and extracting and outputting the packet from the queue according to an output instruction. doing.
The packet buffer device 10 includes a buffer control unit 11, a memory unit 12, a write buffer unit 13, and a read buffer unit 14 as main functional units.

  The buffer control unit 11 writes the packet data of the input packet to the memory unit 12 to store the packet in the memory unit 12 and the output instruction information that specifies the timing to extract the stored packet. It has a function of reading packet data from the memory unit 12 and outputting it. The buffer control unit 11 outputs, to the external device, storage state information indicating the storage state as output instruction information input from an external device (not shown) as information for the external device to generate. A function may be provided.

  The memory unit 12 receives the packet data and an address for writing the packet data from the buffer control unit 11, and reads the packet data from the buffer control unit 11, and a function for writing the packet data to the memory cell corresponding to the address. It has a function of receiving an address and outputting packet data held in a memory cell corresponding to the address to the buffer control unit 11.

  The write buffer unit 13 includes a write block buffer 13A that holds at least one block of data, that is, block data. The write buffer unit 13 receives packet data and block management information from the buffer control unit 11, and receives the write block buffer 13A. And the function of outputting the block data held in the write block buffer 13A to the buffer control unit 11 in response to an output instruction from the buffer control unit 11.

  The read buffer unit 14 has a read block buffer 14A that holds at least one block of block data. The read buffer unit 14 receives block data from the buffer control unit 11 and stores it in the read block buffer 14A. In response to the output instruction, the block data held in the read block buffer 14A is output to the buffer control unit 11.

FIG. 2 is an explanatory diagram illustrating a packet data accumulation state in the memory unit according to the first embodiment.
Based on the control from the buffer control unit 11, the memory unit 12 sequentially writes / reads packets in blocks of a fixed length of K bytes. In this example, memory areas with consecutive addresses are divided into K bytes and each block is stored, and the blocks are stored from the block with the smallest address in the order of packet input.

  K is the number of bytes in one block, and by making the value of K an integer multiple of the amount of data that can be accessed in one burst of the memory storing the block, efficient writing / reading of the block becomes possible. The amount of data per burst is generally a power of 2, but this value depends on the data width and burst length of the memory. When K increases, the amount of memory for holding data for one block increases, which causes a problem that the circuit scale of the write buffer unit 13 and the read buffer unit 14 increases.

Also, if K is smaller than the minimum packet length, the ratio of blocks that do not include a packet boundary increases, causing a problem that the memory used for block management information is wasted.
In addition, when the memory is divided into a plurality of banks, the bandwidth utilization efficiency of the memory can be improved by the multi-bank operation. Therefore, if K is an integral multiple of the data amount per burst × the number of banks A multi-bank operation can be realized with a simple circuit by performing one block access by a predetermined command issuing procedure to the memory. Examples of the value of K are 128, 256, 512, and 1024.

Since the block boundary is determined independently of the packet boundary, packet data of one packet is completely accommodated in one block, and cases where it is accommodated across a plurality of blocks. is there.
Each block includes, in addition to packet data, block management information having a fixed length (H bytes), and the position of the block management information in the block is determined. In this example, it is arranged close to the head side of the block, that is, the address minimum side.

In this example, the block management information has a packet data continuation flag indicating whether or not the packet data area of the block has been used, in addition to the packet boundary information. When the packet data continuation flag is “1”, it means that the packet data area is used up and that valid packet data is stored up to the end of the packet data area.
On the other hand, when the packet data continuation flag is “0”, it is after the end of the packet data included in the area (the end of the data of the last packet when a plurality of packets are accommodated in one block). Indicates that valid packet data is not stored.

  H is the number of bytes of the block management information. It is necessary to include packet end positions indicating packet boundary positions corresponding to the number of packets that can enter the block. When the packet end position is expressed as the number of bytes from the head of the block, one packet end position represents a value less than the number of bytes in the block, and therefore has a bit number equal to or greater than log2 (K-1). Further, when data in a block is handled in units of words instead of in units of bytes, it is matched with handling in units of words by defining the block management information to be stored in one word or a predetermined number of words.

Further, when the block management information includes a packet data continuation flag, at least one bit is required for the flag in addition to the block management information. When the minimum packet length is 64 bytes, examples of the value of H are 2, 4, 8, and 16, corresponding to K = 128, 256, 512, and 1024, respectively.
However, in the case of K = 512, 1024, it is assumed that the packet end position represents the number of words from the block head, not the number of bytes from the block head. This is because the packet end position can be expressed by a smaller number of bits than the number of bits that can be expressed as a binary number in the block. For example, when K = 512, if the packet end position is defined as the number of bytes from the head of the block, the length is 8 bits. However, if the 4-byte length word count from the block head is defined, the packet end position is 6 bits.

  The packet boundary information consists of M packet end positions. Each packet end position is represented by the position within the block of the last byte of packet data included in the block, that is, the number of bytes from the first byte of the packet data area to the last byte of the packet data. At this time, when the packet end position is “1”, the first byte of the packet data area is the last byte of the packet data. When the packet end position is a value of “0”, this means that the packet end position is invalid, and occurs when the number of end bytes of packet data included in one block is less than M. .

  M is the maximum number of packets that can enter a block. Therefore, M ≧ K / minimum packet length. When the minimum packet length is 64 bytes, examples of the value of M are M = 2, 4, 8, 16, and correspond to K = 128, 256, 512, 1024, respectively. However, it is assumed that the packet boundary position information represents the number of words from the block head, not the number of bytes from the block head.

[Write Operation of First Embodiment]
Next, the writing operation of the packet buffer device 10 according to the present embodiment will be described with reference to FIG. FIG. 3 is a state transition diagram showing a write operation according to the first embodiment.

In this writing operation, the following control variables are used.
The packet end position is a variable indicating the position of the last byte of each packet data, and is represented by the number of bytes from the first byte of the packet data area in one block data.
The variable i is a counter for counting the number of packet end bytes included in one block data.
The variable M is the maximum number of packets that can be included in one block data.
The storage position is a variable (byte address) that specifies the position when packet data is stored byte by byte in the packet data area in the write block buffer 13A.
The packet data continuation flag is a variable indicating whether or not the packet data area is used up.

[Initialization status]
The packet buffer device 10 transitions to an initialization state (step 100) after the power is turned on and before starting to input a packet, and executes an initialization process. The initialization is also performed when the packet buffer device 10 itself detects the occurrence of an abnormality in which normal operation cannot be maintained in the packet buffer device 10 or when there is a reset request from the outside.

  In the initialization state (step 100), the buffer control unit 11 initializes the write block buffer 13A. In this initialization process, the buffer control unit 11 initializes the values of the M packet end positions to “0” and initializes the value of the variable i to “0”. In addition, the buffer control unit 11 initializes the storage position of the write buffer unit 13. Thereby, the storage position is set at the head position of the packet data area.

  In the initialization state (step 100), the buffer control unit 11 transitions to an input wait state (step 101) in which the input of a packet is waited when the initialization is completed.

[Waiting for input]
In the input waiting state (step 101), when a packet is input, that is, when “input is present”, the buffer control unit 11 stores the packet data of the packet in the write block buffer 13A (data storage state ( Transition to step 102).

  In the input waiting state (step 101), when there is no packet input and there is a block accumulated in the memory unit 12 or there is no packet data held in the write buffer unit 13, that is, “input” In the case of “none and (with memory accumulation or no data retention)”, the buffer control unit 11 does not transition to another state but remains in an input waiting state (step 101) for waiting for packet input.

  The write buffer unit 13 holds the packet data in the write block buffer 13A until packet data for one block is prepared. For example, when one packet having packet data of 3.5 blocks in length is input to the write block buffer 13A in the initial state (empty state), the packet data includes three packets from the beginning. The data is divided into blocks in order and written to the memory unit 12, but for the remaining 0.5 blocks of packet data less than one block, the next packet is input in the write block buffer 13A. Therefore, it waits for the data for one block to be prepared.

In such a case, when the packet data is read from the memory unit 12, the data of the three blocks stored in the memory unit 12 are read, but the packet data remaining in the write block buffer 13A is read. Are not stored in the memory unit 12, the packet cannot be reproduced from the three block data read out from the memory unit 12 as it is.
Therefore, in such a situation, by making a transition to the block write 2 state (step 104), the remaining data remaining in the write block buffer 13A can be stored in the memory unit even if block data for one block is not prepared. By writing to 12, all the packet data can be read from the memory unit 12.

  That is, in the input waiting state (step 101), when there is no packet input, there is no block stored in the memory unit 12, and there is data held in the write buffer unit 13, that is, “no input and In the case of “No memory storage and data retention”, the buffer control unit 11 writes the block in the incomplete state to the memory unit 12 without waiting for the packet data for one block to be prepared, so that the block write 2 state Transition to (Step 104). This transition is for avoiding a situation where the packet data accumulated in the memory unit 12 without input is exhausted and the last data remaining in the write block buffer 13A is not output.

[Data storage status]
In the data storage state (step 102), the buffer control unit 11 stores the input packet data byte by byte at a position in the packet data area indicated by the storage position in the write block buffer 13A. The storage position is moved backward by 1 byte.

  Further, in the data storage state (step 102), when packet data follows and the packet data area of the writing block buffer 13A has an empty space, that is, “packet continuation and block less than end”, the buffer control unit 11 Stays in the data storage state (step 102) and continues to store the packet data.

  On the other hand, in the data storage state (step 102), when the packet data follows and the packet data area of the writing block buffer 13A is full, that is, when “packet continuation and block expiration”, the buffer control unit 11 Transitions to the block write 1 state (step 103), in which the block data held in the write block buffer 13A is written to the memory unit 12.

  Further, in the data storage state (step 102), when the packet data has been input to the write block buffer 13A up to the last byte, that is, at the “packet end”, the buffer control unit 11 sends a packet to the write block buffer 13A. Transition to the packet end position update state (step 105) in which the end position is stored.

[Data end position update status]
In the data end position update state (step 105), the buffer control unit 11 adds “1” to the value of the variable i.
Furthermore, when the last byte of the packet data is stored in the write block buffer 13A in the previous data storage state (step 102), the buffer control unit 11 stores the number of bytes corresponding to the storage position, that is, the write block The number of bytes from the beginning of the packet data area of the buffer 13A to the end byte is stored in the writing block buffer 13A as the packet end position #i included in the block management information.

In the data end position update state (step 105), when there is a vacancy in the packet data area of the write block buffer 13A, that is, when “less than block end”, the buffer control unit 11 transitions to an input waiting state (step 101). .
In addition, in the data end position update state (step 105), when there is no more space in the packet data area of the write block buffer 13A, that is, when “block expiration” occurs, the buffer control unit 11 is held in the write block buffer 13A. The block is written to the memory unit 12, and the state transits to the block write 2 state (step 104).

[Block write 1 status]
In the block write 1 state (step 103), the buffer control unit 11 sets the value of the packet data continuation flag held as block management information in the write block buffer 13A to “1” and holds it in the write block buffer 13A. The written block data is written to a predetermined address in the memory unit 12.

  Further, the buffer control unit 11 initializes the writing block buffer 13A. In this initialization, the values of the M packet end positions are initialized to “0”, and the variable i is initialized to “0”. Further, the storage position held in the write buffer unit 13 is initialized. Thereby, the storage position is set at the head position of the packet data area. Thereafter, the buffer control unit 11 transitions to a data storage state (step 102).

[Block write 2 status]
In the block write 2 state (step 104), the buffer control unit 11 initializes the value of the packet data continuation flag held as block management information in the write block buffer 13A to “0”, and writes the write block buffer 13A. The block data held in is stored in a predetermined address in the memory unit 12.

  Further, the buffer control unit 11 initializes the writing block buffer 13A. In this initialization, the values of the M packet end positions are initialized to “0”, and the variable i is initialized to “0”. Further, the storage position of the write buffer unit 13 is initialized to “0”. As a result, the storage position is set at the head position of the packet data area. Thereafter, the buffer control unit 11 transitions to an input waiting state (step 101).

  In the write operation described above, in the block write 1 state (step 103) or the block write 2 state (step 104), the block data held in the memory unit 12 is written. If the block is not accumulated in the block and the read buffer unit 14 does not hold the block, a process of storing the block in the read buffer unit 14 instead of writing in the memory unit 12 as described above may be performed. As a result, in the situation where the input packet is output without being stored, the storage in the memory unit 12 can be omitted, so that the power consumption in the memory unit 12 can be reduced.

[Read Operation of First Embodiment]
Next, the read operation of the packet buffer device 10 according to the present embodiment will be described with reference to FIG. FIG. 4 is a state transition diagram showing a read operation according to the first embodiment.

In this reading operation, the following control variables are used. Data holding / non-holding is a variable indicating whether data is held in the reading block buffer 14A.
The variable i is a counter for counting the number of packet end bytes included in one block data.
The variable M is the maximum number of packets that can be included in one block data.
The packet end position is a variable indicating the position of the last byte of each packet data, and is represented by the number of bytes from the first byte of the packet data area in one block data.

The storage position is a variable (byte address) that specifies a position when packet data is stored byte by byte in the packet data area in the read block buffer 14A.
The acquisition position is a variable (byte address) that specifies a position when packet data is acquired byte by byte from the packet data area in the read block buffer 14A.
The packet data continuation flag is a variable indicating whether or not the packet data packet data area is used up.

[Initialization status]
The packet buffer device 10 transitions to the initialization state (step 110) after the power is turned on and before starting the output of the packet, and executes the initialization process. The initialization is also performed when the packet buffer device 10 itself detects the occurrence of an abnormality in which normal operation cannot be maintained in the packet buffer device 10 or when there is a reset request from the outside.

  In the initialization state (step 110), the buffer control unit 11 initializes the read block buffer 14A. In this initialization process, the buffer control unit 11 initializes a value indicating whether data is retained without retaining data.

In this initialization, the buffer control unit 11 initializes the values of the M packet end positions to “0” and initializes the value of the variable i to “0”. Further, the buffer control unit 11 initializes the storage position of the read buffer unit 14. Thereby, the storage position is set at the head position of the packet data area.
In the initialization state (step 110), the buffer control unit 11 transitions to an input waiting state (step 111) where the input of the output instruction information is waited when the initialization is completed.

[Waiting for input]
In the input waiting state (step 111), the buffer control unit 11 remains in the input waiting state (step 111) waiting for the input of the output instruction information without transitioning to another state until the output instruction information is input.
Further, in the input waiting state (step 111), when the output instruction information is input, if the data holding presence / absence indicates that there is data holding, that is, “with input and with data holding”, the buffer control unit 11 Transitions to the data acquisition state (step 112).

  On the other hand, in the input waiting state (step 111), when the output instruction information is input, if the data holding presence / absence indicates no data holding, that is, “with input and no data holding”, the buffer control unit 11 Transitions to the block read state (step 113).

[Data acquisition status]
In the data acquisition state (step 112), the buffer control unit 11 acquires and outputs packet data byte by byte from the position indicated by the acquisition position from the read block buffer 14A, and also sets the acquisition position byte by byte. Move back. When packet data is not output in units of 1 byte but in units of a predetermined number of bytes, storage and storage position movement are performed in units of the number of bytes.

Further, in the data acquisition state (step 112), the buffer control unit 11 determines whether or not there is packet continuation / end and whether or not there is remaining data, that is, whether or not there is packet data before acquisition in the read block buffer 14A. .
At this time, the end of the packet indicates that the acquisition position has reached the position indicated by the packet end position #i stored in the read block buffer 14A, that is, that acquisition has been completed up to the last byte of the packet data being acquired. Judge as a condition. The variable i is also used as a variable for specifying the packet end position for the acquisition target packet among the M packet end positions included in the read block buffer 14A.

Further, the packet continuation is determined on condition that the condition for ending the packet is not satisfied. At this time, if the value of the packet end position #i is “0” or if i> M, it means that the last byte of the packet being acquired is not included in the read block buffer 14A but is included in the subsequent block. The determination is packet continuation.
On the other hand, the presence of remaining data means that the acquisition position has not reached the final byte position of the packet data area, and the condition of no remaining data is determined on the condition that the condition of remaining data is not satisfied.

  Further, in the data acquisition state (step 112), when the data acquisition is completed up to the last byte of the packet data, that is, at the time of “end of packet”, the buffer control unit 11 determines the data holding presence / absence value as follows: And then transitions to an input wait state (step 111).

In the above determination, when the acquisition position reaches the final byte position of the packet data area, the buffer control unit 11 first sets the data holding presence / absence value as not holding.
On the other hand, when the acquisition position has not reached the final byte position of the packet data area, the buffer control unit 11 adds “1” to the value of the variable i.

  At this time, after updating the variable i, the value of the packet end position #i stored in the read block buffer 14A is “0” or i> M, and the value of the packet data continuation flag is “1”. In this case, that is, in the case of “(i> M) or packet end position [i] == 0) and packet data continuation flag == 1”, the buffer control unit 11 sets the value of whether or not the data is retained as retained. .

On the other hand, when the value of the packet end position #i is “0” or i> M and the value of the packet data continuation flag is “0”, that is, “(i> M) or packet end position In the case of [i] == 0) and packet data continuation flag == 0, the buffer control unit 11 sets the data holding presence / absence value as no holding.
In addition, when the value of the packet end position #i is other than “0” and i ≦ M, the buffer control unit 11 sets the data holding / non-holding value as holding.

  Further, in the data acquisition state (step 112), when the packet is continuation and there is no remaining data, that is, “packet continuation and no remaining data”, the buffer control unit 11 reads out the blocks stored in the memory unit 12 Transition to the block read state (step 113) stored in the read block buffer 14A.

  On the other hand, in the data acquisition state (step 112), when there is packet continuation and there is remaining data, that is, “packet continuation and remaining data exists”, the buffer control unit 11 remains in the data acquisition state (step 112). The packet data is acquired from the read block buffer 14A and output.

[Block read status]
In the block read state (step 113), the buffer control unit 11 reads one block data from a predetermined address of the memory unit 12, and stores the block data in the read block buffer 14A. Further, the buffer control unit 11 initializes the value of the acquisition position to a value indicating the start position of the packet data area in the read block buffer 14A, initializes the value of the data holding presence / absence with holding, , The value of the variable i is initialized to “1”.

[Effect of the first embodiment]
As described above, the packet buffer device 10 according to the present embodiment includes a memory unit 12 that writes and reads data in units of blocks, which are fixed-length storage areas, and a write that holds data for at least the blocks. A block buffer 13A and a read block buffer 14A for holding at least the data for the block are provided, and the packet controller 11 sequentially stores the input packet data of variable length packets in the write block buffer 13A. At the same time, packet boundary information indicating the end position of the packet data in the write block buffer 13A is stored in the write block buffer 13A, and when a predetermined amount of data is stored in the write block buffer 13A. Write the data to the memory unit 12 In response to the input output instruction, the data is read from the memory unit 12 and stored in the read block buffer 14A, and each packet data included in the data is read based on the packet boundary information included in the data. Output.

  As a result, fixed-length block management information including packet boundary information generated for each input packet is connected to the packet data and stored in the queue of the memory unit 12. Therefore, according to the packet buffer device 10 according to the present embodiment, in order to store a conventional fixed-length packet job (job information), it is necessary to provide a job memory composed of SRAM separately from the queue. There is no. Therefore, even when the number of packets to be accumulated is increased, it is possible to suppress an increase in an extra circuit scale accompanying an increase in the data memory for accumulating packets.

Further, according to the present embodiment, since the memory unit 12 is accessed in units of blocks, the block length is set to an integral multiple of the amount of data written / read in one access when burst accessing the memory. Thus, the memory can be accessed efficiently.
Thereby, since the data bus width and clock frequency of the memory can be reduced, the circuit scale and the power consumption can be reduced.

In addition, according to the present embodiment, the block management information is arranged at a predetermined position in the block, and the block has a fixed length. Therefore, the block management information and the packet data are stored in the memory in which they are stored. The address value can be reliably identified.
Accordingly, even if a soft error or the like occurs in the memory and the packet data stored in the block in which the error has occurred cannot be normally read, the subsequent normal block and block management information can be read. For subsequent packets, the packet data can be read normally. Thereby, it is not necessary to add or check the parity for confirming that there is no error in the block management information, and it is possible to reduce the circuit for the parity calculation and holding. Further, even when an error occurs, an error recovery process that causes a serious effect of discarding even normal packets such as initialization of the memory unit 12 is not required.

  Further, since the packet boundary information is information indicating the position of the packet boundary in the block, the number of bits is smaller than the information indicating the position of the packet boundary in the entire memory. As a result, the rate at which the memory is occupied by the packet boundary information can be reduced, so that a large amount of packet data can be stored in the memory.

Hereinafter, the effects of the present embodiment will be described by comparing the present embodiment with the prior art.
Since the packet buffer device 10 according to the present embodiment does not require a job memory as described above, it is possible to suppress an increase in circuit scale accompanying an increase in the number of accumulated packets.

In the conventional packet buffer device, only the packet data is stored in the data memory, whereas in the packet buffer device 10 of the present invention, the block management information is stored in addition to the packet data, so the storage amount increases. However, by using a large-capacity memory such as SDRAM, it is possible to suppress an increase in circuit scale caused by the increase in the accumulation amount.
According to the present invention, packet data is stored as a block in a memory (SDRAM), but the data of the block is stored in a memory area connected to the memory area storing the block management information of the block.

By issuing one burst read command to the memory, at least a part of the block management information and the block data can be efficiently read from the memory.
On the other hand, when block management information and block data are stored separately in different areas of the memory, at least two of a read command for reading management information and a read command for reading data are read when the block is read. Commands must be issued to memory.

At this time, it is necessary to wait for a time from when a command is issued until the next command can be issued. This waiting time reduces the bandwidth utilization efficiency of the memory.
In addition, since the memory is accessed in units of blocks, the memory can be accessed efficiently by setting the block length to an integral multiple of the amount of data written / read in one access when burst accessing the memory. it can.
Thereby, the data bus width and clock frequency of the memory can be reduced, so that the circuit scale and power consumption can be reduced.

The block management information is arranged at a predetermined position in the block, and the block has a fixed length. Therefore, the block management information and the packet data are surely identified by the address value of the memory in which they are stored. can do.
Accordingly, even if a soft error or the like occurs in the memory and the packet data stored in the block in which the error has occurred cannot be normally read, the subsequent normal block and block management information can be read. For subsequent packets, the packet data can be read normally.

  Thereby, it is not necessary to add or check the parity for confirming that there is no error in the block management information, and it is possible to reduce the circuit for the parity calculation and holding. Further, even when an error occurs, an error recovery process that causes a serious effect of discarding even normal packets such as initialization of the memory unit 12 is not required.

  In the present invention, even when a soft error or the like occurs in the memory and a block including management information having an error is read, the subsequent block can be read, and the subsequent block including the packet boundary can be read. Packets accumulated in the buffer after the packet boundary in which the error has occurred can be read from the memory. This is because the block is a fixed length (all blocks have the same length), the memory is managed as a FIFO buffer in units of blocks, and the block management information is arranged at a predetermined position in the block. Because the position of the block management information and the block in the memory is determined regardless of the value of the block management information, an error in the value of the block management information causes an error in the subsequent reading position of the block or block management information. It is because it does not give.

  On the other hand, if the block has a variable length, and the block includes block management information including packet boundary position information such as the packet length and all data of one packet, the packet length read from the memory has an error. Then, the position on the memory where the next block is stored will be mistaken, the error occurs in the packet length of the block where the reading position is wrong, the reading of the next block is wrong, and so on. An error chain occurs, and an error occurs in all packets stored in the buffer after the packet in which the error has occurred.

  In the case where a job memory is provided separately and the packet storage location is stored in the job memory as a packet job, the above problem does not occur as in the present invention, but after the packet job is read from the job memory. The procedure of reading the packet data from the data memory is necessary, and when both the job memory and the data memory are arranged on the SDRAM, the memory bandwidth utilization efficiency decreases due to the waiting time until the packet job is read. . When arranged on an SRAM that can read out the job memory at high speed, the area per bit of the SRAM is larger than the area per bit of the SDRAM used for the data memory, so that the circuit is more than the present invention. The area increases.

  Further, since the packet boundary information is information indicating the position of the packet boundary in the block, the number of bits is smaller than the information indicating the position of the packet boundary in the entire memory. As a result, the rate at which the memory is occupied by the packet boundary information can be reduced, so that a large amount of packet data can be stored in the memory.

  In the present invention, a buffer is constituted by a FIFO buffer having a block as a storage unit. For example, when the block a is read, the storage position of the block b to be read next is a position moved by one block from the storage position of the block a, so there is no need to store the storage position of each block. Calculation can be performed based on the storage position of the block read out last. As a configuration for realizing the above, for example, there is a ring buffer arranged so that the areas of the respective blocks are adjacent in the arrangement of the respective blocks on the memory. In the above configuration, the position on the memory of the block to be written next and the position of the block to be read next can be known from the two pointers indicating the write block position and the read block position of the ring buffer. Therefore, a table or the like for storing the position on the memory for each block is unnecessary.

  An example of the memory capacity of the job memory in the conventional example is shown below. Assuming that the memory capacity of the data memory is 8 MB and the minimum frame length is 64 bytes, a maximum of 8000000/64 = 125000 frames can be stored in the data memory. If the data width of the data memory is 4 bytes, the number of addresses is 8000000/4 = 2000000. Therefore, the number of bits for expressing the address in binary is 21 (an integer greater than or equal to log 2 (2000000)).

  Therefore, when one packet job is stored in the job memory for each accumulated packet and the address of the data memory storing the packet is stored in the packet job, the bit number of each packet job is 21 bits, and the data is stored in the job memory. The number of stored packet jobs is 125,000, the same as the maximum number of stored frames, and the memory capacity of the job memory is 21 bits × 125000 = 22625000 bits = 328 kBytes.

  On the other hand, in the present invention, assuming that the block length = 256 bytes and the block management information = 4 bytes, the number of blocks for storing 8 Mbytes of data is 8 MByte / (256 bytes−4 bytes) = 31746, and the packet job The amount of memory required for the block management information corresponding to is 4 bytes × 31746 = 127 Kbytes. Since the maximum number of packets entering a block is four, it is sufficient that one block management information can hold the boundary positions of four packets. If the packet boundary position is expressed as the number of bytes from the head of the block, the number of bits of each packet boundary information is enough to be 8 bits. Therefore, one block management information only needs to have a length of 4 bytes or more.

The area of the job memory when the memory amount of 328 kByte of the job memory is realized by the SRAM is about mm although it depends on the manufacturing process. That is, when the DRAM is excluded from the circuit area as an external device of the circuit, according to the present application, mm, which is the area for the job memory, can be reduced from the circuit area. Regarding the area reduction when the areas of the DRAM are combined, if the present application (block length = 256 bytes, management information of 1 block = 4 bytes) is adopted, the DRAM will increase by 127 Kbytes as management information. Job memory is not required. If the area per bit of the DRAM is 1/4 of the area per bit of the SRAM, the area of the DRAM is increased by 0.8 mm ² as management information. Therefore, the circuit area of 8−0.8 = 7.4 mm ² can be reduced according to the present application.

  Further, while the DRAM used as the data memory has a substantially constant power consumption regardless of the amount of memory, the SRAM used as the job memory increases with the amount of memory. Even when the area of the management information is increased in this application, the power consumed by the DRAM is the same in the conventional example and the present application because the DRAM has a constant power regardless of the amount of memory. Since no job memory is required in the present application, the power consumption equivalent to the above, 700 mW, can be reduced by adopting the present application. The memory area and power were calculated with reference to, for example, the document http://www2.renesas.com/process/en/edramadvantages.html.

  As described above, the block management information corresponding to the packet job can be stored in the conventional example with a small amount of memory (in the above specific example, the amount of memory is about 39% of the job memory size of the conventional example).

  In general, when storing a plurality of packet data in a fixed-length block, the head address of the block is specified by a calculation formula from the block number, and the packet data is stored in each block based on the head address. be able to. Furthermore, if the packet data has a fixed length, it is also possible to specify the start address of the packet data stored in the block by a calculation formula, assuming that the packet data is stored from a predetermined address in the block. is there.

However, when the packet data of the present invention has a variable length, the above method cannot specify the start address of the packet data stored in the block. Therefore, it is necessary to manage the same management information as the packet job (job information) described above in a separate memory for each block, and the circuit scale increases with the increase in these memories.
On the other hand, according to the packet buffer device 10 according to the present embodiment, the block management information provided for each block includes the packet boundary information indicating the end position of the packet data stored in the block. . For this reason, the start address of each packet data stored in the block can be specified very easily based on this packet boundary information, and an increase in the extra circuit scale accompanying an increase in memory can be suppressed. It becomes possible.

[Second Embodiment]
Next, the packet buffer device 10 according to the second embodiment of the present invention will be described.
The packet buffer device 10 according to the present embodiment has the same configuration as that of the first embodiment shown in FIG. 1, but is partially different from the state transition shown in FIGS. As a result, the internal structure of the blocks stored in the memory unit 12 is different.

FIG. 5 is a configuration example of a memory unit according to the second embodiment.
In the packet buffer device 10 according to the present embodiment, as shown in FIG. 5, the memory unit 12 stores packets in block units of fixed length (K words, each word is K bits) by the buffer control unit 11. It is controlled as follows.
In this example, a memory area in the memory unit 12 where addresses are continuous is divided into K words to form blocks, and each time packet data is input, the blocks are stored in order from the smallest address.

Since the block boundary is determined independently of the packet data boundary, there is a case where one packet data is completely accommodated in one block and a case where it is accommodated across a plurality of blocks. is there.
Each block includes, in addition to packet data, fixed-length block management information consisting of, for example, one word, and the storage position of this block management information is fixed in each block. In this example, the block management information is arranged close to the head side of the block, that is, the address minimum side.

  When the block management information is placed in the first read position in the block and stored in the memory, the packet data that is not divided and stored in multiple blocks is divided and stored in multiple blocks compared to when reading from the memory. Even in the case of packet data, it is possible to avoid a decrease in the bandwidth utilization efficiency of the memory when reading the packet data from the memory, and to read a plurality of blocks including the divided packet data from the memory without interruption.

  This is due to the following operations. From the block management information that is read first when reading a block, it is determined whether or not the end of the packet is included in the block. If the end of the packet is not included, a command to read the block that continues to the block is issued to the memory . That is, by storing the block management information at a position where it is first read out in the block, immediately after reading out the block from the memory, it is possible to determine whether or not the end of the packet is included in the block. When the end of the packet is not included, reading of the next block can be started early. For this reason, the time between reading of a block and reading of the next block can be minimized.

  The packet data area of each block accommodates packet data composed of K-1 words. Here, in the word including the first byte of the packet data, the first byte is arranged in the first byte of the word. Further, a predetermined packet end pattern is set after the last byte of the packet data.

  In this example, the packet end pattern is composed of a packet end byte and a packet end pad pattern. That is, a byte next to the end byte of the packet data is set as a packet end byte having a value “0”, and a packet is included between the packet end byte and the first byte of the next packet data, that is, within a word including the packet end byte. A packet end pad pattern having a byte value of “255” is inserted from the end of the end byte to the end of the word. When the packet end byte is located at the end of the word, the end pad pattern is not inserted. When the last byte of the packet data comes to the end of the word, the subsequent packet end byte is the beginning of the next word, and the end pad pattern is inserted up to the end of the word.

The block management information is composed of one bit of the packet data continuation flag and K−1 boundary determination bit strings indicating whether or not each word constituting the packet data area includes a packet end byte.
The packet data continuation flag indicates whether or not the packet data area of the block is used up. When the packet data continuation flag is “1”, it means that the packet data area is used up and that valid packet data is stored up to the end of the packet data area. On the other hand, when the packet data continuation flag is “0”, it is after the end of the packet data included in the area (the end of the data of the last packet when a plurality of packets are accommodated in one block). Indicates that valid packet data is not stored.

  In this example, since the number of bits of one word matches the number of words included in one block, one word of the block management information is composed only of a packet data continuation flag and a boundary determination bit string. However, when the number of bits of one word <the number of words included in one block, the block management information is composed of two or more words. If the number of bits in one word> the number of words included in one block, the block management information includes a parity calculated by a predetermined method for each block in addition to the packet data continuation flag and the boundary determination bit string. The number of words in the block management information can be made larger than the number of words when only the packet data continuation flag and the boundary determination bit string are included, and the parity can be included in the block management information.

[Write Operation of Second Embodiment]
Next, the write operation of the packet buffer device 10 according to the present embodiment will be described with reference to FIG. 3 described above. The read operation according to the present embodiment is different in part of the state transition diagram of FIG.

In this writing operation, the following control variables are used.
The boundary determination bit is a variable indicating whether or not the packet end byte exists in the word for each word.
The variable i is a counter for counting the number of packet end bytes included in one block data.
The storage position is a variable (word address) that specifies a position when packet data is stored word by word in the packet data area in the write block buffer 13A.
The packet data continuation flag is a variable indicating whether or not the packet data packet data area is used up.

[Initialization status]
In the initialization state (step 100), the buffer control unit 11 initializes the write block buffer 13A. In this initialization process, the buffer control unit 11 sets the values of all the boundary determination bits of the write block buffer 13A to “0”. Also, the storage position of the write buffer unit 13 is initialized. Thereby, the storage position is set at the head position of the packet data area.
In the initialization state (step 100), the buffer control unit 11 transitions to an input wait state (step 101) in which the input of a packet is waited when the initialization is completed.

[Waiting for input]
In the input waiting state (step 101), when a packet is input, that is, when “input is present”, the buffer control unit 11 stores the packet data of the packet in the write block buffer 13A (data storage state ( Transition to step 102).

  In the input waiting state (step 101), when there is no packet input and there is a block accumulated in the memory unit 12 or there is no packet data held in the write buffer unit 13, that is, “input” In the case of “none and (with memory accumulation or no data retention)”, the buffer control unit 11 does not transition to another state but remains in an input waiting state (step 101) for waiting for packet input.

  In the input waiting state (step 101), when there is no packet input, there is no block stored in the memory unit 12, and there is packet data held in the write buffer unit 13, that is, “no input” In the case of “and (without memory accumulation and data retention)”, the buffer control unit 11 writes the block in the incomplete state to the memory unit 12 without waiting for packet data for one block to be prepared, so that the block write 2 Transition to the state (step 104). This transition is for avoiding a situation in which the packet data stored in the memory unit 12 without input is exhausted and the last packet data remaining in the writing block buffer 13A is not output.

[Data storage status]
In the data storage state (step 102), the buffer control unit 11 stores the input packet data word by word at a position in the packet data area indicated by the storage position in the write block buffer 13A. The storage position is moved backward by one word. The packet data is divided in units of words so that the first byte of the packet data is the start position of the word including the byte.

  Further, in the data storage state (step 102), when packet data follows and the packet data area of the writing block buffer 13A has an empty space, that is, “packet continuation and block less than end”, the buffer control unit 11 Stays in the data storage state (step 102) and continues the data storage.

  On the other hand, in the data storage state (step 102), when the packet data follows and the packet data area of the writing block buffer 13A is full, that is, when “packet continuation and block expiration”, the buffer control unit 11 Changes to the block writing 1 state (step 103), in which the block held in the writing block buffer 13A is written to the memory unit 12.

  Further, in the data storage state (step 102), when the data has been input up to the last byte of the packet data, that is, at the “packet end”, the buffer control unit 11 stores the packet end position in the write block buffer 13A. , Transition to the packet end position update state (step 105).

[Data end position update status]
In the data end position update state (step 105), the buffer control unit 11 stores the packet end pattern following the end byte of the packet data included in the last word stored in the data storage state. In this example, the packet end byte having the value “0” is stored in the byte position next to the end byte of the packet data, and the byte position next to the packet end byte is included in the word including the packet end byte. To the end byte position of the word, a packet end pad pattern having each byte value “255” is stored. Further, in the data end position update state (step 105), the buffer control unit 11 stores “1” in the boundary determination bit corresponding to the word storing the packet end byte.

In the data end position update state (step 105), when there is an empty packet data area in the writing block buffer 13A, that is, when “less than block end”, the buffer control unit 11 enters the input waiting state (step 101). Transition.
On the other hand, in the data end position update state (step 105), when there is no more space in the packet data area of the write block buffer 13A, that is, when “block expiration” occurs, the buffer control unit 11 is held in the write block buffer 13A. The block is written to the memory unit 12, and the state transits to the block write 2 state (step 104).

[Block write 1 status]
In the block write 1 state (step 103), the buffer control unit 11 sets the value of the packet data continuation flag held in the block management information in the write block buffer 13A to “1” and holds it in the write block buffer 13A. The written block data is written to a predetermined address in the memory unit 12.

  Further, the buffer control unit 11 initializes the writing block buffer 13A. In this initialization, the values of all boundary determination bits are set to “0”. Also, the storage position of the write buffer unit 13 is initialized. As a result, the storage position is set to the first word of the packet data area. Thereafter, the buffer control unit 11 transitions to a data storage state (step 102).

[Block write 2 status]
In the block write 2 state (step 104), the buffer control unit 11 initializes the value of the packet data continuation flag held in the write block buffer 13A to “0” and is held in the write block buffer 13A. The block data is written to a predetermined address in the memory unit 12.

  Further, the buffer control unit 11 initializes the writing block buffer 13A. In this initialization, the values of all boundary determination bits are initialized to “0”, and the storage position of the write buffer unit 13 is initialized to “0”. As a result, the storage position is set to the first word of the packet data area. Thereafter, the buffer control unit 11 transitions to an input waiting state (step 101).

  In the writing operation described above, in the block writing 1 state (step 103) or the block writing 2 state (step 104), a process of writing block data held in the memory unit 12 is performed. If the block is not stored in the block and the block is not held in the read block buffer 14A, a process of storing in the read block buffer 14A instead of writing in the memory unit 12 as described above may be performed. As a result, in the situation where the input packet is output without being stored, the storage in the memory unit 12 can be omitted, so that the power consumption in the memory unit 12 can be reduced.

[Read Operation of Second Embodiment]
Next, the read operation of the packet buffer device 10 according to the present embodiment will be described with reference to FIG. Note that the read operation according to the present embodiment is different in part of the state transition diagram of FIG.

In this reading operation, the following control variables are used. Data holding / non-holding is a variable indicating whether data is held in the reading block buffer 14A.
The variable i is a counter for counting the number of packet end bytes included in one block data.
The packet end position is a variable indicating the position of the last byte of each packet data, and is represented by the number of bytes from the first byte of the packet data area in one block data.

The storage position is a variable (word address) that specifies a position when packet data is stored word by word in the packet data area in the read block buffer 14A.
The acquisition position is a variable (word address) that specifies a position when packet data is acquired word by word from the packet data area in the read block buffer 14A.
The packet data continuation flag is a variable indicating whether or not the packet data packet data area is used up.

[Initialization status]
In the initialization state (step 110), the buffer control unit 11 initializes the read block buffer 14A. In this initialization process, the buffer control unit 11 initializes a value indicating whether data is retained without retaining data.
In the initialization state (step 110), the buffer control unit 11 transitions to an input waiting state (step 111) where the input of the output instruction information is waited when the initialization is completed.

[Waiting for input]
In the input waiting state (step 111), the buffer control unit 11 remains in the input waiting state (step 111) waiting for the input of the output instruction information without transitioning to another state until the output instruction information is input.
Further, in the input waiting state (step 111), when the output instruction information is input, if the data holding presence / absence indicates that there is data holding, that is, “with input and with data holding”, the buffer control unit 11 Transitions to the data acquisition state (step 112).

  On the other hand, in the input waiting state (step 111), when the output instruction information is input, if the data holding presence / absence indicates no data holding, that is, “with input and with data holding”, the buffer control unit 11 Transitions to the block read state (step 113).

[Data acquisition status]
In the data acquisition state (step 112), the buffer control unit 11 acquires and outputs packet data from the read block buffer 14A from the position indicated by the acquisition position one word at a time. Move back.

Further, in the data acquisition state (step 112), the buffer control unit 11 determines whether the packet continues / ends and whether there is remaining data.
At this time, the end of the packet indicates that the boundary determination bit corresponding to the word acquired from the read block buffer 14A is “1” (including the packet end byte in the word), that is, the end of the packet data being acquired. Judgment is made on the condition that acquisition to the byte is completed. Further, the packet continuation is determined on condition that the condition for ending the packet is not satisfied.

  On the other hand, the presence of remaining data means that the acquisition position has not reached the final word position of the packet data area, and the condition of no remaining data is determined on the condition that the condition of remaining data is not satisfied.

  Further, in the data acquisition state (step 112), when the data acquisition is completed up to the last byte of the packet data, that is, at the time of “end of packet”, the buffer control unit 11 determines the data holding presence / absence value as follows: And then transitions to an input wait state (step 111).

In the above determination, the buffer control unit 11 first determines that there is no holding when the acquisition position reaches the final word position of the packet data area.
On the other hand, if the acquisition position has not reached the final word position of the packet data area and the value of the packet data continuation flag is “1”, the data is held.

Further, when the acquisition position has not reached the final word position of the packet data area, and the value of the packet data continuation flag is “0”, and after the acquired word in the packet data area If a boundary determination bit corresponding to a word includes a value having a value of “1”, the word is held.
Other than the above, there is no holding.

  Further, in the data acquisition state (step 112), when the packet is continuation and there is no remaining data, that is, “packet continuation and no remaining data”, the buffer control unit 11 reads out the blocks stored in the memory unit 12 Thus, a transition is made to the block read state (step 113) stored in the read block buffer 14A.

  On the other hand, in the data acquisition state (step 112), when there is packet continuation and there is remaining data, that is, “packet continuation and remaining data exists”, the buffer control unit 11 remains in the data acquisition state (step 112). The packet data is acquired from the read block buffer 14A and output.

[Block read status]
In the block read state (step 113), the buffer control unit 11 reads one block from a predetermined address in the memory unit 12, and stores the block in the read block buffer 14A. In addition, the buffer control unit 11 initializes the variable value indicating the acquisition position to a value indicating the start word position of the packet data area in the read block buffer 14A, and initializes the data holding presence / absence value with holding. To do.

[Effect of the second embodiment]
Thus, in the packet buffer device 10 according to the present embodiment, the block of the memory unit 12 is divided into a plurality of words each having a fixed length of a plurality of bytes, and the packet control unit 11 When storing the block management information in the write block buffer 13A, the block management information is stored from the first word of the word in the write block buffer 13A, and the packet data is written to the write block buffer 13A When selecting the word for storage in order from the next word of the first word storing the last byte of the block management information, and storing the packet data in the selected word, the packet in order from the first byte of the word Stores each byte of data and the last byte of the packet data When a predetermined packet end pattern is stored from the byte next to the specified byte and the block management information is stored in the write block buffer 13A, the last byte of the packet data in each word instead of the packet boundary information The block management information including a boundary determination bit string indicating the presence / absence of the block is stored.

Thereby, according to the packet buffer device 10 according to the present embodiment, the block management information and the packet data can be set to an integer multiple of a fixed-length word, and processing in a larger word unit, not a byte unit, can be performed. This makes it possible to simplify the write buffer circuit.
Further, since the boundary determination bit string is used as packet boundary information, it is not necessary to count the number of bytes from the first byte of the block, and the circuit for generating the packet boundary information can be simplified. Similarly, a circuit for extracting individual packets from a block based on packet boundary information can be simplified.

The above effect will be described below.
In the second embodiment, block management information and packet data are handled in units of fixed-length words, but in the first embodiment, they are handled in units of bytes.
The header containing information indicating the destination and source of the packet is at a fixed position based on the first byte of the packet data, and when processing the packet, for example, when the device has multiple ports that input and output the packet Packet data headers, such as deciding which port to output according to the header value of the packet, or deciding which queue to store packets according to the header value of the packet when multiple queues are provided The process of reading the value of is performed.

In the above processing, packet data is not a byte string but a word string, and a circuit is generally configured as a process for the word string to reduce the clock frequency of the circuit.
Here, in a circuit in which the packet first byte may appear in any byte in the word, the position of the packet first byte in the word is taken into account when reading the header value from the word string of the packet data. Processing is required.

  On the other hand, when the packet head byte is packet data arranged so that it appears only in the first byte in the word, the above consideration is not necessary, and the circuit for processing the header can be simplified. . For this reason, it is common practice to align the first byte of the packet so that it appears only in the first byte in the word.

The second embodiment is suitable for a circuit that handles the above-mentioned packet head byte position as a word string arranged so as to appear only in the first byte in the word.
That is, the packet buffer device 10 according to the second embodiment is in the subsequent stage or the previous stage of the device that handles the packet head byte position as a word string arranged so as to appear only in the first byte in the word. If the signal format is a word string aligned so that the first byte position of the packet appears only in the first byte in the word, it can be blocked and stored in the memory while maintaining the signal format. The signal format conversion required in the packet buffer device 10 according to the first embodiment, which handles packet data as a byte string, becomes unnecessary.

  When the above signal format is used for the signal between devices, a signal indicating whether or not the word string indicates a packet boundary is required in addition to the signal line for communicating the word string. If the bit values of the packet boundary signal are arranged in the order of the words stored in the block, the boundary determination bit string in the second embodiment can be obtained. For this reason, the circuit for generating the boundary determination bit string and generating the block management information in the second embodiment uses the packet end byte from the block start position for generating the packet end position in the first embodiment. This can be simplified because it is not necessary to count the number of bytes up to and the number of packet end bytes included in the data held in the write block buffer 13A.

[Third Embodiment]
Next, the packet buffer device 10 according to the present embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram illustrating a configuration of a packet buffer device according to the third embodiment.
In the first embodiment described above, the case where the packet data of each input packet is stored in the memory unit 12 is described as an example in units of blocks each including a fixed-length storage area. In this embodiment, a partition is constituted by a plurality of blocks, and packet data of each input packet is accumulated in blocks in the partition corresponding to the designated queue.

  This packet buffer device 10 includes write position information in addition to the buffer control unit 11, the memory unit 12, the write buffer unit 13, and the read buffer unit 14 in the first embodiment shown in FIG. A holding unit 21, a reading position information holding unit 22, a connected partition information holding unit 23, and an empty partition information holding unit 24 are provided.

  The write position information holding unit 21 includes a write partition identifier that is a partition identifier for identifying a partition where packet data is to be written to the memory for each queue, and a write partition information indicating a position at which writing is started in the partition. The function of holding the position information and the value of the queue identifier from the buffer control unit 11, and the buffer control unit 11 receives the value of the write partition identifier and the position information in the write partition of the queue specified by the queue identifier. Or a queue identifier value and an updated write partition identifier and write partition position information value of the queue specified by the queue identifier from the buffer control unit 11, The values of the writing partition identifier and the writing partition position information held for the above are written in the updated writing partition identifier and writing partition position information values. And it has a function and a frog. These functions can be realized by a memory circuit which uses the value of the queue identifier as an address and holds the value of the corresponding write partition identifier and the value of the position information in the write partition in the word specified by the address.

  The read position information holding unit 22 reads, for each queue, a read section identifier that is a section identifier that identifies a section from which packet data is to be read from the memory, and read section position information that indicates the position at which reading is started in the section. And a function of receiving the value of the queue identifier from the buffer control unit 11 and outputting the value of the read partition identifier and the read partition position information of the queue specified by the queue identifier to the buffer control unit 11; Alternatively, the value of the queue identifier and the updated read section identifier and the value of the position information in the read section of the queue specified by the queue identifier are received from the buffer control unit 11, and the read section held for the queue The value of the identifier and the position information in the reading section is changed to the value of the updated reading section identifier and the position information in the reading section. And a can replace function. These functions can be realized by a memory circuit that uses the value of the queue identifier as an address, and holds the value of the corresponding read partition identifier and the value of position information in the read partition in the word specified by the address.

The connected partition information holding unit 23 receives, for each partition, a function of holding a connected partition identifier that is a partition identifier that identifies a partition connected to the partition, and a value of the partition identifier from the buffer control unit 11. A function of outputting a value of a connected partition identifier that specifies a partition connected to the partition specified by the partition identifier, or a value of the partition identifier from the buffer control unit 11 and an update of the partition specified by the partition identifier are updated. A function of receiving the value of the connected partition identifier and rewriting the value of the connected partition identifier held for the partition to the updated read partition identifier and the value of the position information in the read partition. These functions can be realized by a memory circuit that uses the value of the partition identifier as an address and holds the value of the linked partition identifier corresponding to the word specified by the address.
In the present embodiment, the connected partition information holding unit 23 can hold M as the value of the connected partition identifier, which means that there is no connected partition.

  The free partition information holding unit 24 is a free partition concatenation that is a partition identifier that identifies the first partition of the free partition list so that the buffer control unit 11 manages a partition in which packet data is not stored as a list of free partitions. A function of holding a start identifier and a free partition connection end identifier that is a partition identifier for specifying the last partition in the free partition list, and the buffer control unit 11 are provided with values of a free partition connection start identifier and a free partition connection end identifier. The updated empty partition connection start identifier and the empty partition connection end identifier values received from the function to be output or the buffer control unit 11, and the stored empty partition connection start identifier and empty partition connection end identifier values are retained. And a function of changing to the updated value. These functions can be realized by a memory circuit which uses the value of the partition identifier as an address and holds the values of the corresponding free partition connection start identifier and the free partition connection end identifier in the word specified by the address.

FIG. 7 is a configuration example of the memory unit (block division).
As shown in FIG. 7, the memory unit 12 is divided into a plurality of non-overlapping address ranges by the buffer control unit 11, and managed as the divided plurality of partitions. In this embodiment, it is divided into M sections. M is an integer that takes a value equal to or greater than the number N of queues. The constraint on M is a constraint necessary to allow packets to be stored in all queues simultaneously, and in embodiments where it is not necessary to store packets in all queues simultaneously, the constraints are not necessary. The number assigned to each partition when the memory unit 12 is sorted in the order of addresses is used as a partition identifier for specifying the partition, and the value is any one of integers from 0 to M-1. Take.

  Each partition is further divided into a plurality of non-overlapping address ranges and managed by a fixed-length K-byte block, and a maximum of B blocks can be stored in one partition. . Thus, the memory unit 12 sequentially writes / reads packet data in units of blocks when writing / reading packet data for an arbitrary partition based on the control from the buffer control unit 11.

FIG. 8 is an explanatory diagram of a packet data accumulation state in the memory unit according to the third embodiment.
In the present embodiment, the memory area 12 of the memory section 12 is divided into K bytes each for a memory area where addresses are continuous, and B blocks are provided. The blocks are stored in the order of packet input from the block with the smaller address.
B is the number of blocks included in each section, but the value of B is a natural number and there is no limit on the value. However, since the value of B × K × M is a value that should be larger than the total number of bytes of data to be stored in the packet buffer, the range of values of B, K, and M is determined, and the data to be stored in the packet buffer When the total number of bytes is defined, the range that B can take is practically restricted by the above equation.

  When data is written to or read from a memory area in a certain partition, a pointer that expresses the position in the partition, for example, the number of words from the first word of the partition as a binary number, is used. In the case of updating the pointer value when the partition is used as a FIFO, etc., if B is a power of 2, the arithmetic circuit can be configured easily.

On the other hand, the value of M should be equal to or greater than the number N of queues. When M = N, one partition can be assigned to each queue. However, when M <N, a queue to which no partition is assigned is generated.
When the total number of bits of data to be accumulated in the packet buffer is specified, the number of bits in each partition can be reduced by increasing the value of M. As a result, it is possible to reduce the size of the free area that does not store data among the partitions allocated to the queue. This is because it becomes about the amount.

Therefore, when M is increased, the memory utilization efficiency is improved, and the required memory amount can be made close to the total number of bits of data to be stored in the packet buffer. In this case, since the situation where the partition is allocated to each queue but was not used for accumulation is the situation where there is the most free space, the number of partitions used for accumulation / the total number of partitions = (M−N) / M is the memory. A value corresponding to the utilization efficiency.
However, if M is increased, the number of partitions to be managed by the buffer control unit 11 increases. Therefore, a connected partition information holding unit 23 that holds the partition connection state of each queue, and a free partition information holding unit 24 that manages empty partitions. The circuit scale increases. That is, if the memory utilization efficiency approaches 100%, the increase in the circuit scale becomes a problem. Therefore, M = N × 5 to N × 10, which is an index when the utilization efficiency is changed from 80% to 90%. The degree is a practical range.

  K is the number of bytes in one block, and by making the value of K an integer multiple of the amount of data that can be accessed in one burst of the memory storing the block, efficient writing / reading of the block becomes possible. The amount of data per burst is generally a power of 2, but this value depends on the data width and burst length of the memory. When K increases, the amount of memory for holding data for one block increases, which causes a problem that the circuit scale of the write buffer unit 13 and the read buffer unit 14 increases.

Also, if K is smaller than the minimum packet length, the ratio of blocks that do not include a packet boundary increases, causing a problem that the memory used for block management information is wasted.
In addition, when the memory is divided into a plurality of banks, the bandwidth utilization efficiency of the memory can be improved by the multi-bank operation. Therefore, if K is an integral multiple of the data amount per burst × the number of banks A multi-bank operation can be realized with a simple circuit by performing one block access by a predetermined command issuing procedure to the memory. Examples of the value of K are 128, 256, 512, and 1024.

Since the block boundary is determined independently of the packet boundary, packet data of one packet is completely accommodated in one block, and cases where it is accommodated across a plurality of blocks. is there.
Each block includes, in addition to packet data, block management information having a fixed length (H bytes), and the position of the block management information in the block is determined. In this example, it is arranged close to the head side of the block, that is, the address minimum side.

In this example, the block management information has a packet data continuation flag indicating whether or not the packet data area of the block has been used, in addition to the packet boundary information. When the packet data continuation flag is “1”, it means that the packet data area is used up and that valid packet data is stored up to the end of the packet data area.
On the other hand, when the packet data continuation flag is “0”, it is after the end of the packet data included in the area (the end of the data of the last packet when a plurality of packets are accommodated in one block). Indicates that valid packet data is not stored.

  H is the number of bytes of the block management information. It is necessary to include packet end positions indicating packet boundary positions corresponding to the number of packets that can enter the block. When the packet end position is expressed as the number of bytes from the head of the block, one packet end position represents a value less than the number of bytes in the block, and therefore has a bit number equal to or greater than log2 (K-1). Further, when data in a block is handled in units of words instead of in units of bytes, it is matched with handling in units of words by defining the block management information to be stored in one word or a predetermined number of words.

Further, when the block management information includes a packet data continuation flag, at least one bit is required for the flag in addition to the block management information. When the minimum packet length is 64 bytes, examples of the value of H are 2, 4, 8, and 16, corresponding to K = 128, 256, 512, and 1024, respectively.
However, in the case of K = 512, 1024, it is assumed that the packet end position represents the number of words from the block head, not the number of bytes from the block head. This is because the packet end position can be expressed by a smaller number of bits than the number of bits that can be expressed as a binary number in the block. For example, when K = 512, if the packet end position is defined as the number of bytes from the head of the block, the length is 8 bits. However, if the 4-byte length word count from the block head is defined, the packet end position is 6 bits.

  The packet boundary information consists of P packet end positions. Each packet end position is represented by the position within the block of the last byte of packet data included in the block, that is, the number of bytes from the first byte of the packet data area to the last byte of the packet data. At this time, when the packet end position is “1”, the first byte of the packet data area is the last byte of the packet data. When the packet end position is a value of “0”, it means that the packet end position is invalid, and occurs when the number of end bytes of packet data included in one block is less than P. .

  P is the maximum number of packets that can enter a block. Therefore, P ≧ K / minimum packet length. When the minimum packet length is 64 bytes, examples of the value of P are P = 2, 4, 8, and 16, corresponding to K = 128, 256, 512, and 1024, respectively. However, it is assumed that the packet boundary position information represents the number of words from the block head, not the number of bytes from the block head.

[Write Operation of Third Embodiment]
Next, referring to FIG. 9, in the packet buffer device 10 according to the present embodiment, in response to the input of the queue input instruction information, the packet data of the input packet is transferred to the write block buffer 13A in units of words. A writing operation in which data is sequentially written and then written in a corresponding partition in the memory unit 12 in units of blocks will be described. FIG. 9 is a state transition diagram showing a write operation according to the third embodiment. Of the write operation, the details of the block write operation in the block write 1 state (step 203) and the block write 2 state (step 204) will be described later with reference to FIG.

In this writing operation, the following control variables are used.
The packet end position is a variable indicating the position of the last byte of each packet data, and is represented by the number of bytes from the first byte of the packet data area in one block data.
The variable P is the maximum number of packets that can be included in one block data.
The variable i is a counter for counting the number of packet end bytes included in one block data, and takes a value equal to or less than the maximum value P.
The storage position is a variable (byte address) that specifies the position when packet data is stored byte by byte in the packet data area in the write block buffer 13A.
The packet data continuation flag is a variable indicating whether or not the packet data area is used up.

[Initialization status]
The packet buffer device 10 transitions to the initialization state (step 200) after the power is turned on and before the packet input is started, and executes the initialization process. The initialization is also performed when the packet buffer device 10 itself detects the occurrence of an abnormality in which normal operation cannot be maintained in the packet buffer device 10 or when there is a reset request from the outside.

  In the initialization state (step 200), the buffer control unit 11 initializes the write block buffer 13A. In this initialization process, the buffer control unit 11 initializes the values of the M packet end positions to “0” and initializes the value of the variable i to “0”. In addition, the buffer control unit 11 initializes the storage position of the write buffer unit 13. Thereby, the storage position is set at the head position of the packet data area.

  In the initialization state (step 200), the buffer control unit 11 transitions to an input waiting state (step 201) where the input of the packet is waited when the initialization is completed.

[Waiting for input]
In the input waiting state (step 201), when a packet is input, the buffer control unit 11 determines whether or not packet data can be stored. At this time, whether or not storage is possible is determined by determining that the state (block) in the writing partition in the current writing partition is expired and that the connected partition is not connected cannot be stored, and storing other states. Judge that it is possible.
Therefore, when there is an input of a packet and the packet can be accumulated, that is, when “input and memory accumulation is possible”, the buffer control unit 11 stores the packet data of the packet in the write block buffer 13A. To the data storage state (step 202).

  In the input waiting state (step 201), when there is no packet input and there is a block accumulated in the memory unit 12, or there is no packet data held in the write buffer unit 13, that is, “input” In the case of “none and (with memory accumulation or no data retention)”, the buffer control unit 11 remains in an input waiting state (step 201) waiting for input of a packet without transitioning to another state.

  The write buffer unit 13 holds the packet data in the write block buffer 13A until packet data for one block is prepared. For example, when one packet having packet data of 3.5 blocks in length is input to the write block buffer 13A in the initial state (empty state), the packet data includes three packets from the beginning. The data is divided into blocks in order and written to the memory unit 12, but for the remaining 0.5 blocks of packet data less than one block, the next packet is input in the write block buffer 13A. Therefore, it waits for the data for one block to be prepared.

In such a case, when the packet data is read from the memory unit 12, the data of the three blocks stored in the memory unit 12 are read, but the packet data remaining in the write block buffer 13A is read. Are not stored in the memory unit 12, the packet cannot be reproduced from the three block data read out from the memory unit 12 as it is.
Therefore, in such a situation, by making a transition to the block write 2 state (step 204), the remaining data remaining in the write block buffer 13A can be stored in the memory unit even if block data for one block is not prepared. By writing to 12, all the packet data can be read from the memory unit 12.

  That is, in the input waiting state (step 201), when there is no packet input, there is no block stored in the memory unit 12, and there is data held in the write buffer unit 13, that is, “no input and In the case of “No memory storage and data retention”, the buffer control unit 11 writes the block in the incomplete state to the memory unit 12 without waiting for the packet data for one block to be prepared, so that the block write 2 state Transition to (Step 204). This transition is for avoiding a situation where the packet data accumulated in the memory unit 12 without input is exhausted and the last data remaining in the write block buffer 13A is not output.

  On the other hand, in the input waiting state (step 201), if there is a packet input and the packet cannot be stored, that is, if “input and memory cannot be stored”, the buffer control unit 11 discards the input packet. Transition to the state (step 206) and discard the packet without accumulating.

[Input packet discard status]
In the input packet discarding state (step 206), the buffer control unit 11 remains in the state until the input of the packet data is completed, and transitions to an input waiting state (step 201) according to the end of the input of the packet data. . Thereby, packet data can be discarded in units of packets. Therefore, it is possible to avoid the occurrence of discontinuous packet data in which only half of the packet data is discarded after the packet data has been written halfway, and it is possible to suppress the occurrence of defects at the time of packet reading caused by the discontinuous packet data. Become.

[Data storage status]
In the data storage state (step 202), the buffer control unit 11 stores the input packet data byte by byte at a position in the packet data area indicated by the storage position in the write block buffer 13A. The storage position is moved backward by 1 byte. When packet data is input not in units of 1 byte but in units of a predetermined number of bytes, storage and movement of the storage position are performed in units of the number of bytes.

  In the data storage state (step 202), when packet data follows and the packet data area of the writing block buffer 13A has a vacancy, that is, “packet continuation and block less than end”, the buffer control unit 11 Stays in the data storage state (step 202) and continues storing the packet data.

  On the other hand, in the data storage state (step 202), when the packet data follows and the packet data area of the writing block buffer 13A is full, that is, “packet continuation and block expiration”, the buffer control unit 11 Changes to the block writing 1 state (step 203), in which the block data held in the writing block buffer 13A is written to the memory unit 12.

  In the data storage state (step 202), when the packet data has been input to the write block buffer 13A up to the last byte, that is, at the “packet end”, the buffer control unit 11 sends a packet to the write block buffer 13A. Transition is made to the packet end position update state (step 205) in which the end position is stored.

[Data end position update status]
In the data end position update state (step 205), the buffer control unit 11 adds “1” to the value of the variable i.
Further, when the last byte of the packet data is stored in the write block buffer 13A in the previous data storage state (step 202), the buffer control unit 11 stores the number of bytes corresponding to the storage position, that is, the write block The number of bytes from the beginning of the packet data area of the buffer 13A to the end byte is stored in the writing block buffer 13A as the packet end position #i included in the block management information.

In the data end position update state (step 205), when the packet data area of the writing block buffer 13A has an empty space, that is, when “less than block end”, the buffer control unit 11 transitions to an input waiting state (step 201). .
In addition, in the data end position update state (step 205), when there is no more space in the packet data area of the write block buffer 13A, that is, when “block expiration” occurs, the buffer control unit 11 is held in the write block buffer 13A. The block is written to the memory unit 12, and the state transits to the block write 2 state (step 204).

[Block write 1 status]
In the block write 1 state (step 203), the buffer control unit 11 sets the value of the packet data continuation flag held as block management information in the write block buffer 13A to “1” and holds it in the write block buffer 13A. The written block data is written to a predetermined address in the memory unit 12.

  Further, the buffer control unit 11 initializes the writing block buffer 13A. In this initialization, the values of the P packet end positions are initialized to “0” and the variable i is initialized to “0”. Further, the storage position held in the write buffer unit 13 is initialized. Thereby, the storage position is set at the head position of the packet data area. Thereafter, the buffer control unit 11 transitions to a data storage state (step 202).

[Block write 2 status]
In the block write 2 state (step 204), the buffer control unit 11 initializes the value of the packet data continuation flag held as block management information in the write block buffer 13A to “0”, and writes the write block buffer 13A. The block data held in is stored in a predetermined address in the memory unit 12.

  Further, the buffer control unit 11 initializes the writing block buffer 13A. In this initialization, the values of the P packet end positions are initialized to “0” and the variable i is initialized to “0”. Further, the storage position of the write buffer unit 13 is initialized to “0”. As a result, the storage position is set at the head position of the packet data area. Thereafter, the buffer control unit 11 transitions to an input waiting state (step 201).

  In the writing operation described above, in the block writing 1 state (step 203) or the block writing 2 state (step 204), a process for writing the block data held in the memory unit 12 is performed. If the block is not accumulated in the block and the read buffer unit 14 does not hold the block, a process of storing the block in the read buffer unit 14 instead of writing in the memory unit 12 as described above may be performed. As a result, in the situation where the input packet is output without being stored, the storage in the memory unit 12 can be omitted, so that the power consumption in the memory unit 12 can be reduced.

[Block Write Operation of Third Embodiment]
Next, referring to FIG. 10, in the block write 1 state (step 203) and block write 2 state (step 204) of FIG. 9 described above, the block data in the write block buffer 13A is expressed in block data units. A block write operation for writing to a corresponding partition in the memory unit 12 will be described. FIG. 10 is a state transition diagram showing a block write operation according to the third embodiment.

In this block writing operation, the following control variables are used.
The write partition identifier is an identifier that is provided for each of the queues and identifies a partition in which the packet data corresponding to the queue is written.
The writing partition position information is information that is provided for each queue and indicates the writing start block position in the partition specified by the writing partition identifier of the queue.
The address is an address value in the memory unit 12 indicating a storage location corresponding to the position information in the writing section.
The variable B is the total number of blocks provided in the partition.
The variable K is the number of bytes indicating the size of the storage area in the block.

The connected partition identifier is an identifier that is provided for each of the partitions and identifies a partition connected to the partition.
The partition connection position is write position information in the partition for specifying the timing of outputting a partition connection signal for connecting a new partition to the partition during the writing process of packet data to the partition. is there.
The variable M is the total number of partitions provided in the memory unit 12 and corresponds to the maximum value of the writing partition identifier.

[Initialization status]
The packet buffer device 10 transitions to the initialization state (step 210) after the power is turned on and before the packet input is started, and executes the initialization process. The initialization is also performed when the packet buffer device 10 itself detects the occurrence of an abnormality in which normal operation cannot be maintained in the packet buffer device 10 or when there is a reset request from the outside.

  In the initialization state (step 210), the buffer control unit 11 transitions to an input waiting state (step 211) in which the packet and the queue input instruction information are waited for input when the initialization is completed.

[Waiting for input]
In the input waiting state (step 211), when a packet and queue input instruction information are input, the state shifts to the writing position information acquisition state (step 212). While there is no input, the buffer control unit 11 stays in an input waiting state (step 211) waiting for input of a packet without making a transition to another state.

[Writing position information acquisition status]
In the write position information acquisition state (step 212), the buffer control unit 11 outputs the value of the queue identifier included in the input queue input instruction information to the write position information holding unit 21, and accumulates the packet. The value of the writing partition identifier (partition unit) and the writing partition position information (block unit) of the queue to be received is received from the writing position information holding unit 21, and the state shifts to the address calculation state (step 213).

[Address calculation status]
In the address calculation state (step 213), the buffer control unit 11 calculates a memory address when packet data is written in units of words based on the values of the write partition identifier and the write partition position information. In the present embodiment, calculation is performed using an address = writing partition identifier value × B × K + writing partition position information value × K. After the calculation, the buffer control unit 11 transitions to a block data write state (step 214).

[Block data write status]
In the block data writing state (step 214), the buffer control unit 11 outputs the calculated address and data for one block in the writing block buffer 13A to the memory unit 12.
Thereby, in the memory unit 12, one block data is held in the memory cell at the address. After the output, the state transits to either the writing partition position update state (step 215) or the linked partition information acquisition state (step 216) according to the following conditions.

The transition condition to the writing partition position update state (step 215) is when the writing partition position is less than the end, that is, when writing to the partition being written can be continued. In the present embodiment, the write partition position information value <B-1 is the condition.
The position information in the writing section corresponds to the word number in the section where writing is performed. In the embodiment, since the number of the block at the head of the partition is 0 and the number of words in the partition is B, the number of the last word of the partition is B-1. Further, the fact that the position in the writing partition is less than that means that the position information value in the writing partition is before the last block of the partition (at the head of the partition), and the position information value in the writing partition <B−1. Is an expression representing the condition.

On the other hand, the transition condition to the connected partition information acquisition state (step 216) is when the position in the writing partition is expired, that is, when the position in the writing partition exceeds the maximum value. The writing partition position value ≧ B−1 is the condition. In addition, B-1 is the maximum value in the writing partition position value, and the writing partition position information value> B-1 is not normal.
When the position information value in the writing area at the position of the word at the head of the section is defined as 0, the position information value in the written image at the position of the last block in the section is B-1. If the number of words in a partition is B and the position information value in the writing partition indicates a word in the partition, the position information value in the writing partition may be greater than or equal to B or take a negative value. do not do.

[Writing section update status]
In the writing partition position update state (step 215), the buffer control unit 11 updates the writing partition position from the position where writing has been completed to the next position. In the present embodiment, the value of the position information in the writing section is incremented by one. Thereafter, the state transits to the writing position information update state (step 218).

  In addition, in the writing partition position update state (step 215), the buffer control unit 11 generates a partition connection signal when the value of the writing partition position information matches the value of the partition connection position. In response to the partition connection signal, one of the free partitions is removed from the list of free partitions by state transition processing related to partition connection, which will be described later, and the connected partition identifier held for the partition being written is used as the free space. Compartment concatenation is performed with a value indicating the section.

[Linked partition information acquisition status]
In the connected partition information acquisition state (step 216), the buffer control unit 11 outputs the value of the write partition identifier to the connected partition information holding unit 23, and from the connected partition information holding unit 23 to the partition being written. Enter the value of the connected partition identifier that identifies the connected partition. Thereafter, the state transits to the writing partition information update state (step 217). In this embodiment, when M is input as the connected partition identifier value, it means that there is no connected partition.

[Write partition information update status]
In the write partition information update state (step 217), the buffer control unit 11 updates the value of the write partition identifier to the value of the linked partition identifier. At the same time, the value of the position in the writing section is initialized. In the present embodiment, the value of the position in the writing section is updated to zero. That is, the writing position is changed to the head position of the connected section. Thereafter, the state transits to the writing position information update state (step 218).

[Write position information update status]
In the write position information update state (step 218), the buffer controller 11 sets the queue identifier value, the updated write partition identifier, and the write partition position information value included in the input queue input instruction information. Is output to the writing position information holding unit 21, and the value held in the writing position information holding unit 21 is updated. That is, the writing partition identifier and the writing partition position information are updated by writing the packet data to the memory unit 12, but when these packet data writing is completed, these values are retained. The state is reflected in the holding value in the unit 21 and the state shifts to an input waiting state (step 211).

[Read Operation of the Third Embodiment]
Next, referring to FIG. 11, in the packet buffer device 10 according to the present embodiment, in response to the input of the queue output instruction information, the packet data of the designated queue is sent from the corresponding section in the memory unit 12. A read operation when reading corresponding packet data from the read block buffer 14A after reading in block units and storing in the read block buffer 14A will be described. FIG. 11 is a state transition diagram showing a read operation according to the third embodiment. Of the read operation, details of the block read operation in the block read state (step 223) will be described later with reference to FIG.

In this reading operation, the following control variables are used. Data holding / non-holding is a variable indicating whether data is held in the reading block buffer 14A.
The variable i is a counter for counting the number of packet end bytes included in one block data.
The variable P is the maximum number of packets that can be included in one block data.
The packet end position is a variable indicating the position of the last byte of each packet data, and is represented by the number of bytes from the first byte of the packet data area in one block data.

The storage position is a variable (byte address) that specifies a position when packet data is stored byte by byte in the packet data area in the read block buffer 14A.
The acquisition position is a variable (byte address) that specifies a position when packet data is acquired byte by byte from the packet data area in the read block buffer 14A.
The packet data continuation flag is a variable indicating whether or not the packet data packet data area is used up.

[Initialization status]
The packet buffer device 10 transitions to an initialization state (step 220) after the power is turned on and before starting to output a packet, and executes an initialization process. The initialization is also performed when the packet buffer device 10 itself detects the occurrence of an abnormality in which normal operation cannot be maintained in the packet buffer device 10 or when there is a reset request from the outside.

  In the initialization state (step 220), the buffer control unit 11 initializes the read block buffer 14A. In this initialization process, the buffer control unit 11 initializes a value indicating whether data is retained without retaining data.

In this initialization, the buffer control unit 11 initializes the values of the M packet end positions to “0” and initializes the value of the variable i to “0”. Further, the buffer control unit 11 initializes the storage position of the read buffer unit 14. Thereby, the storage position is set at the head position of the packet data area.
In the initialization state (step 220), the buffer control unit 11 transitions to an input waiting state (step 221) where the input of queue output instruction information is waited when the initialization is completed.

[Waiting for input]
In the input waiting state (step 221), the buffer control unit 11 enters an input waiting state (step 221) for waiting for the input of the queue output instruction information without transitioning to another state until the queue output instruction information is input. stay.
Further, in the input waiting state (step 221), when the queue output instruction information is input, if the data holding presence / absence indicates that there is data holding, that is, “with input and with data holding”, the buffer control unit 11 transitions to the data acquisition state (step 222).

  On the other hand, when the queue output instruction information is input in the input waiting state (step 221), if the data holding presence / absence indicates no data holding, that is, “with input and no data holding”, the buffer control unit 11 transits to a block read state (step 223).

[Data acquisition status]
In the data acquisition state (step 222), the buffer control unit 11 acquires and outputs packet data byte by byte from the position indicated by the acquisition position from the read block buffer 14A, and also sets the acquisition position byte by byte. Move back. When packet data is not output in units of 1 byte but in units of a predetermined number of bytes, storage and storage position movement are performed in units of the number of bytes.

Further, in the data acquisition state (step 222), the buffer control unit 11 determines whether or not there is packet continuation / end and whether or not there is remaining data, that is, whether or not there is packet data before acquisition in the read block buffer 14A. .
At this time, the end of the packet indicates that the acquisition position has reached the position indicated by the packet end position #i stored in the read block buffer 14A, that is, that acquisition has been completed up to the last byte of the packet data being acquired. Judge as a condition. Note that the variable i is also used as a variable for specifying the packet end position for the acquisition target packet among the P packet end positions included in the read block buffer 14A.

Further, the packet continuation is determined on condition that the condition for ending the packet is not satisfied. At this time, if the value of the packet end position #i is “0” or i> P, it means that the last byte of the packet being acquired is not included in the read block buffer 14A but is included in the subsequent block. The determination is packet continuation.
On the other hand, the presence of remaining data means that the acquisition position has not reached the final byte position of the packet data area, and the condition of no remaining data is determined on the condition that the condition of remaining data is not satisfied.

  In the data acquisition state (step 222), when data has been acquired up to the last byte of the packet data, that is, at the time of “end of packet”, the buffer control unit 11 determines the data holding presence / absence value as follows: And then transitions to an input wait state (step 221).

In the above determination, when the acquisition position reaches the final byte position of the packet data area, the buffer control unit 11 first sets the data holding presence / absence value as not holding.
On the other hand, when the acquisition position has not reached the final byte position of the packet data area, the buffer control unit 11 adds “1” to the value of the variable i.

  At this time, after updating the variable i, the value of the packet end position #i stored in the read block buffer 14A is “0” or i> P, and the value of the packet data continuation flag is “1”. In this case, that is, when “(i> P) or packet end position [i] == 0) and packet data continuation flag == 1”, the buffer control unit 11 sets a value indicating whether or not data is retained as retained. .

On the other hand, when the value of the packet end position #i is “0” or i> P and the value of the packet data continuation flag is “0”, that is, “(i> P) or packet end position In the case of [i] == 0) and packet data continuation flag == 0, the buffer control unit 11 sets the data holding presence / absence value as no holding.
In addition, when the value of the packet end position #i is other than “0” and i ≦ P, the buffer control unit 11 sets the data holding / non-holding value as holding.

  Further, in the data acquisition state (step 222), when the packet is continuation and there is no remaining data, that is, “packet continuation and no remaining data”, the buffer control unit 11 reads the blocks accumulated in the memory unit 12 Transition to the block read state (step 223) stored in the read block buffer 14A.

  On the other hand, in the data acquisition state (step 222), when there is packet continuation and there is remaining data, that is, when "packet continuation and remaining data exists", the buffer control unit 11 remains in the data acquisition state (step 222). The packet data is acquired from the read block buffer 14A and output.

[Block read status]
In the block read state (step 223), the buffer control unit 11 reads one block data from a predetermined address of the memory unit 12, and stores the block data in the read block buffer 14A. Further, the buffer control unit 11 initializes the value of the acquisition position to a value indicating the start position of the packet data area in the read block buffer 14A, initializes the value of the data holding presence / absence with holding, , The value of the variable i is initialized to “1”.

[Block Read Operation of Third Embodiment]
Next, referring to FIG. 12, in the block read state of FIG. 11 (step 223) described above, the block read operation for reading the block data from the corresponding partition in the memory unit 12 and storing it in the read block buffer 14A Will be described. FIG. 12 is a state transition diagram showing a block read operation according to the third embodiment.

In the block read operation, the following control variables are used.
The read partition identifier is provided for each of the queues, and is an identifier for specifying a partition from which the packet data corresponding to the queue is read.
The read section position information is information that is provided for each of the queues and indicates the read start block position in the section specified by the read section identifier of the queue.
The address is an address value in the memory unit 12 indicating a storage location corresponding to the position information in the reading section.

The variable B is the total number of blocks provided in the partition.
The variable K is the number of bytes indicating the size of the storage area in the block.
The connected partition identifier is an identifier that is provided for each of the partitions and identifies a partition connected to the partition.

[Initialization status]
The packet buffer device 10 transitions to an initialization state (step 230) after the power is turned on and before starting to output a packet, and executes an initialization process. The initialization is also performed when the packet buffer device 10 itself detects the occurrence of an abnormality in which normal operation cannot be maintained in the packet buffer device 10 or when there is a reset request from the outside.
In the initialization state (step 230), the buffer control unit 11 transitions to an input waiting state (step 231) waiting for input of a packet and queue input instruction information when the initialization is completed.

[Waiting for input]
In the input waiting state (step 231), the buffer control unit 11 transitions to the reading position information acquisition state (step 232) when the queue output instruction information is input. While there is no input, the state remains in the input waiting state (step 231) waiting for input of the queue output instruction information without transitioning to another state.

[Reading position information acquisition status]
In the read position information acquisition state (step 232), the buffer control unit 11 outputs the queue identifier value included in the input queue output instruction information to the read position information holding unit 22, and stores the packet. The read section identifier and the value of the position information in the read section are received from the read position information holding unit 22 and the state shifts to the address calculation state (step 233).

[Address calculation status]
In the address calculation state (step 233), based on the values of the read section identifier and the read position information, the memory address for writing packet data in word units is calculated. In the present embodiment, the address is calculated as follows: address = read section identifier value × B × K + read position information value × K. After the calculation, the block data reading state (step 234) is entered.

[Block data read status]
In the block data reading state (step 234), the buffer control unit 11 outputs the calculated address to the memory unit 12, and stores the data for one block held in the memory cell in the memory unit 12 corresponding to the address. Read from the memory unit 12. After the reading, the state transitions to either the reading section position update state (step 235) or the connected section information acquisition state (step 236) according to the following conditions.

  The transition condition to the reading section position update state (step 235) is when the position within the reading section is less than the end, that is, when reading from the section being read can be continuously performed. In the embodiment, the position information value in the readout section <B-1 is the condition. Note that the position information in the reading section corresponds to the block number in the section where reading is performed. In this embodiment, the number of the block at the head of the partition is 0, and the number of blocks in the partition is B, so the block number at the end of the partition is B-1. Further, the reading section position is less than that means that the reading section position information value is in front of the last block of the section (at the head of the section), and the reading section position information value <B-1 is An expression representing the condition.

  On the other hand, the transition condition to the linked section information acquisition state (step 236) is when the position within the read section is expired, that is, when the position within the read section exceeds the maximum value. The intra-compartment position information value ≧ B−1 is the condition. It should be noted that B-1 is the maximum value of the position information value in the reading section, and the position information value in the reading section is not normally larger than B-1. When the position information value in the read section at the position of the first block in the section is defined as 0, the position information value in the read image at the position of the last block in the section is B-1. When the number of blocks in a partition is B and the position information value in the read partition indicates a block in the partition, the position information value in the read partition does not exceed B or takes a negative value.

  The method for preventing the occurrence of the abnormal value is to monitor the position information value in the reading section and perform processing such as device abnormality (reset or the like) when an abnormality occurs in the value. Further, when all the bits representing the position information value in the reading section are 1, the value of B is determined so that the position information value in the reading section = B−1 (it is possible by making B a power of 2). Therefore, the abnormal value will not occur. This is because no matter what value is taken as the position information value in the reading section, it falls within the normal range. Further, when the position information value in the reading section is B-1, it means that the reading position has reached the last block in the section.

[Reading position update status]
In the reading section position update state (step 235), the buffer control unit 11 updates the reading section position from the position where reading is completed to the next position. In the present embodiment, the value of the position in the readout section is incremented by one. Thereafter, the reading position information update state (step 237) is entered.

[Linked partition information acquisition status]
In the connected partition information acquisition state (step 236), the buffer control unit 11 outputs the value of the read partition identifier to the connected partition information holding unit 23, and connects to the partition being read from the connected partition information holding unit 23. The value of the connected partition identifier that identifies the partition that has been set is received, and a transition is made to the read partition information update state (step 238).
In the connected partition information acquisition state (step 236), the buffer control unit 11 generates a partition release signal. Triggered by the partition release signal, partition release is performed to return the partition to the list of free partitions by state transition processing related to partition release described later.

[Reading section information update status]
In the read section information update state (step 238), the buffer control unit 11 updates the value of the read section identifier to the value of the connected section identifier. At the same time, the value of the position in the reading section is initialized. In this embodiment, the value of the position in the readout section is updated to 0. That is, the reading position is changed to the head position of the connected section. Thereafter, the process proceeds to the read position information update state (step 237).

[Reading position information update status]
In the read position information update state (step 237), the buffer control unit 11 updates the read position information holding unit 22 with the value of the queue identifier included in the input queue output instruction information, and the update. The read section identifier and the value of the position information in the read section are output to the read position information holding unit 22, and the value held in the read position information holding unit 22 is updated. That is, reading the block data from the memory unit 12 updates the reading section identifier and the reading section position information. When the reading of the block data is completed, these values are read by the reading position information holding unit 22. The state is reflected in the stored value, and a transition is made to the input wait state (step 231).

[Partition Linking Operation of Third Embodiment]
Next, with reference to FIG. 13, the partition connection operation of the packet buffer device 10 according to the present embodiment will be described. FIG. 13 is a state transition diagram showing the partition connection operation. When the partition connection signal is generated in the writing partition position update state (step 215) of FIG. 10 described above, the buffer control unit 11 executes the partition connection operation based on the state transition of FIG.

[Initialization status]
The packet buffer device 10 transitions to an initialization state (step 240) after the power is turned on and before starting to output a packet, and executes an initialization process. The initialization is also performed when the packet buffer device 10 itself detects the occurrence of an abnormality in which normal operation cannot be maintained in the packet buffer device 10 or when there is a reset request from the outside.

  In the initialization state (step 240), the buffer control unit 11 performs initialization to add all partitions to the free partition list for the linked partition information holding unit 23 and the free partition information holding unit 24. In this embodiment, the empty partition information holding unit 24 outputs “0” as the value of the empty partition connection start identifier and M−1 as the value of the empty partition connection end identifier. The empty partition connection start identifier and the empty partition connection end identifier to be held are initialized.

Furthermore, the buffer control unit 11 outputs the partition identifier +1 as the value of the connected partition identifier for all partition identifiers to the connected partition information holding unit 23, so that each partition identifier held by the connected partition information holding unit 23 ( The value of the connected partition identifier [m] (m = 0 to M−1) for 0 to M−1) is initialized.
In the initialization state (step 240), the buffer control unit 11 transitions to a partition connection signal waiting state (step 241), which waits for a partition connection signal when initialization is completed.

[Block connection signal waiting state]
In the partition connection signal waiting state (step 241), the buffer control unit 11 transitions to the free partition information acquisition state (step 242) when there is a partition connection signal. There is no transition while the signal is not present. It should be noted that the value of the write partition identifier for specifying the partition that is the target of packet data writing of the buffer control unit 11 at the time when the partition connection signal is received is held.

[Free partition information acquisition status]
In the free partition information acquisition state (step 242), the buffer control unit 11 inputs the value of the free partition connection start identifier from the free partition information holding unit 24. After the input, the state transitions to either the unconnected state (step 243) or the empty partition acquisition state (step 244) according to the following conditions.

The transition condition to the unconnected state (step 243) is when there is no empty partition, and in this embodiment, the value of the acquired empty partition connection start identifier is M.
On the other hand, the transition condition to the empty partition acquisition state (step 244) is a case where there is an empty partition. In this embodiment, the acquired empty partition connection start identifier value is a valid partition identifier range (from 0 This is the case of an integer up to M-1.

[Free partition acquisition status]
In the free partition acquisition state (step 244), the buffer control unit 11 sends the free partition connection start identifier acquired from the free partition information storage unit 24 in the free partition information acquisition state (step 242) to the connected partition information storage unit 23. Is output as a partition identifier, and a connected partition identifier value for specifying a partition connected to the partition identifier is input from the connected partition information holding unit 23. Further, the empty partition connection start identifier value is updated to the input connected partition identifier value for the empty partition information holding unit 24.

  When the input connected partition identifier value is a connected partition identifier value indicating that there is no connected partition, the empty partition connection end identifier is further transmitted to the empty partition information holding unit 24. Is updated to the value of the connected partition identifier, which means that there is no connected partition. In the present embodiment, the value of the connected partition identifier that means that there is no connected partition is M. Thereafter, the state transits to a linked update state (step 245). As a result, one partition is removed from the list of free partitions.

[Consolidated update status]
In the concatenated update state (step 245), the buffer control unit 11 instructs the concatenated partition information holding unit 23 to store the value of the write partition identifier held when the partition concatenation signal is received and the free partition information acquisition state (step In 242), the value of the empty partition connection start identifier acquired from the empty partition information holding unit 24 is output, so that the value of the connected partition identifier of the writing partition is rewritten to the value of the empty partition connection start identifier.
As a result, one partition removed from the list of empty partitions is connected to the partition whose writing is about to expire (the position in the writing partition is scheduled to expire). Thereafter, the state transits to a partition connection signal waiting state (step 241).

[Unconnected state]
In the unconnected state (step 243), the buffer control unit 11 does not have a partition connected with the value of the write partition identifier held when the partition connection signal is given to the connected partition information holding unit 23. A connected partition identifier value indicating that the write partition is connected, and the connected partition identifier value of the writing partition is rewritten to a connected partition identifier value indicating that there is no connected partition. Transition to (Step 241). In the present embodiment, the value of the connected partition identifier that means that there is no connected partition is M.

[Partition release operation of the third embodiment]
Next, the partition release operation of the packet buffer device 10 according to the present embodiment will be described with reference to FIG. FIG. 14 is a state transition diagram showing the partition release operation. When the partition release signal is generated in the connected partition information acquisition state (step 236) of FIG. 12 described above, the buffer control unit 11 executes the partition release operation based on the state transition of FIG.

[Initialization status]
The packet buffer device 10 transitions to the initialization state (step 250) after the power is turned on and before starting the output of the packet, and executes the initialization process. The initialization is also performed when the packet buffer device 10 itself detects the occurrence of an abnormality in which normal operation cannot be maintained in the packet buffer device 10 or when there is a reset request from the outside.
When the initialization is completed in the initialization state (step 250), the buffer control unit 11 transitions to a partition release signal wait state (step 251) waiting for the partition release signal.

[Partition release signal waiting state]
When there is a partition release signal in the partition release signal waiting state (step 251), the state transits to the free partition information acquisition state (step 252). There is no transition while the signal is not present. It should be noted that the value of the read partition identifier for specifying the partition that is the target of packet data reading by the buffer control unit 11 at the time when the partition release signal is received is held.

[Free partition information acquisition status]
In the free partition information acquisition state (step 252), the buffer control unit 11 receives the value of the free partition connection end identifier from the free partition information holding unit 24, and transitions to the free partition return state (step 253).

[Free space return status]
In the empty partition return state (step 253), the buffer controller 11 instructs the connected partition information holding unit 23 that there is no connected partition and the value of the read partition identifier held when the partition release signal is received. The value of the connected partition identifier meaning that the connected partition identifier value of the partition specified by the read partition identifier value is changed to the value of the connected partition identifier meaning that there is no connected partition. rewrite. In the present embodiment, the value of the connected partition identifier that means that there is no connected partition is M. Furthermore, the value of the empty partition connection end identifier input in the empty partition information acquisition state (step 252) and the value of the read partition identifier held when the partition release signal is received are given to the connected partition information holding unit 23. Output and specified by the empty partition connection end identifier

  The value of the connected partition identifier of the partition is rewritten to the value of the read partition identifier. However, when the value of the empty partition connection end identifier is a value of a connected partition identifier that means that there is no connected partition, the rewriting is not performed. As a result, the section whose reading has been completed is connected to the last section in the list of free sections. After the above, a transition is made to the empty partition update state (step 254).

[Free partition update status]
In the free partition update state (step 254), the buffer control unit 11 sets the value of the free partition connection end identifier to the free partition information holding unit 24 and the value of the read partition identifier held when the partition release signal is received. Update to However, if the value of the empty partition connection end identifier input in the empty partition information acquisition state (step 252) is the value of a connected partition identifier that means that there is no connected partition, in addition to the above, For the free partition information holding unit 24, the value of the free partition connection start identifier is updated to the value of the read partition identifier held when the partition release signal is received. Thereafter, the state transits to a partition release signal waiting state (step 251).

[Effect of the third embodiment]
As described above, in this embodiment, in the first embodiment, a partition is configured by a plurality of blocks, and the packet data of each input packet is represented by a block in the partition corresponding to the designated queue. It is to be accumulated.

  More specifically, the buffer control unit 11 writes the packet data to a partition corresponding to the queue specified by the queue input instruction information among the partitions configured by a plurality of blocks. The packet data is accumulated in the queue, and the packet data is read from the queue by reading the packet data from the partition corresponding to the queue designated by the queue output instruction information in the memory unit 12. When the writing of the packet data to the partition is completed, the packet data from the partition is continuously written after the empty partition is connected to the partition as a connected partition. When the data reading has expired, the partition is released as an empty partition and It is obtained so as to continue the reading of the packet data from the connection section which is connected to the partition.

  As a result, similarly to the first embodiment, fixed-length block management information including packet boundary information generated for each input packet is concatenated with the packet data and stored in the queue of the memory unit 12. Therefore, according to the packet buffer device 10 according to the present embodiment, in order to store a conventional fixed-length packet job (job information), it is necessary to provide a job memory composed of SRAM separately from the queue. There is no. Therefore, even when the number of packets to be accumulated is increased, it is possible to suppress an increase in an extra circuit scale accompanying an increase in the data memory for accumulating packets.

  In addition to this, when packet accumulation is concentrated in a specific queue, the partitions are connected before the queue overflows, and for queues with little packet accumulation, the partitions are connected to the queue. In addition, the partition is released according to the decrease in the accumulated amount due to the output of the packet. Therefore, even when the required capacity varies for each queue, or when the accumulated amount fluctuates over time, the capacity is appropriately allocated to each queue. Compared with the device, the required memory capacity can be reduced.

  This effect will be described using an example used in the description of the prior art. In the present embodiment, in the process of accumulating packets in the queue, additional allocation is performed when there is less free space in the memory amount already allocated to the queue. For example, if the memory is divided into partitions having a capacity of 64 KBytes, and a new partition is added to the queue when the space allocated to the queue becomes 2 KBytes, the partition allocated to each queue Since the maximum value of the free capacity generated in 2 is 2 Kbytes which is a condition for assigning a new partition + 64 Kbytes which is the capacity of one new partition, it is 66 Kbytes.

  Therefore, the situation where the free capacity is generated in all the queues is the situation where the memory usage rate is the lowest. Therefore, the value obtained by adding the total free capacity value 66 KB x 8 to 12.5 Mbytes required for accumulation. 13 Mbytes is a necessary memory amount in the present embodiment. As shown in this example, the memory amount of 100 MBytes is conventionally required, but 13 MBytes is sufficient. Therefore, the present embodiment has an effect that the memory amount can be reduced by 87%.

In addition, the present embodiment manages the area of the memory that holds the packet data accumulated in each queue as a virtual FIFO buffer in which partitions are connected. Complex buffer control is not required.
Further, according to the present embodiment, addresses for accessing the memory can be made continuous in one partition, and burst access to the memory is possible as in the packet buffer device to which the conventional technique is applied. As a result, when used in an application where the output from one queue is continuously performed, reading from the memory can be performed at a high speed, so that the packet extraction from the queue is fast.

  Specifically, the addresses at the time of memory access can be made continuous by dividing the memory unit 12 into a plurality of address ranges that do not overlap with each other, and setting these as respective partitions. In other words, in order to determine the address range for each partition, if the next address of the address when accessing a certain partition is within the range of the address determined for the partition, the next address is accessed. This is because the memory area in the partition has been accessed.

  Further, in this embodiment, since a partition to be written next is connected on the condition that the write position in the partition has reached a predetermined position, the next partition is written before the partition being written becomes full. Therefore, even when writing is performed across partitions, writing is not interrupted and packet accumulation in the queue is fast.

Note that the size range of the memory partition that can realize high-speed packet reading and efficient memory use varies depending on the burst length of packets input to and output from the buffer and the maximum and average packet lengths.
When the size of each partition is m, the maximum stored data amount (= burst length) when input packets are continuously stored is Lb, and when the queue stores the data amount Lb, Lb / m A partition is used.

  Therefore, if the value of m is increased so that the value of Lb / m is decreased, the number of necessary partitions is reduced, so that the circuit scale for connecting the partitions can be reduced. On the other hand, among the partitions allocated to the queue, data Since the average amount (m / 2) of empty areas that do not store is increased, the memory accumulation rate Rs = 1−m / (2 × Lb) decreases.

  In addition, if the value of m is reduced, the number of partition connection processing and release processing increases, so that an increase in processing amount may cause an increase in power consumption and a decrease in packet input / output speed. Further, since the partition changes during data writing / reading, when a memory such as a DDR-SDRAM is used, access to the memory is interrupted and the use efficiency of the access bandwidth of the memory is lowered. . In particular, when the value of m is equal to or less than the average packet length Lp, the partition switching probability Pc = Lp / m in the middle of the packet is 1 or more, so that the partition switching occurs during the reading or writing of each packet. The problem gets worse.

Therefore, a practical range of m is a range represented by Lp / Pc ≦ m ≦ 2 × Rs × Lb when Lb, Lp, Rs, and Pc are given, and m is a large value within the range. The circuit scale and power consumption are reduced by taking the circuit. For example, if Bb = 1 Mbyte, Lp = 750 bytes, Rs = 0.05, and Pc = 0.1, 7.5 Kbytes ≦ m ≦ 100 Kbytes, and the partition is preferably 100 Kbytes.
Depending on how Lb, Lp, Rs, and Pc are given, m in the practical range may not exist. In this case, it is determined that the present invention is not effective and the conventional configuration should be adopted. it can.

  In addition, the average packet length and burst length may be different for each queue. In such a case, when obtaining an appropriate partition size range for each queue, a value that satisfies all these ranges is obtained. What is necessary is just to employ | adopt the maximum value among the ranges as the magnitude | size of a division. In this way, m can be determined within an appropriate range for all the queues.

  Further, when the above-mentioned m does not exist because the average packet length and burst length vary greatly depending on the queue, the memory area is divided into M1 areas with a partition size m1 and M2 areas with a partition size m2. The partitioned areas A2,... Are partitioned into Mk partitioned areas Ak with a partition size mk, and each queue is assigned to any one of the sections A1 to Ak having a partition size in an appropriate range. When accumulating packets in each queue, the packets are accumulated using a section in a section to which the queue belongs. The processing for connecting and releasing partitions within each section is as described above.

  Note that the amount of memory allocated to each category is less than or equal to the total burst length of the queues belonging to that category, and the statistical multiplexing effect (the total queue length is the maximum length because each queue is unlikely to have the maximum length). The effect may be set to a value that takes into account an effect that is smaller than the total value.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

  DESCRIPTION OF SYMBOLS 10 ... Packet buffer apparatus, 11 ... Buffer control part, 12 ... Memory part, 13 ... Write buffer part, 13A ... Write block buffer, 14 ... Read buffer part, 14A ... Read block buffer, 21 ... Write position information holding , 22 ... Reading position information holding unit, 23 ... Linked partition information holding unit, 24 ... Free partition information holding unit.

Claims (6)

A memory unit having a plurality of blocks each having a fixed-length storage area, and writing and reading data for each of these blocks;
A write block buffer for holding at least data for the block;
A read block buffer for holding at least data for the block;
The packet data of the input variable length packet is sequentially stored in the write block buffer, and block management information including packet boundary information indicating the end position of each packet data stored in the write block buffer is stored in the write block buffer. When a predetermined amount of data is stored in the write block buffer, the data is written to the memory unit, and the data is read from the memory unit according to the input output instruction. A packet control unit that reads and stores the packet data in the read block buffer, and reads and outputs each packet data included in the data based on the packet boundary information of the block management information included in the data. Packet buffer device. The packet buffer device according to claim 1, wherein
When storing the packet data in the write block buffer, the packet control unit stores the packet data in the write block buffer if the write block buffer has insufficient free space to store all of the packet data. After the written data is written to the memory unit, the remaining packet data is stored from the head of the write block buffer. The packet buffer device according to claim 1, wherein
The block is divided into a plurality of words each having a fixed length of a plurality of bytes.
The packet control unit
When storing the block management information in the writing block buffer, storing the block management information from the first word of the word in the writing block buffer,
When writing the packet data to the write block buffer, a word for storage is selected in order from the next word after the first word storing the last byte of the block management information, and the packet data is stored in the selected word When storing each byte of the packet data in order from the first byte of the word, and storing a predetermined packet end pattern from the byte next to the byte storing the tail byte of the packet data,
When storing the block management information in the write block buffer, the block management information including a boundary determination bit string indicating the presence / absence of the last byte of the packet data in each word is stored instead of the packet boundary information. A packet buffer device. The packet buffer device according to claim 3, wherein
The packet control unit
When reading the packet data from the block, the block management information is first obtained from the head word of the block, and based on the boundary determination bit string of the block management information, the presence or absence of the last byte of the packet data in the block If the tail byte does not exist, the memory unit is requested to read the next block. If the tail byte does not exist, the packet is sequentially received from the word next to the head word. A packet buffer device for reading data. In the packet buffer device according to any one of claims 1 to 4,
The buffer control unit
The packet data is stored in the queue by writing the packet data to a partition corresponding to the queue specified by the queue input instruction information among the partitions configured by a plurality of blocks. The packet data is taken out from the queue by reading the packet data from the partition corresponding to the queue specified by the queue output instruction information in the memory unit,
When writing of the packet data to the partition has expired, after linking an empty partition to the partition as a connected partition, the writing of the packet data to the empty partition is continued, and the packet data from the partition is When reading is completed, the packet is released as an empty partition, and the packet data is continuously read from the connected partition connected to the partition. A packet buffer control method used in a packet buffer device for storing an input packet in a queue (FIFO memory) and extracting and outputting the packet from the queue according to an output instruction,
A memory unit having a plurality of blocks each having a fixed-length storage area, and writing and reading data for each of these blocks;
A write block buffer for holding at least data for the block;
A read block buffer for holding at least the data for the block;
The packet controller
The packet data of the input variable length packet is sequentially stored in the write block buffer, and block management information including packet boundary information indicating the end position of each packet data stored in the write block buffer is stored in the write block buffer. Storing in the embedded block buffer;
When a predetermined amount of data is stored in the write block buffer, the data is written to the memory unit, and the data is read from the memory unit in response to the input output instruction, and sent to the read block buffer. A packet buffer control method comprising: storing and reading each packet data included in the data based on the packet boundary information of the block management information included in the data and outputting the packet data.

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