JPH10229119A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the withstand voltage characteristics of a transistor capacitance constituting a circuit from being deteriorated, by a method wherein, when a groove is formed, a pad oxide film is removed by etching longer than the distance in a specified range from the end parts of an oxidation preventive film to retreat the pad oxide film. SOLUTION: A pad oxide film 2 is formed on the surface of a silicon substrate 1, and a silicon nitride film 12 and a photoresist 13 are deposited on the film 2. Each one part of the phtoresist 13 and the films 12 and 2 is removed and a shallow groove having a prescribed angle is formed in the substrate 1. Then, the film 2 is removed by etching in a thickness of 5 to 40nm or thereabouts to retreat the film 2 and thereafter, the surface of the substrate 1 is thermally oixdized and a thermal oxide film 5 is formed on the part of the groove. For relaxing the volume expansion originating stress of the film 5 in this oxidation of the groove, a buried insulating film 6 is buried in the groove. Then, the film 6 is etched back and the films 12 and 2 are removed, whereby a groove buried structure is completed. After that, a semiconductor device is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a highly reliable groove separation structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art A LOCOS (Local Oxidation Ratio) is used as a structure for electrically insulating and separating adjacent elements on a semiconductor substrate.
n of Silicon) structure. In this structure, a thick oxide film is formed by selectively oxidizing the substrate surface, and is used in many semiconductor devices. However, this LO
The COS structure is not suitable for an insulating isolation structure of a highly integrated semiconductor device requiring processing dimensional accuracy like a deep submicron device. This is because an oxidizing species diffuses and invades from the edge of the film just below the antioxidant film typified by the silicon nitride film used for selective oxidation, resulting in a thick oxide film region called a bird's beak. . For this reason, a shallow groove is formed on the substrate surface as disclosed in, for example, Japanese Patent Application Laid-Open No. 63-143835, instead of the LOCOS structure as an insulating isolation structure of a semiconductor device requiring high integration. A groove separation structure of a selective oxidation method for selectively oxidizing to form a thermal oxide film has begun to be adopted.

The trench isolation structure has an advantage that an element isolation oxide film having a small plane dimension can be formed as compared with the LOCOS structure. Therefore, it is suitable for manufacturing a deep submicron device which requires a processing dimensional accuracy of 0.5 μm or less. It is.

[0004]

For example, when a silicon thermal oxide film is formed by oxidizing the surface of a silicon substrate which is a semiconductor substrate, a large mechanical stress is generated at an interface between the formed thermal oxide film and the silicon substrate. I do. This is because when a part of the silicon substrate is oxidized and changes into a thermal oxide film, the volume expansion is approximately doubled. When the mechanical stress is increased, crystal defects such as dislocations and stacking faults are likely to occur in the silicon substrate, thereby deteriorating the reliability of the semiconductor device.
In addition, it has been clarified that the shape of an oxide film that grows under the influence of stress in the oxidation reaction itself changes (the growth of the oxide film becomes slow due to compressive stress).

FIG. 1 is a schematic view of a manufacturing process of a trench structure in a conventional selective oxidation method. As shown in FIG. 1, according to the conventional method, an antioxidant film 3 is deposited on a surface of a silicon substrate 1 via a pad oxide film (silicon oxide film) 2, and then the antioxidant film 3 at a desired position is removed. Forming a groove by partially removing the film 2 and the silicon substrate 1 (FIGS. 1a and 1b);
The groove portion is oxidized to form an element isolation thermal oxide film 5 (FIG. 1c).

In this structure, in particular, the shape of the substrate near the upper end of the groove may be oxidized to an acutely sharp shape (substrate acute portion 4) as shown in FIG.

After the buried insulating film 6 is formed, as shown in FIG. 1D, an electronic circuit such as a transistor and a capacitor is formed in the element forming region covered with the oxide protective film 3. 4 remains on the substrate surface, for example, A.Br
yant et al., “Tecnical Digestof IEDM´94, pp.671-67
4), electric field concentration occurs in this part during circuit operation, which may degrade the withstand voltage characteristics of transistors and capacitors constituting the circuit. It is empirically known that such a withstand voltage deterioration phenomenon similarly occurs even when the angle of the substrate near the upper end of the groove is 90 degrees or more and when the radius of curvature on the substrate side near the upper end of the groove is about 3 nm or less. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a trench isolation structure, which has high reliability without deteriorating withstand voltage characteristics of a transistor capacitor constituting a circuit, and a method of manufacturing the same.

[0008]

The object of the present invention is to reduce the stress generated near the upper end of an element isolation groove on the surface of a semiconductor substrate,
This is achieved by preventing sharpening of the substrate shape. In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes the following steps. (1) a step of forming a pad oxide film on the circuit formation surface of the semiconductor substrate (2) a step of forming an antioxidant film on the pad oxide film (3) the antioxidation at a desired position on the circuit formation surface of the semiconductor substrate Step of partially removing the film and pad oxide film and forming a groove of a predetermined depth on the surface of the semiconductor substrate. (4) Etching and removing the pad oxide film from the end of the remaining antioxidant film by 5 nm or more. (5) The groove portion formed in the semiconductor substrate is formed in an oxidizing atmosphere: H
2 / O 2 gas ratio 0.5 or less, oxidation amount: a step of oxidizing in a range until the space of the recessed pad oxide film (gap between the substrate surface and the antioxidant film) is filled (7) The oxidized groove (8) removing the buried insulating film formed on the antioxidant film; (9) removing the oxidized film formed on the circuit forming surface of the semiconductor substrate. Step of removing (10) Step of removing the pad oxide film formed on the circuit forming surface of the semiconductor substrate. In order to achieve the above object, a semiconductor device according to the present invention comprises: In the semiconductor device in which the element isolation oxide film structure formed in the above is a trench isolation structure, the oxidation amount at the center side surface of the trench of the trench isolation structure is 5 to 70 nm.
And the radius of curvature of the trench at the upper end of the semiconductor substrate is in the range of 3 to 35 nm.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of a trench isolation structure for a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 3 is a sectional structural view of the semiconductor device according to the present embodiment, and FIG. 3 is a flowchart showing an outline of the manufacturing process. Less than,
The manufacturing process will be described with reference to FIG. 2 according to the flowchart of FIG.

(1) The surface of a silicon substrate 1 is thermally oxidized to form a pad oxide film 2 having a thickness of 5 to several tens nm.
(101), (102)｝. (2) A silicon nitride film 12 having a thickness of 10
Deposit about 300 nm. This silicon nitride film 12 is used as an antioxidant film when forming the element isolation thermal oxide film 5 (FIG. 3 (103)). (3) A photoresist 13 is formed on the silicon nitride film 12 (FIG. 3 (104)). (4) After removing the photoresist 13 at a desired position by using a normal exposure method, the silicon nitride film 12, the pad oxide film 2 and a part of the silicon substrate 1 are removed by etching to remove the surface of the silicon substrate 1. A shallow groove whose side wall has a predetermined angle with respect to the silicon substrate 1 (for example, the angle of the portion A in the figure is 90 to 110 degrees) is formed {FIGS. 3 (105) to (107)}. (5) After removing the photoresist 13, the pad oxide film 2
Is removed by etching about 5 to 40 nm {FIGS. 3 (108) to (109)}. (6) Thereafter, the surface of the silicon substrate 1 is thermally oxidized in an oxidizing atmosphere of, for example, 900 to 1100 ° C. in an H ₂ / O ₂ gas ratio of 1 ppm or less, and a thermal oxide film 5 having a thickness of about 30 nm is formed in the groove portion. (110)｝. (7) In this groove oxidation, it is necessary to stop as far as the inside of the groove is not completely filled, in order to reduce the stress caused by the volume expansion of the oxide film as much as possible. As a result, an insulating film such as a silicon oxide film is deposited and buried in the space remaining in the groove by, for example, a chemical vapor deposition (CVD) method, a sputtering method or the like (hereinafter, buried insulating film 6). Further, since the silicon oxide film or the like manufactured by the chemical vapor deposition method, the sputtering method or the like is generally a rough film, after the buried insulating film 6 is deposited, an annealing or oxidizing atmosphere at about 1000 ° C. is performed for the purpose of densification. The silicon substrate 1 may be oxidized inside.
(111)｝. (8) The buried insulating film 6 is etched back by using a chemical mechanical polishing (CMP) method or a dry etching method. In this case, the silicon nitride film 12 used as an oxidation prevention film
Serves as an etching stopper and has a function of preventing the silicon substrate 1 under the silicon nitride film 12 from being etched {FIG. 3 (112)}. (9) Then, the trench filling structure is completed by removing the silicon nitride film 12 and the pad oxide film 2 {FIG.
3)｝. Thereafter, the semiconductor device is completed through, for example, the formation of a gate oxide film and a gate electrode, the introduction of impurities, the formation of a wiring and an interlayer insulating film, the formation of a multilayer wiring structure, the formation of a surface protection film, and the like, which are necessary for manufacturing the transistor structure. .

Next, the operation and effect of the first embodiment will be described with reference to FIGS.
This will be described with reference to FIG. The first embodiment differs from the prior art in that the pad oxide film 2 in the manufacturing step (5) is recessed. FIG. 4 shows the manufacturing process (5) described in the first embodiment.
5 shows the results of analyzing the change in the radius of curvature of the substrate side near the upper end of the groove by changing the amount of retreat of the pad oxide film. Are shown respectively. From FIG.
It can be seen that the radius of curvature at the upper end of the substrate increases as the amount of recession of the pad oxide film 2 increases from zero. 5n retraction
m, the radius of curvature is about 25 nm, and the amount of retreat is 20
If nm, the radius of curvature increases to about 35 nm. However, even if the retreat amount is further increased, the radius of curvature hardly increases. This is considered to be due to the following reasons. During the groove oxidation, the oxide film grows while expanding the volume between the silicon nitride film 12 and the silicon substrate 1 about twice (see FIGS. 5A and 5B). When the retreat amount of the pad oxide film 2 is zero (FIG. 5A), the end of the silicon nitride film 12 is lifted by the volume expansion, and as a result, it warps concavely. As a result of the reaction force of the warpage deformation of the silicon nitride film 12, a compressive stress is generated in the oxide film (including a part of the pad oxide film 2) under the silicon nitride film 12 and the silicon substrate 1. As described in the subject, when a compressive stress is generated in the oxide film, the diffusion of the oxidized species, that is, the progress of the oxidation reaction is suppressed, so that the oxidation rate is significantly reduced at the upper end portion of the groove. On the other hand, on the trench side wall, there is no restriction in the growth direction of the oxide film (side normal direction), and there is no inhibitor of the volume expansion of the grown oxide film. Therefore, oxidation is relatively suppressed on the side wall surface. Proceed without progress. Therefore, in the vicinity of the upper end of the groove of the silicon substrate 1, the shape of the substrate becomes sharper as the oxidation progresses as shown by the broken line in FIG. However, when the pad oxide film 2 is retracted (see FIG. 5B), a part of the groove end of the silicon substrate 1 is exposed. In the exposed portion, since the grown oxide film and the upper silicon nitride film 12 do not come into contact with each other in the initial stage of the oxidation, the generation of the compressive stress due to the warp deformation of the silicon nitride film 12 described with reference to FIG. Since there is almost no oxidation, oxidation proceeds without suppression. As a result, the upper end of the groove is rounded, and the radius of curvature is increased. If the oxidation is further continued in the manufacturing step (6), the oxide film grown on the exposed portion comes into contact with the silicon nitride film, and thereafter the compressive stress is rapidly generated as described above. Care must be taken because the formed curvature is reduced again.

In the first embodiment, the radius of curvature of the groove isolation structure near the upper end on the substrate side can be made sufficiently larger than 3 nm. Since it is possible to prevent an acute angle portion from remaining near the upper end portion of the groove of the silicon substrate, it is possible to prevent an increase in leakage current or a decrease in breakdown voltage characteristics of the transistor due to electric field concentration near the end portion of the gate electrode film.
There is an effect that the electrical reliability of the transistor can be improved.

Next, a manufacturing process of a trench isolation structure of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. The manufacturing method (flowchart) of the groove filling structure of the semiconductor device of the second embodiment shown in FIG. 6 is a modification of the manufacturing process (in the text) (6) of the first embodiment. Since the shape and the like are not largely changed as compared with the first embodiment, a cross-sectional view of the semiconductor device in this embodiment will be described with reference to FIG. Hereinafter, the manufacturing process of this embodiment will be described with reference to the flowchart of FIG.

(1) Thermal oxidation of the surface of silicon substrate 1 to form pad oxide film 2 having a thickness of 5 to several tens nm {FIG.
(201), (202)｝. (2) A silicon nitride film 12 having a thickness of 10
Deposit about 300 nm. This silicon nitride film 12 is used as an anti-oxidation film when forming the element isolation thermal oxide film 5 (FIG. 6 (203)). (3) A photoresist 13 is formed on the silicon nitride film 12 (FIG. 6 (204)). (4) After removing the photoresist 13 at a desired position by using a normal exposure method, the silicon nitride film 12, the pad oxide film 2 and a part of the silicon substrate 1 are removed by etching to remove the surface of the silicon substrate 1. A shallow groove whose side wall has a predetermined angle with respect to the silicon substrate 1 (for example, the angle of the portion A in the figure is 90 to 110 degrees) is formed {FIGS. 6 (205) to (207)}. (5) After removing the photoresist 13, the pad oxide film 2
Is removed by etching about 10 to 40 nm (FIGS. 6 (208) to (209)). (6) The groove portion formed in the silicon substrate 1 is thermally oxidized in an H ₂ / O ₂ gas mixed oxidizing atmosphere (gas flow ratio r: 0 <r ≦ 0.5) to form a device isolation thermal oxide film having a thickness of about 30 nm. 5 (FIG. 6 (210)). (7) In this groove oxidation, it is necessary to stop as far as the inside of the groove is not completely filled, in order to reduce the stress caused by the volume expansion of the oxide film as much as possible. As a result, an insulating film such as a silicon oxide film is deposited and buried in the space remaining in the groove by, for example, a chemical vapor deposition (CVD) method, a sputtering method or the like (hereinafter, buried insulating film 6). Further, since the silicon oxide film or the like manufactured by the chemical vapor deposition method, the sputtering method or the like is generally a rough film, after the buried insulating film 6 is deposited, an annealing or oxidizing atmosphere at about 1000 ° C. is performed for the purpose of densification. The silicon substrate 1 may be oxidized in it.
(211)｝. (8) The buried insulating film 6 is etched back by using a chemical mechanical polishing (CMP) method or a dry etching method. In this case, the silicon nitride film 12 used as an oxidation prevention film
Serves as an etching stopper and has a function of preventing the silicon substrate 1 under the silicon nitride film 12 from being etched {FIG. 6 (212)}. (9) Then, the trench filling structure is completed by removing the silicon nitride film 12 and the pad oxide film 2 {FIG.
3)｝. Thereafter, a semiconductor device is completed through, for example, formation of a gate oxide film and a gate electrode, introduction of impurities, formation of a wiring, an interlayer insulating film, and the like, formation of a multilayer wiring structure, formation of a surface protection film, and the like necessary for manufacturing a transistor structure. .

Next, the operation and effect of this embodiment will be described with reference to FIG. The H ₂ / O ₂ gas ratio r in the oxidizing atmosphere is 0 ≦ r <2.
Can change up to. Since the reaction explosively proceeds when r reaches 2, considering safety, it is substantially r
= 1.8 is the upper limit. Generally, assuming that the oxidation temperature is constant when the gas ratio is within the above range, the oxidation rate increases as this ratio increases, and the oxidation rate decreases as the ratio decreases. Therefore, the effect of this oxidation rate on the shape of the upper end of the groove of the semiconductor substrate was analyzed. FIG. 7 shows the result. The horizontal axis indicates the H ₂ / O ₂ gas ratio, and the vertical axis indicates the radius of curvature of the upper end of the semiconductor substrate. FIG. 7 shows that the larger the flow rate ratio of hydrogen (H2) in the oxidizing atmosphere, the more rapidly the formed radius of curvature decreases. When the gas ratio reaches 0.5, the radius of curvature decreases to about 3 nm. As the gas ratio is increased further, the radius of curvature decreases, albeit slightly.

The cause can be explained as follows. As described above, the oxidation generates strain (stress) near the interface between silicon and the silicon oxide film. On the other hand, since the silicon oxide film exhibits a remarkable viscous behavior at a high temperature (950 ° C. or higher), the stress generated with time is relaxed at a high temperature. Therefore, assuming that the oxide film thickness is constant, the value of the generated strain (stress) is constant, but the oxidation rate is high (H
_The larger the ( ₂ / O ₂ gas ratio), the shorter the time during which the generated stress is relieved, resulting in a higher residual stress. When the oxidation rate is low (the H ₂ / O ₂ gas ratio is small), the viscous effect of the silicon oxide film acts, and the stress is relatively relaxed when compared under the condition of a constant oxide film thickness. As the oxidation-induced stress increases, oxidation in the vicinity of the stress is suppressed. Therefore, the vicinity of the upper end of the groove of the silicon substrate is a place where the stress is concentrated by the growth of the oxide film from the upper surface and the side surface. If the residual stress is increased, the oxidation in the vicinity is suppressed, and as a result, the tip becomes sharp. It becomes a shape. From the above, H ₂
By reducing the / O ₂ gas ratio, oxidation proceeds at a lower stress at the upper end of the groove of the semiconductor substrate, and as a result, a curvature near the upper end of the silicon substrate 1 is achieved. .

For the above reasons, according to the second embodiment,
Since the radius of curvature near the upper end of the trench isolation structure on the substrate side can be made sufficiently larger than 3 nm, an acute angle portion near the upper end of the trench of the silicon substrate remains when the trench isolation structure is formed in the transistor manufacturing process. Therefore, it is possible to prevent an increase in leakage current or a decrease in breakdown voltage characteristics of the transistor due to the concentration of an electric field near the end of the gate electrode film, thereby improving the electrical reliability of the transistor. Next, a manufacturing process of a trench filling structure of a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. The manufacturing method (flowchart) of the trench burying structure of the semiconductor device of the third embodiment shown in FIG. 8 is a modification of the manufacturing process (6) of the first embodiment (in the text). Since the shape and the like are not largely changed as compared with the first embodiment, a cross-sectional view of the semiconductor device according to the present embodiment will be described with reference to FIG. explain.

(1) The surface of the silicon substrate 1 is thermally oxidized to form a pad oxide film 2 having a thickness of 5 to several tens nm.
(301), (302)}. (2) A silicon nitride film 12 having a thickness of 10
Deposit about 300 nm. This silicon nitride film 12 is used as an antioxidant film when forming the element isolation thermal oxide film 5 (FIG. 8 (303)). (3) A photoresist 13 is formed on the silicon nitride film 12 (FIG. 8 (304)). (4) After removing the photoresist 13 at a desired position by using a normal exposure method, the silicon nitride film 12, the pad oxide film 2 and a part of the silicon substrate 1 are removed by etching to remove the surface of the silicon substrate 1. 8 (305)-(307)}, a shallow groove whose side wall has a predetermined angle with respect to the silicon substrate 1 (for example, the angle of the portion A in the figure is 90-110 degrees). (5) After removing the photoresist 13, the pad oxide film 2
Is removed by etching about 5 to 40 nm {FIGS. 8 (308) to (309)}. (6) The groove portion formed in the silicon substrate 1 is thermally oxidized in an H ₂ / O ₂ gas mixed oxidizing atmosphere (gas flow ratio r: 0 <r ≦ 0.5), and the groove portion formed in the semiconductor substrate 1 is Oxidation is performed until the space of the recessed pad oxide film is filled. ｛Figure 8
(310)｝. (7) In this groove oxidation, it is necessary to stop as far as the inside of the groove is not completely filled, in order to minimize the stress caused by the volume expansion of the oxide film as much as possible. As a result, an insulating film such as a silicon oxide film is deposited and buried in the space remaining in the groove by, for example, a chemical vapor deposition (CVD) method, a sputtering method or the like (hereinafter, buried insulating film 6). Further, since the silicon oxide film or the like manufactured by the chemical vapor deposition method, the sputtering method or the like is generally a rough film, after the buried insulating film 6 is deposited, an annealing or oxidizing atmosphere at about 1000 ° C. is performed for the purpose of densification. The silicon substrate 1 may be oxidized inside.
(311)｝. (8) The buried insulating film 6 is etched back by using a chemical mechanical polishing (CMP) method or a dry etching method. In this case, the silicon nitride film 12 used as an oxidation prevention film
Serves as an etching stopper and has a function of preventing the silicon substrate 1 under the silicon nitride film 12 from being etched {FIG. 8 (312)}. (9) Then, the trench filling structure is completed by removing the silicon nitride film 12 and the pad oxide film 2 {FIG.
3)｝. Thereafter, a semiconductor device is completed through, for example, formation of a gate oxide film and a gate electrode, introduction of impurities, formation of a wiring, an interlayer insulating film, and the like, formation of a multilayer wiring structure, formation of a surface protection film, and the like necessary for manufacturing a transistor structure. .

The effect of this embodiment is that, as described in the first embodiment (see FIG. 5), after the space of the recessed pad oxide film is filled, the silicon nitride film 12 is warped. However, the compressive stress is generated in the pad oxide film 2 and the silicon substrate 1 under the silicon nitride film 12 by the force of the bending of the film, so that the oxidation suppresses the stress, and as a result, the silicon substrate in the vicinity of the upper end of the groove is formed. The shape becomes sharp. As described above, by reducing the amount of oxidation until the space of the pad oxide film is filled, no compressive stress is generated due to the warpage deformation, so that the oxidation of the upper end portion of the silicon substrate 1 proceeds smoothly. As a result, a curvature near the upper end of the silicon substrate 1 is achieved.

For the above reasons, according to the third embodiment,
Since the radius of curvature near the upper end of the trench isolation structure on the substrate side can be made sufficiently larger than 3 nm, an acute angle portion near the upper end of the trench of the silicon substrate remains when the trench isolation structure is formed in the transistor manufacturing process. Therefore, it is possible to prevent an increase in leakage current or a decrease in breakdown voltage characteristics of the transistor due to the concentration of an electric field near the end of the gate electrode film, thereby improving the electrical reliability of the transistor. Next, a trench embedding structure of a semiconductor device according to a fourth embodiment of the present invention and a manufacturing process thereof will be described with reference to FIGS. FIG. 2 is a sectional structural view of the semiconductor device according to the present embodiment, and FIG. 9 is a flowchart showing an outline of the manufacturing process. Hereinafter, the manufacturing process will be described with reference to FIG. 2 along the flowchart of FIG.

(1) The surface of the silicon substrate 1 is thermally oxidized to form a pad oxide film 2 having a thickness of 5 to 50 nm {FIG.
(401), (402)}. (2) A silicon nitride film 12 having a thickness of 10
Deposit about 300 nm. This silicon nitride film 12 is used as an oxidation prevention film when forming the element isolation thermal oxide film 5 (FIG. 9 (403)). (3) A photoresist 13 is formed on the silicon nitride film 12 (FIG. 9 (404)). (4) After removing the photoresist 13 at a desired position by using a normal exposure method, the silicon nitride film 12, the pad oxide film 2 and a part of the silicon substrate 1 are removed by etching to remove the surface of the silicon substrate 1. 9 (405)-(407)}, a shallow groove whose sidewall has a predetermined angle with respect to the silicon substrate 1 (for example, the angle of the portion A in the figure is 90-110 degrees). (5) After removing the photoresist 13, the pad oxide film 2
Is etched away by about 10 to 40 nm and receded (FIGS. 9 (408) to (409)). (6) Thereafter, the surface of the silicon substrate 1 is thermally oxidized at, for example, 900 to 1100 ° C. in an oxidizing atmosphere H ₂ / O ₂ gas ratio of 1 ppm or less to form a thermal oxide film 5 (FIG. 9 (410)). (7) In this groove oxidation, it is necessary to stop as far as the inside of the groove is not completely filled, in order to minimize the stress caused by the volume expansion of the oxide film as much as possible. As a result, an insulating film such as a silicon oxide film is deposited and buried in the space remaining in the groove by, for example, a chemical vapor deposition (CVD) method, a sputtering method or the like (hereinafter, buried insulating film 6). Further, since the silicon oxide film or the like manufactured by the chemical vapor deposition method, the sputtering method or the like is generally a rough film, after the buried insulating film 6 is deposited, an annealing or oxidizing atmosphere at about 1000 ° C. is performed for the purpose of densification. The silicon substrate 1 may be oxidized inside.
(411)｝. (8) The buried insulating film 6 is etched back by using a chemical mechanical polishing (CMP) method or a dry etching method. In this case, the silicon nitride film 12 used as an oxidation prevention film
Serves as an etching stopper and has a function of preventing the silicon substrate 1 under the silicon nitride film 12 from being etched {FIG. 9 (412)}. (9) Then, the trench filling structure is completed by removing the silicon nitride film 12 and the pad oxide film 2 {FIG. 9 (41)
3)｝. Thereafter, the semiconductor device is completed through, for example, the formation of a gate oxide film and a gate electrode, the introduction of impurities, the formation of a wiring and an interlayer insulating film, the formation of a multilayer wiring structure, the formation of a surface protection film, and the like, which are necessary for manufacturing the transistor structure. . explain. In the trench isolation structure of the semiconductor device according to the present embodiment, the amount of oxidation at the center side surface of the trench is in the range of 5 to 70 nm, and the radius of curvature of the trench at the upper end of the semiconductor substrate is in the range of 3 to 35 nm. Things.

Next, the operation and effect of this embodiment will be described with reference to FIG.

FIG. 10 is a simulation result of the relationship between the oxidation amount of the element isolation thermal oxide film and the radius of curvature on the side surface of the central portion of the groove in accordance with the present embodiment. In FIG. 10, a indicates the thickness of the pad oxide film. . According to FIG. 10, the radius of curvature R at the upper end of the silicon substrate increases with the oxidation amount of the groove side wall.
Further, it can be seen that the maximum value is reached and the value is saturated to a substantially constant value. The maximum value becomes larger as the thickness of the pad oxide film a becomes larger, but becomes substantially constant (about 35 nm) at 10 nm or more.
It has become. The reason for the maximum radius of curvature is
Although the radius of curvature increases with the oxidation of the groove, the space of the recessed pad oxide film gradually fills up, and then, as shown in FIG. And compressive stress on the oxide film)
However, it is considered that oxidation was suppressed by this compressive stress.

From experiments, it has been found by experiments that the radius of curvature R does not adversely affect transistor characteristics if the radius of curvature is about 3 nm or more. Therefore, the oxidation amount of the groove side wall that can secure this radius of curvature is 5 nm or more from FIG. 10, and the radius of curvature does not increase even if it is oxidized to 30 nm or more. Therefore, in order to maximize the radius of curvature, the pad oxide film thickness should be 10 nm or more and the side wall oxidation amount should be 30.
It is preferably at least nm.

In this embodiment, by adopting this structure and the manufacturing method, it is possible to increase the radius of curvature near the upper end of the groove to about 35 nm, which is caused by the electric field concentration near the end of the gate electrode film. This has the effect of preventing an increase in leakage current or a decrease in breakdown voltage characteristics of the transistor, and improving the electrical reliability of the transistor.

[0027]

According to the present invention, in a semiconductor device having a trench isolation structure, it is possible to provide a semiconductor device and a manufacturing method which do not deteriorate the breakdown voltage characteristics of transistors and capacitors constituting a circuit.

[Brief description of the drawings]

FIG. 1 is a schematic view of a manufacturing process of a trench isolation structure in a conventional selective oxidation method.

FIG. 2 is a schematic view of a manufacturing process of the groove separation structure of the first embodiment according to the present invention.

FIG. 3 is a flowchart showing a manufacturing process of the first embodiment according to the present application.

FIG. 4 is a diagram illustrating the operation and effect of the first embodiment according to the present application.

FIG. 5 is a diagram illustrating the operation and effect of the first embodiment according to the present application.

FIG. 6 is a flowchart showing a manufacturing process of a second embodiment according to the present application.

FIG. 7 is a diagram illustrating the operation and effect of the second embodiment according to the present application.

FIG. 8 is a flowchart showing a manufacturing process of a third embodiment according to the present application.

FIG. 9 is a flowchart showing a manufacturing process of a fourth embodiment according to the present application.

FIG. 10 is a diagram illustrating the operation and effect of the fourth embodiment according to the present application.

[Explanation of symbols]

1 ... silicon substrate, 2 ... pat oxide film, 3 ...
An oxidation prevention film, 4 ... a substrate acute angle portion, 5 ... a device isolation thermal oxide film, 6 ... a buried insulating film, 7 ... a gate oxide film, 8 ... a gate electrode film, 9 ...・ Insulating film, 10 ・
··· Wiring, 11: interlayer insulating film, 12: silicon nitride film, 13: photoresist.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Norio Suzuki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Yasushi Matsuda Yasushi Josuihoncho, Kodaira-shi, Tokyo 20-1 Chome, Semiconductor Division, Hitachi, Ltd.

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device including the following steps: (1) A pad oxide film is formed to a thickness of 5 nm on a circuit formation surface of a semiconductor substrate.
As described above, a step of preferably forming a layer having a thickness of 10 nm or more. (2) A step of forming an antioxidant film on the pad oxide film. (3) A groove having a predetermined depth is formed at a desired position on a circuit forming surface of the semiconductor substrate. Step (4) The pad oxide film has a thickness of 5 nm or more, preferably 10 nm or more.
(5) Step of oxidizing a groove portion formed in the semiconductor substrate (6) Step of burying a buried insulating film in the oxidized groove (7) Step of forming on the antioxidant film Removing the buried insulating film; (8) removing the antioxidant film formed on the circuit forming surface of the semiconductor substrate; and (9) removing the pad oxidation formed on the circuit forming surface of the semiconductor substrate. Step of removing film 2. A method of manufacturing a semiconductor device including the following steps: (1) A pad oxide film having a thickness of 5 nm is formed on a circuit forming surface of a semiconductor substrate.
As described above, a step of preferably forming a layer having a thickness of 10 nm or more. (2) A step of forming an antioxidant film on the pad oxide film. (3) A groove having a predetermined depth is formed at a desired position on a circuit forming surface of the semiconductor substrate. Step (4) The pad oxide film has a thickness of 5 nm or more, preferably 10 nm or more.
(5) a step of oxidizing a groove portion formed in the semiconductor substrate in an oxidizing atmosphere having an H ₂ / O ₂ gas ratio of 0.5 or less (6) a buried insulating film in the oxidized groove Embedding step (7) Step of removing the embedded insulating film formed on the antioxidant film (8) Step of removing the antioxidant film formed on the circuit formation surface of the semiconductor substrate (9) Removing the pad oxide film formed on the circuit forming surface of the semiconductor substrate 3. A method for manufacturing a semiconductor device including the following steps: (1) A pad oxide film having a thickness of 5 nm is formed on a circuit forming surface of a semiconductor substrate.
As described above, a step of preferably forming a layer having a thickness of 10 nm or more. (2) A step of forming an antioxidant film on the pad oxide film. (3) A groove having a predetermined depth is formed at a desired position on a circuit forming surface of the semiconductor substrate. Step (4) The pad oxide film has a thickness of 5 nm or more, preferably 10 nm or more.
(5) Step of oxidizing the groove portion formed in the semiconductor substrate until the space of the recessed pad oxide film fills (6) Step of burying a buried insulating film in the oxidized groove (7) A) removing the buried insulating film formed on the antioxidant film; (8) removing the antioxidant film formed on the circuit forming surface of the semiconductor substrate. Removing the pad oxide film formed on the circuit forming surface 4. A method of manufacturing a semiconductor device including the following steps: (1) A pad oxide film having a thickness of 5 nm is formed on a circuit forming surface of a semiconductor substrate.
As described above, a step of preferably forming a layer having a thickness of 10 nm or more. (2) A step of forming an antioxidant film on the pad oxide film. (3) A groove having a predetermined depth is formed at a desired position on a circuit forming surface of the semiconductor substrate. Step (4) The pad oxide film has a thickness of 5 nm or more, preferably 10 nm or more.
(5) Step of oxidizing the groove formed in the semiconductor substrate under the following conditions Oxidizing atmosphere: H2 / O2 gas ratio of 0.5 or less Oxidation amount: Until the space of the recessed pad oxide film is filled (6) a step of burying a buried insulating film in the oxidized groove; (7) a step of removing the buried insulating film formed on the antioxidant film; and (8) a step of removing the buried insulating film on the circuit formation surface of the semiconductor substrate. Removing the formed antioxidant film (9) removing the pad oxide film formed on the circuit forming surface of the semiconductor substrate 5. A semiconductor device in which an element isolation oxide film structure formed on a circuit formation surface of a semiconductor substrate has a trench isolation structure, wherein the amount of oxidation at the center side surface of the trench of the trench isolation structure is 5%.
(Preferably 30) to 70 nm, and a radius of curvature of an upper end of the semiconductor substrate in the groove is in a range of 3 to 35 nm.