JP3547279B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a highly reliable trench isolation structure and a method for manufacturing the same.
[0002]
[Prior art]
As a structure for electrically insulating and separating adjacent elements on a semiconductor substrate, there is a LOCOS (Local Oxidation of Silicon) structure. In this structure, a thick oxide film is formed by selectively oxidizing the substrate surface, and is employed in many semiconductor devices. However, this LOCOS structure is not suitable for an insulation isolation structure of a highly integrated semiconductor device requiring processing dimensional accuracy like a deep submicron device. This is because the oxidizing species diffuses and invades from the edge of the film just below the antioxidant film typified by the silicon nitride film used for selective oxidation, resulting in the formation of a thick oxide film region called a bird's beak. . For this reason, a shallow groove is formed on the substrate surface as disclosed in, for example, JP-A-63-143835, instead of a LOCOS structure as an insulating isolation structure of a semiconductor device required to be highly integrated. A groove separation structure of a selective oxidation method for selectively oxidizing to form a thermal oxide film has begun to be adopted.
[0003]
This groove isolation structure has an advantage that an element isolation oxide film having a small planar dimension can be formed as compared with the LOCOS structure, and is therefore suitable for manufacturing a deep submicron device requiring a processing dimensional accuracy of 0.5 μm or less.
[0004]
[Problems to be solved by the invention]
For example, when a silicon thermal oxide film is formed by oxidizing the surface of a silicon substrate which is a semiconductor substrate, a large mechanical stress is generated at an interface between the formed thermal oxide film and the silicon substrate. This is because when a part of the silicon substrate is oxidized and changes into a thermal oxide film, the volume expansion is approximately doubled. When the mechanical stress is increased, crystal defects such as dislocations and stacking faults are likely to occur in the silicon substrate, thereby deteriorating the reliability of the semiconductor device. In addition, it has been clarified that the shape of an oxide film that grows under the influence of stress in the oxidation reaction itself changes (the growth of the oxide film is slowed down by compressive stress).
[0005]
FIG. 1 is a schematic diagram of a manufacturing process of a groove structure in a conventional selective oxidation method. As shown in FIG. 1, in the conventional method, an antioxidant film 3 is deposited on a surface of a silicon substrate 1 via a pad oxide film (silicon oxide film) 2 and then the antioxidant film 3 at a desired position is removed. The film 2 and the silicon substrate 1 are partially removed to form a groove (FIGS. 1A and 1B), and the groove is oxidized to form an element isolation thermal oxide film 5 (FIG. 1C).
[0006]
In this structure, in particular, the substrate shape near the upper end of the groove may be oxidized to an acutely sharp shape (substrate acute angle portion 4) as shown in FIG.
[0007]
After the buried insulating film 6 is formed, as shown in FIG. 1D, an electronic circuit such as a transistor and a capacitor is formed in the element forming region covered with the oxide protective film 3. When remaining on the surface, for example, A.I. As disclosed by Bryant et al. In "Technical Digestof IEDM'94, pp. 671-674", electric field concentration occurs in this portion during circuit operation, deteriorating the withstand voltage characteristics of transistors and capacitors constituting the circuit. There are cases. It has been empirically known that such a breakdown voltage degradation phenomenon similarly occurs when the radius of curvature of the substrate near the top of the groove is about 3 nm or less even when the angle of the substrate near the top of the groove is 90 degrees or more.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a trench isolation structure, which has high reliability without deteriorating withstand voltage characteristics of a transistor capacitor constituting a circuit, and a method of manufacturing the same.
[0008]
[Means for Solving the Problems]
The above object is achieved by reducing the stress generated near the upper end of the element isolation groove on the surface of the semiconductor substrate and preventing the substrate shape from being sharpened.
In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes the following steps.
(1) Step of forming a pad oxide film on a circuit formation surface of a semiconductor substrate
(2) Step of forming antioxidant film on pad oxide film
(3) a step of partially removing the antioxidant film and the pad oxide film at desired positions on the circuit formation surface of the semiconductor substrate, and forming a groove of a predetermined depth on the surface of the semiconductor substrate;
(4) A step of etching and removing the pad oxide film from the end of the remaining antioxidant film by 5 nm or more to retract it.
(5) The space of the pad oxide film (gap between the substrate surface and the antioxidant film) in which the groove portion formed in the semiconductor substrate is oxidized atmosphere: H2 / O2 gas ratio is 0.5 or less, and the amount of oxidation is recessed is filled. Oxidation process up to
(7) A step of burying a buried insulating film inside the oxidized groove
(8) removing the buried insulating film formed on the antioxidant film
(9) removing the antioxidant film formed on the circuit formation surface of the semiconductor substrate;
(10) removing the pad oxide film formed on the circuit formation surface of the semiconductor substrate
According to another aspect of the present invention, there is provided a semiconductor device according to the present invention, wherein the element isolation oxide film structure formed on the circuit formation surface of the semiconductor substrate has a trench isolation structure. The amount of oxidation on the side surface of the portion was in the range of 5 to 70 nm, and the radius of curvature of the groove at the upper end of the semiconductor substrate was in the range of 3 to 35 nm.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, examples of embodiments of the present invention will be described with reference to the drawings.
[0010]
【Example】
A manufacturing process of a trench isolation structure of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.
FIG. 2 is a sectional structural view of the semiconductor device according to the present embodiment, and FIG. 3 is a flowchart showing an outline of the manufacturing process. Hereinafter, the manufacturing process will be described with reference to FIG. 2 along the flowchart of FIG.
[0011]
(1) The surface of the silicon substrate 1 is thermally oxidized to form the pad oxide film 2 having a thickness of 5 to several tens nm {FIGS. 3 (101) and (102)}.
(2) A silicon nitride film 12 is deposited on the pad oxide film 2 to a thickness of about 10 to 300 nm. This silicon nitride film 12 is used as an oxidation prevention film when forming the element isolation thermal oxide film 5 (FIG. 3 (103)).
(3) A photoresist 13 is formed on the silicon nitride film 12 (FIG. 3 (104)).
(4) After removing the photoresist 13 at a desired position by using a normal exposure method, the silicon nitride film 12, the pad oxide film 2 and a part of the silicon substrate 1 are removed by etching, and the surface of the silicon substrate 1 is removed. 3 (105)-(107)}, a shallow groove whose sidewall has a predetermined angle with respect to the silicon substrate 1 (for example, the angle of the portion A in the figure is 90-110 degrees).
(5) After removing the photoresist 13, the pad oxide film 2 is etched away by about 5 to 40 nm and receded (FIGS. 3 (108) to (109)).
(6) Thereafter, for example, an oxidizing atmosphere H at 900 to 1100 ° C. ₂ / O ₂ The surface of the silicon substrate 1 is thermally oxidized at a gas ratio of 1 ppm or less, and a thermal oxide film 5 having a thickness of about 30 nm is formed in the groove (FIG. 3 (110)).
(7) In this groove oxidation, it is necessary to stop as far as the inside of the groove is not completely filled, in order to reduce the stress caused by the volume expansion of the oxide film as much as possible. As a result, an insulating film such as a silicon oxide film is deposited and buried in the space remaining in the groove by, for example, a chemical vapor deposition (CVD) method or a sputtering method (hereinafter, buried insulating film 6). In addition, since silicon oxide films and the like manufactured by the chemical vapor deposition method, the sputtering method, and the like are generally rough films, after deposition of the buried insulating film 6, annealing or oxidizing atmosphere at about 1000 ° C. is performed for the purpose of densification. The silicon substrate 1 may be oxidized therein (FIG. 3 (111)).
(8) The embedded insulating film 6 is etched back using a chemical mechanical polishing (CMP) method or a dry etching method. In this case, the silicon nitride film 12 used as the antioxidant film serves as an etching stopper, and has a function of preventing the silicon substrate 1 under the silicon nitride film 12 from being etched {FIG. 3 (112)}.
(9) Then, the trench filling structure is completed by removing the silicon nitride film 12 and the pad oxide film 2 (FIG. 3 (113)). Thereafter, a semiconductor device is completed through, for example, formation of a gate oxide film and a gate electrode, introduction of impurities, formation of a wiring, an interlayer insulating film, etc., formation of a multilayer wiring structure, formation of a surface protection film, and the like necessary for manufacturing a transistor structure. .
[0012]
Next, the operation and effect of the first embodiment will be described with reference to FIGS.
The first embodiment differs from the prior art in that the pad oxide film 2 in the manufacturing step (5) is recessed. FIG. 4 shows the result of analyzing the change in the radius of curvature of the substrate near the upper end of the groove by changing the amount of retreat of the pad oxide film in the manufacturing process (5) described in the first embodiment. The amount of retreat of the film 2 and the vertical axis indicate the radius of curvature of the upper end of the groove of the silicon substrate 1. From FIG. 4, it can be seen that the radius of curvature at the upper end of the substrate increases as the amount of retreat of the pad oxide film 2 increases from zero. When the retreat amount is 5 nm, the radius of curvature is about 25 nm, and when the retreat amount is 20 nm, the radius of curvature increases to about 35 nm. However, even if the retreat amount is further increased, the curvature radius hardly increases. This is considered for the following reasons. During the groove oxidation, the oxide film grows while expanding the volume between the silicon nitride film 12 and the silicon substrate 1 about twice (see FIGS. 5A and 5B). When the retreat amount of the pad oxide film 2 is zero (FIG. 5A), the end of the silicon nitride film 12 is lifted by the volume expansion, and as a result, it warps concavely. As a result of the reaction force of the warpage deformation of the silicon nitride film 12, a compressive stress is generated in the oxide film (including a part of the pad oxide film 2) under the silicon nitride film 12 and the silicon substrate 1. As described in the subject, when a compressive stress is generated in the oxide film, the diffusion of the oxidized species, that is, the progress of the oxidation reaction is suppressed, so that the oxidation rate is significantly reduced at the upper end portion of the groove. On the other hand, on the trench side wall, there is no restriction in the growth direction of the oxide film (side normal direction), and there is no inhibitor of the volume expansion of the grown oxide film. Therefore, oxidation is relatively suppressed on the side wall surface. Proceed without progress. Therefore, in the vicinity of the upper end of the groove of the silicon substrate 1, the shape of the substrate becomes sharper as the oxidation progresses as shown by the broken line in FIG. However, when the pad oxide film 2 is retracted (see FIG. 5B), a part of the groove end of the silicon substrate 1 is exposed. In the exposed portion, the oxide film grown and the upper silicon nitride film 12 do not come into contact with each other at the initial stage of the oxidation, so that the generation of the compressive stress due to the warp deformation of the silicon nitride film 12 as described with reference to FIG. Since there is almost no oxidation, oxidation proceeds without suppression. As a result, the upper end of the groove is rounded, and the radius of curvature is increased. If the oxidation is further continued in the manufacturing step (6), the oxide film grown on the exposed portion comes into contact with the silicon nitride film, and thereafter the compressive stress is rapidly generated as described above. It is necessary to be careful that the formed curvature decreases again.
[0013]
In the first embodiment, since the radius of curvature near the upper end of the trench isolation structure near the substrate can be made sufficiently larger than 3 nm, in forming the trench isolation structure in the MOS transistor manufacturing process, Since an acute angle portion can be prevented from remaining near the upper end portion of the groove, an increase in leak current or a decrease in breakdown voltage characteristics of the transistor due to electric field concentration near the end portion of the gate electrode film can be prevented, and the electrical reliability of the transistor can be improved. There is an effect that can be.
[0014]
Next, a manufacturing process of a trench isolation structure of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. The manufacturing method (flowchart) of the trench filling structure of the semiconductor device of the second embodiment shown in FIG. 6 is a modification of the manufacturing process (in the text) (6) of the first embodiment. Since the shape and the like do not largely change as compared with the first embodiment, a cross-sectional view of the semiconductor device in this embodiment will be described with reference to FIG. Hereinafter, the manufacturing process of this embodiment will be described with reference to the flowchart of FIG.
[0015]
(1) The surface of the silicon substrate 1 is thermally oxidized to form a pad oxide film 2 having a thickness of 5 to several tens nm {FIGS. 6 (201) and (202)}.
(2) A silicon nitride film 12 is deposited on the pad oxide film 2 to a thickness of about 10 to 300 nm. This silicon nitride film 12 is used as an antioxidant film when forming the element isolation thermal oxide film 5 (FIG. 6 (203)).
(3) A photoresist 13 is formed on the silicon nitride film 12 (FIG. 6 (204)).
(4) After removing the photoresist 13 at a desired position by using a normal exposure method, the silicon nitride film 12, the pad oxide film 2 and a part of the silicon substrate 1 are removed by etching, and the surface of the silicon substrate 1 is removed. 6 (205)-(207), a shallow groove whose side wall has a predetermined angle with respect to the silicon substrate 1 (for example, the angle of the portion A in the figure is 90-110 degrees).
(5) After removing the photoresist 13, the pad oxide film 2 is etched away by about 10 to 40 nm and receded (FIGS. 6 (208) to (209)).
(6) The groove formed in the silicon substrate 1 is H ₂ / O ₂ Thermal oxidation is performed in a gas-mixed oxidizing atmosphere (gas flow ratio r: 0 <r ≦ 0.5) to form an element isolation thermal oxide film 5 having a thickness of about 30 nm {FIG. 6 (210)}.
(7) In this groove oxidation, it is necessary to stop as far as the inside of the groove is not completely filled, in order to reduce the stress caused by the volume expansion of the oxide film as much as possible. As a result, an insulating film such as a silicon oxide film is deposited and buried in the space remaining in the groove by, for example, a chemical vapor deposition (CVD) method or a sputtering method (hereinafter, buried insulating film 6). In addition, since silicon oxide films and the like manufactured by the chemical vapor deposition method, the sputtering method, and the like are generally rough films, after deposition of the buried insulating film 6, annealing or oxidizing atmosphere at about 1000 ° C. is performed for the purpose of densification. The silicon substrate 1 may be oxidized therein (FIG. 6 (211)).
(8) The embedded insulating film 6 is etched back using a chemical mechanical polishing (CMP) method or a dry etching method. In this case, the silicon nitride film 12 used as the antioxidant film serves as an etching stopper, and has a function of preventing the silicon substrate 1 under the silicon nitride film 12 from being etched {FIG. 6 (212)}.
(9) Then, the trench filling structure is completed by removing the silicon nitride film 12 and the pad oxide film 2 (FIG. 6 (213)). Thereafter, a semiconductor device is completed through, for example, formation of a gate oxide film and a gate electrode, introduction of impurities, formation of a wiring, an interlayer insulating film, etc., formation of a multilayer wiring structure, formation of a surface protection film, and the like necessary for manufacturing a transistor structure. .
[0016]
Next, the operation and effect of this embodiment will be described with reference to FIG.
H in oxidizing atmosphere ₂ / O ₂ The gas ratio r can vary from 0 ≦ r <2. When r reaches 2, the reaction proceeds explosively, so in consideration of safety, the upper limit is substantially r = 1.8. Generally, assuming that the oxidation temperature is constant when the gas ratio is within the above range, the oxidation rate increases as the ratio increases, and the oxidation rate decreases as the ratio decreases. Therefore, the effect of this oxidation rate on the shape of the upper end of the groove of the semiconductor substrate was analyzed. FIG. 7 shows the result. H on the horizontal axis ₂ / O ₂ The gas ratio and the vertical axis indicate the radius of curvature of the upper end of the semiconductor substrate. FIG. 7 shows that the larger the flow rate ratio of hydrogen (H2) in the oxidizing atmosphere, the sharper the radius of curvature formed decreases. When the gas ratio reaches 0.5, the radius of curvature decreases to about 3 nm. As the gas ratio is increased further, the radius of curvature decreases slightly but slightly.
[0017]
The cause can be explained as follows.
Oxidation generates strain (stress) near the interface between silicon and the silicon oxide film, as described above. On the other hand, since the silicon oxide film exhibits a remarkable viscous behavior at a high temperature (950 ° C. or higher), the stress generated with time is relaxed at a high temperature. Therefore, assuming that the oxide film thickness is constant, the value of the generated strain (stress) is constant, but the oxidation rate is high (H ₂ / O ₂ The larger the gas ratio), the shorter the time during which the generated stress is relieved, resulting in a higher residual stress. Slow oxidation rate (H ₂ / O ₂ When the gas ratio is small), the viscous effect of the silicon oxide film acts, and the stress is relatively relaxed when compared under the condition of a constant oxide film thickness. The higher the oxidation-induced stress, the more the oxidation in the vicinity is suppressed. Therefore, the vicinity of the upper end of the groove of the silicon substrate is a place where the stress is concentrated by the growth of the oxide film from the upper surface and the side surface. If the residual stress is increased, the oxidation in the vicinity is suppressed, and as a result, the tip becomes sharp. It takes shape. From the above, H ₂ / O ₂ By reducing the gas ratio, oxidation proceeds at a lower stress at the upper end of the groove of the semiconductor substrate, and as a result, a curvature near the upper end of the silicon substrate 1 is achieved.
[0018]
For the above reasons, according to the second embodiment, the radius of curvature near the upper end of the trench isolation structure on the substrate side can be made sufficiently larger than 3 nm, and therefore, when forming the trench isolation structure in the transistor manufacturing process. Since it is possible to prevent an acute angle portion near the upper end portion of the groove of the silicon substrate from remaining, it is possible to prevent an increase in leakage current or a decrease in withstand voltage characteristics of the transistor due to electric field concentration near the end portion of the gate electrode film, and to improve the electrical reliability of the transistor. There is an effect that the property can be improved. Next, a manufacturing process of a trench filling structure of a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. The manufacturing method (flowchart) of the semiconductor device according to the third embodiment shown in FIG. 8 in which the trench is filled is a modification of the manufacturing process (6) of the first embodiment (in the text). Since the shape and the like are not largely changed as compared with the first embodiment, a cross-sectional view of the semiconductor device according to the present embodiment will be described with reference to FIG. explain.
[0019]
(1) The surface of the silicon substrate 1 is thermally oxidized to form the pad oxide film 2 having a thickness of 5 to several tens nm {FIGS. 8 (301) and (302)}.
(2) A silicon nitride film 12 is deposited on the pad oxide film 2 to a thickness of about 10 to 300 nm. This silicon nitride film 12 is used as an antioxidant film when forming the element isolation thermal oxide film 5 (FIG. 8 (303)).
(3) A photoresist 13 is formed on the silicon nitride film 12 (FIG. 8 (304)).
(4) After removing the photoresist 13 at a desired position by using a normal exposure method, the silicon nitride film 12, the pad oxide film 2 and a part of the silicon substrate 1 are removed by etching, and the surface of the silicon substrate 1 is removed. A shallow groove whose side wall has a predetermined angle with respect to the silicon substrate 1 (for example, the angle of the portion A in the figure is 90 to 110 degrees) is formed {FIGS. 8 (305) to (307)}.
(5) After removing the photoresist 13, the pad oxide film 2 is etched away by about 5 to 40 nm and receded (FIGS. 8 (308) to (309)).
(6) The groove formed in the silicon substrate 1 is H ₂ / O ₂ Thermal oxidation is performed in a gas-mixed oxidizing atmosphere (gas flow ratio r: 0 <r ≦ 0.5) to oxidize the groove formed in the semiconductor substrate 1 until the space of the recessed pad oxide film is filled. {FIG. 8 (310)}.
(7) In this groove oxidation, it is necessary to stop the groove in a range where the inside of the groove is not completely filled in order to minimize the stress caused by the volume expansion of the oxide film. As a result, an insulating film such as a silicon oxide film is deposited and buried in the space remaining in the groove by, for example, a chemical vapor deposition (CVD) method or a sputtering method (hereinafter, buried insulating film 6). In addition, since silicon oxide films and the like manufactured by the chemical vapor deposition method, the sputtering method, and the like are generally rough films, after deposition of the buried insulating film 6, annealing or oxidizing atmosphere at about 1000 ° C. is performed for the purpose of densification. The silicon substrate 1 may be oxidized therein (FIG. 8 (311)).
(8) The embedded insulating film 6 is etched back using a chemical mechanical polishing (CMP) method or a dry etching method. In this case, the silicon nitride film 12 used as the antioxidant film serves as an etching stopper, and has a function of preventing the silicon substrate 1 under the silicon nitride film 12 from being etched {FIG. 8 (312)}.
(9) Then, the trench filling structure is completed by removing the silicon nitride film 12 and the pad oxide film 2 (FIG. 8 (313)). Thereafter, the semiconductor device is completed through, for example, formation of a gate oxide film, a gate electrode, introduction of impurities, formation of a wiring, an interlayer insulating film, etc., formation of a multilayer wiring structure, formation of a surface protection film, and the like, which are necessary for manufacturing the transistor structure. .
[0020]
As described in the first embodiment (see FIG. 5), after the space of the recessed pad oxide film is filled, the silicon nitride film 12 is warped and deformed. Since a compressive stress is generated in the pad oxide film 2 and the silicon substrate 1 under the silicon nitride film 12 by the force of the film bending, oxidation is suppressed by this stress, and as a result, the shape of the silicon substrate near the upper end of the groove is sharp. It becomes something. As described above, by reducing the amount of oxidation until the space of the pad oxide film is filled, no compressive stress due to the warpage deformation is generated, so that the oxidation of the upper end portion of the silicon substrate 1 proceeds smoothly. As a result, a curvature near the upper end of the silicon substrate 1 is achieved.
[0021]
For the above reasons, according to the third embodiment, the radius of curvature near the upper end of the trench isolation structure on the substrate side can be made sufficiently larger than 3 nm. Since it is possible to prevent an acute angle portion near the upper end portion of the groove of the silicon substrate from remaining, it is possible to prevent an increase in a leak current or a decrease in a breakdown voltage characteristic of the transistor due to an electric field concentration near an end portion of the gate electrode film. There is an effect that the property can be improved. Next, a trench embedding structure of a semiconductor device according to a fourth embodiment of the present invention and a manufacturing process thereof will be described with reference to FIGS. FIG. 2 is a sectional structural view of the semiconductor device according to the present embodiment, and FIG. 9 is a flowchart showing an outline of the manufacturing process. Hereinafter, the manufacturing process will be described with reference to FIG. 2 along the flowchart of FIG.
[0022]
(1) The surface of the silicon substrate 1 is thermally oxidized to form the pad oxide film 2 having a thickness of 5 to 50 nm {FIGS. 9 (401) and (402)}.
(2) A silicon nitride film 12 is deposited on the pad oxide film 2 to a thickness of about 10 to 300 nm. This silicon nitride film 12 is used as an antioxidant film when forming the element isolation thermal oxide film 5 (FIG. 9 (403)).
(3) A photoresist 13 is formed on the silicon nitride film 12 (FIG. 9 (404)).
(4) After removing the photoresist 13 at a desired position by using a normal exposure method, the silicon nitride film 12, the pad oxide film 2 and a part of the silicon substrate 1 are removed by etching, and the surface of the silicon substrate 1 is removed. 9 (405)-(407)}, a shallow groove whose side wall has a predetermined angle with respect to the silicon substrate 1 (for example, the angle of the portion A in the figure is 90-110 degrees) is formed.
(5) After removing the photoresist 13, the pad oxide film 2 is etched away by about 10 to 40 nm and receded (FIGS. 9 (408) to (409)).
(6) Then, for example, at 900 to 1100 ° C. in an oxidizing atmosphere H ₂ / O ₂ The surface of the silicon substrate 1 is thermally oxidized at a gas ratio of 1 ppm or less to form a thermal oxide film 5 {FIG. 9 (410)}.
(7) In this groove oxidation, it is necessary to stop the groove in a range where the inside of the groove is not completely filled in order to minimize the stress caused by the volume expansion of the oxide film. As a result, an insulating film such as a silicon oxide film is deposited and buried in the space remaining in the groove by, for example, a chemical vapor deposition (CVD) method or a sputtering method (hereinafter, buried insulating film 6). Further, since the silicon oxide film or the like manufactured by the chemical vapor deposition method, the sputtering method or the like is generally a rough film, after the buried insulating film 6 is deposited, an annealing or oxidizing atmosphere at about 1000 ° C. is performed for the purpose of densification. The silicon substrate 1 may be oxidized therein (FIG. 9 (411)).
(8) The embedded insulating film 6 is etched back using a chemical mechanical polishing (CMP) method or a dry etching method. In this case, the silicon nitride film 12 used as the antioxidant film serves as an etching stopper, and has a function of preventing the silicon substrate 1 under the silicon nitride film 12 from being etched {FIG. 9 (412)}.
(9) Then, the trench filling structure is completed by removing the silicon nitride film 12 and the pad oxide film 2 (FIG. 9 (413)). Thereafter, a semiconductor device is completed through, for example, formation of a gate oxide film and a gate electrode, introduction of impurities, formation of a wiring, an interlayer insulating film, etc., formation of a multilayer wiring structure, formation of a surface protection film, and the like necessary for manufacturing a transistor structure. . explain. In the trench isolation structure of the semiconductor device of the present embodiment, the oxidation amount at the center side surface of the trench is in the range of 5 to 70 nm, and the radius of curvature of the trench at the upper end of the semiconductor substrate is in the range of 3 to 35 nm. Things.
[0023]
Next, the operation and effect of this embodiment will be described with reference to FIG.
[0024]
FIG. 10 shows a result of simulating the relationship between the amount of oxidation of the element isolation thermal oxide film and the radius of curvature on the side surface of the central portion of the groove in accordance with the present embodiment, and a in FIG. From FIG. 10, it can be seen that the radius of curvature R at the upper end of the silicon substrate increases with the amount of oxidation of the trench side wall, and then reaches a maximum value and saturates to a substantially constant value. The maximum value increases as the thickness of the pad oxide film a increases, but is substantially constant (about 35 nm) at 10 nm or more. The reason why the radius of curvature takes the maximum value is that the radius of curvature increases with oxidation of the groove, but gradually fills the space of the recessed pad oxide film, and then, as shown in FIG. It is considered that the silicon nitride film was warped (compression stress was generated in the silicon substrate and the oxide film), and oxidation was suppressed by the compression stress.
[0025]
Through experiments, it has been found by experiments that the radius of curvature R does not adversely affect transistor characteristics if the radius of curvature is about 3 nm or more. Therefore, the oxidation amount of the groove side wall that can secure this radius of curvature becomes 5 nm or more from FIG. 10, and the radius of curvature does not become large even if it is oxidized to 30 nm or more. Therefore, in order to maximize the radius of curvature, it is preferable that the pad oxide film thickness is 10 nm or more and the side wall oxidation amount is 30 nm or more.
[0026]
In this embodiment, by employing this structure and the manufacturing method, it is possible to increase the radius of curvature near the upper end of the groove to about 35 nm, and to reduce the transistor leakage caused by the electric field concentration near the end of the gate electrode film. This has the effect of preventing an increase in current or a decrease in breakdown voltage characteristics, and improving the electrical reliability of the transistor.
[0027]
【The invention's effect】
According to the present invention, in a semiconductor device having a trench isolation structure, it is possible to provide a semiconductor device and a manufacturing method which do not deteriorate the withstand voltage characteristics of transistors and capacitors constituting a circuit.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a manufacturing process of a trench isolation structure in a conventional selective oxidation method.
FIG. 2 is a schematic view of a manufacturing process of the groove separation structure of the first embodiment according to the present invention.
FIG. 3 is a flowchart showing a manufacturing process of the first embodiment according to the present application.
FIG. 4 is a diagram illustrating the operation and effect of the first embodiment according to the present application.
FIG. 5 is a diagram illustrating the operation and effect of the first embodiment according to the present application.
FIG. 6 is a flowchart showing a manufacturing process of a second embodiment according to the present application.
FIG. 7 is a diagram illustrating the operation and effect of the second embodiment according to the present application.
FIG. 8 is a flowchart showing a manufacturing process of a third embodiment according to the present application.
FIG. 9 is a flowchart showing a manufacturing process of a fourth embodiment according to the present application.
FIG. 10 is a diagram illustrating the operation and effect of the fourth embodiment according to the present application.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Pat oxide film, 3 ... Anti-oxidation film, 4 ... Sharp corner part of substrate, 5 ... Element isolation thermal oxide film, 6 ... Buried insulating film, 7 ... gate oxide film, 8 ... gate electrode film, 9 ... insulating film, 10 ... wiring, 11 ... interlayer insulating film, 12 ... silicon nitride film, 13 ... photoresist.

Claims (16)

A method of manufacturing a semiconductor device including the following steps.
(1) forming a pad oxide film on the circuit formation surface of the semiconductor substrate and forming an antioxidant film on the pad oxide film; and (2) forming the oxidation prevention film on a desired position of the circuit formation surface of the semiconductor substrate. Removing the antioxidant film and the pad oxide film to form a groove having a predetermined depth and recessing the pad oxide film by 5 nm or more and 40 nm or less (3) forming the recessed pad oxide film; Oxidizing the semiconductor substrate so that an oxide film is formed on a surface of the groove having an upper end portion of the semiconductor substrate having a radius of curvature of 3 nm or more, and embedding a buried insulating film in the oxidized groove (4). A) removing the buried insulating film formed on the antioxidant film and removing the antioxidant film formed on the circuit formation surface of the semiconductor substrate; and (5) a circuit formation surface of the semiconductor substrate. upon Step the pad oxide film is removed step (6) the pad oxide film formed to form a gate insulating film and a gate electrode on a circuit forming surface of the semiconductor substrate which is removed A method of manufacturing a semiconductor device including the following steps.
(1) forming a pad oxide film on a circuit forming surface of the semiconductor substrate and forming an antioxidant film on the pad oxide film; and (2) forming the antioxidant film at a desired position on the circuit forming surface of the semiconductor substrate. Forming a groove having a predetermined depth by removing the pad oxide film and recessing the pad oxide film toward the periphery by 5 nm or more and 40 nm or less (3) forming the recessed pad oxide film Oxidizing the groove portion formed in the semiconductor substrate in an oxidizing atmosphere having a H ₂ / O ₂ gas ratio of 0.5 or less, and burying a buried insulating film in the oxidized groove (4) the antioxidant film Removing the buried insulating film formed on the semiconductor substrate and removing the antioxidant film formed on the circuit formation surface of the semiconductor substrate. (5) Forming the semiconductor device on the circuit formation surface of the semiconductor substrate. Removing the pad oxide film Step (6) forming a gate insulating film and a gate electrode on a circuit forming surface of the semiconductor substrate to the pad oxide film is removed 3. The method of manufacturing a semiconductor device according to claim 1, wherein the amount of oxidation at a central side surface of the groove of the groove separation structure is in a range of 5 to 70 nm. 4. The method according to claim 1, wherein a radius of curvature of an upper end portion of the semiconductor substrate in the groove is in a range of 3 to 35 nm. Forming a first oxide film on the semiconductor substrate;
Forming a silicon nitride film on the first oxide film;
Selectively removing the silicon nitride film according to the photoresist having the desired pattern;
Selectively removing the first oxide film according to the desired pattern, selectively exposing the semiconductor substrate surface;
Forming a groove in the semiconductor substrate surface according to the desired pattern by selectively removing the exposed semiconductor substrate surface;
The silicon nitride layer of the semiconductor substrate surface of the retraction portion and said groove surface selectively oxidized as a mask in a state where the first oxide film retracted 5nm or 40nm or less from the edge of the groove around the groove Forming the groove having a groove upper end portion of the semiconductor substrate having a radius of curvature of 3 nm or more ;
Depositing an insulating film in the trench formed by the oxidation,
Removing the silicon nitride film formed on the semiconductor substrate outside the trench;
Removing the first oxide film formed on the semiconductor substrate outside the groove,
Forming a gate insulating film and a gate electrode on the semiconductor substrate from which the first oxide film has been removed,
A method for manufacturing a semiconductor device, comprising: 6. The method of manufacturing a semiconductor device according to claim 5, wherein the edge of the first oxide film is receded after forming the groove. 6. The method according to claim 5, wherein the groove is formed after the photoresist is removed. 6. The method according to claim 5, wherein the photoresist is removed after the formation of the groove. A step of forming a plurality of first regions on which a first oxide film and an antioxidant film are stacked on a semiconductor substrate via a second region where the semiconductor substrate is exposed,
A region formed to be lower than the substrate surface by removing the semiconductor substrate surface in the second region, wherein the first oxide film in the first region is narrowed by 5 nm or more and 40 nm or less from a boundary with the second region; Forming a concave region provided around the upper end ,
In a state with the oxide barrier layer, and selectively thermally oxidizing the semiconductor substrate surface of the concave region surface and the narrowed portion of the second region, concave region of the semiconductor substrate having the above curvature radius 3nm Forming the concave region with an edge ;
Filling a space on the second oxide film formed by the thermal oxidation of the concave region with an insulating film;
Removing the antioxidant film and the first oxide film formed on the semiconductor substrate outside the trench,
Forming a gate insulating film and a gate electrode on the semiconductor substrate from which the first oxide film has been removed,
A method for manufacturing a semiconductor device, comprising: Forming a first oxide film on one main surface of the semiconductor substrate;
Forming an antioxidant film on the first oxide film;
Removing the antioxidant film and the first oxide film at a desired position to form an element isolation region;
Wherein said first and oxide film using the first oxide film on the semiconductor substrate surface oxidation film is exposed is removed by etching the first oxide film is removed, the first anti-oxidation film end Forming a groove provided around the upper end with a space recessed from 5 nm to 40 nm from
Thermally oxidizing the space and the inner wall of the groove to form the space having a second oxide film and the groove having a groove upper end of the semiconductor substrate having a radius of curvature of 3 nm or more ;
Depositing a third oxide film on the second oxide film of the groove to fill the groove,
Removing the antioxidant film and the first oxide film on the semiconductor substrate;
Forming a gate insulating film and a gate electrode on the semiconductor substrate from which the first oxide film has been removed,
A method for manufacturing a semiconductor device, comprising: 10. The method according to claim 9 , wherein the step of narrowing is performed after the formation of the concave region. A step of forming a pad oxide film on the circuit formation surface by first thermal oxidation of the semiconductor substrate,
Forming an antioxidant film on the pad oxide film;
A step of partially removing the antioxidant film and the pad oxide film in a region where an element isolation region is formed;
Forming a groove on the surface of the semiconductor substrate in a region where the antioxidant film and the pad oxide film have been removed;
Etching the pad oxide film to form a space in which the pad oxide film is recessed by 5 nm or more and 40 nm or less outside the groove;
Forming, by a second thermal oxidation of the semiconductor substrate, the space having a thermal oxide film and the groove having a groove upper end portion of the semiconductor substrate having a radius of curvature of 3 nm or more ;
Filling a buried insulating film on the thermal oxide film in the groove;
Removing the antioxidant film and the pad oxide film formed on the circuit formation surface of the semiconductor substrate;
Forming a gate insulating film and a gate electrode on the circuit formation surface of the semiconductor substrate from which the pad oxide film has been removed;
A method for manufacturing a semiconductor device, comprising: A step of forming a pad oxide film by first thermally oxidizing the surface of the silicon substrate,
Forming a silicon nitride film thicker than the pad oxide film thickness on the pad oxide film;
Forming a photoresist on the silicon nitride film;
Removing the photoresist at a desired position by exposure,
Removing the silicon nitride film at the position;
Removing the pad oxide film at the position;
Forming a groove by removing the silicon substrate surface exposed at the position,
Removing the photoresist located on the silicon nitride film;
Retreating from the groove side by 5 nm or more and 40 nm or less from the edge of the pad oxide film formed by removing the pad oxide film;
A second thermal oxidation of the recessed region and the formed groove is performed to form the recessed region having a thermal oxide film and the groove having a groove upper end of the semiconductor substrate having a radius of curvature of 3 nm or more. The process of
Depositing a buried insulating film on the thermal oxide film and the silicon nitride film in the trench;
Heat-treating the silicon substrate on which the buried insulating film is formed,
Removing a part of the buried insulating film and the silicon nitride formed on the silicon nitride film;
Removing the remaining silicon nitride film on the pad oxide film;
Removing the pad oxide film located in the region where the silicon nitride film has been removed;
Forming a gate insulating film and a gate electrode on the silicon substrate from which the pad oxide film has been removed;
A method for manufacturing a semiconductor device, comprising: A step of forming a pad oxide film on the circuit formation surface by first thermal oxidation of the semiconductor substrate,
Forming an antioxidant film on the pad oxide film;
Partially removing the antioxidant film and the pad oxide film in the region where the element isolation is to be formed;
Forming a groove on the surface of the semiconductor substrate in a region where the antioxidant film and the pad oxide film have been removed;
Etching the pad oxide film to form a space in which the pad oxide film is recessed by 5 to 40 nm outside the groove;
Forming a thermal oxide film in the space and the trench by the second thermal oxidation of the semiconductor substrate, and forming the trench having an upper end portion of the semiconductor substrate having a radius of curvature of 3 nm or more covered with the thermal oxide film ; The process of
Depositing a buried insulating film on the thermal oxide film and the antioxidant film in the groove;
Removing a part of the buried insulating film and the antioxidant film formed on the antioxidant film by chemical mechanical polishing,
Removing the antioxidant film on the pad oxide film remaining without being removed;
Removing the pad oxide film in the region where the antioxidant film has been removed;
Forming a gate insulating film and a gate electrode on the circuit formation surface of the semiconductor substrate in the region where the pad oxide film has been removed;
A method for manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of removing the silicon nitride film by chemical mechanical polishing after depositing the insulating film. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, 9 to 12, and 14, further comprising removing the antioxidant film by chemical mechanical polishing after depositing the insulating film.

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