JPH10229051A - Gallium-nitrogen semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrode which is loaded in ohmic contact condition on an n or p-type of GaN semiconductor layer, and its formation method. SOLUTION: In the case of an n-type electrode, it is loaded on an n-type GaN semiconductor layer 2 through a coexistent layer B1 of Sn and In or a coexistent region B1 of Si and In, which includes at least one kind selected from among the group of W, Cr, Ti, and Mo and is made on the surface layer of the n-type GaN semiconductor layer 2. In the case of a p-type electrode, it is loaded on a p-type GaN semiconductor layer through a coexistent layer of Zn and In or a coexistent region of Mg and In, which includes at least one kind selected from the group of W and Ti and is made on the surface layer of the p-type GaN semiconductor layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a GaN-based semiconductor device and a method of manufacturing the same, and more particularly, to an n-type (or p-type) semiconductor device.
Type) electrodes and n-type (or p-type) loaded with each
The present invention relates to a GaN-based semiconductor device which achieves good ohmic contact with a GaN-based semiconductor layer, and thus can reliably manufacture various devices using a GaN-based semiconductor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art For example, a hetero bipolar transistor (HBT) using a GaAs III-V compound semiconductor.
Has been attempted. In this case, first, a device precursor having a desired layer structure is manufactured by epitaxially growing a GaAs-based semiconductor having a predetermined composition on a semi-insulating GaAs substrate, for example, by applying the MOCVD method. An emitter electrode and a collector electrode, which are n-type electrodes, are respectively loaded at predetermined locations of the n-type GaAs-based semiconductor layer in the obtained device precursor, and a p-type electrode is disposed at predetermined locations of the p-type GaAs-based semiconductor layer. Is loaded.

For example, when an n-type electrode is loaded, a mask such as an SiO ₂ film is formed on the entire surface of the device precursor by using a plasma CVD apparatus or the like, and then n-type is formed by photolithography or chemical etching. Type Ga
The mask covering the portion where the electrode is to be loaded in the As-based semiconductor layer is removed, and then the material of the n-type electrode is vacuum-deposited on the exposed portion where the electrode is to be loaded.

A major problem at this time is that an ohmic contact is realized between the n-type electrode and the n-type GaAs-based semiconductor layer. It is necessary to select a material whose (φs) is larger than the work function (φm) of the n-type GaAs-based semiconductor. Usually, AuGe is used as the material of the n-type electrode.
/ Au is used, and the emitter electrode may be made of Al and the collector electrode may be made of Au / Cr.

When a p-type electrode is loaded on a p-type GaAs-based semiconductor layer, the same method as described above is applied. Then, in order to realize ohmic contact between the p-type electrode and the p-type GaAs-based semiconductor layer, it is necessary to satisfy φm> φs between them, contrary to the above. Normal,
As a material for the p-type electrode, for example, Au / Zn / Au /
And Al / Cr are used.

However, the above-mentioned materials for the respective electrodes have the following problems. For example, in the case of Al, when the device is operated at a temperature of 600 ° C. or higher, the Al melts and eventually loses its function as an electrode. A
In the case of u, when the device is operated at a high temperature of 500 ° C. or higher, the diffusion of the Au into the semiconductor layer proceeds, and the function of the electrode is also lost.

Incidentally, as in the above-mentioned GaAs-based semiconductor, it belongs to the group III-V compound semiconductor and has the general formula: I
A GaN-based semiconductor represented by nxAlyGa1-x-yN (0 ≦ X <1, 0 ≦ Y <1) has a large band gap and is a direct transition type, so that a light-emitting element such as a light-emitting diode or a laser diode is used. Attention has been focused on light-receiving elements such as photodiodes and phototransistors, as well as materials for electronic devices such as field-effect transistors and the above-described HBTs.

[0008] In the case of manufacturing the above-mentioned various electronic devices using the GaN-based semiconductor, it is necessary to load electrodes at predetermined positions of the GaN-based semiconductor layer. In particular, when manufacturing an HBT, since it is a pn junction type device integrated on the same substrate, n-type GaN
An n-type electrode (emitter electrode and collector electrode) and a p-type GaN-based semiconductor layer
The mold electrode (base electrode) must be loaded in ohmic contact.

However, since the quantum chemical properties of the GaN-based semiconductor have not been completely elucidated yet, φm <φs (in the case of an n-type electrode), which is a necessary condition for realizing an ohmic contact state, Or φm> φs
An electrode material that satisfies (in the case of a p-type electrode) is currently being searched for by trial and error. Up to now, the following can be mentioned as typical examples of the prior art of the electrode material loaded on the GaN-based semiconductor layer.

For example, Japanese Patent Application Laid-Open No. 7-45867 discloses that Ti and Al are used as n-type electrodes of an n-type GaN semiconductor layer.
Or a multilayer film having a structure in which a Ti-only layer and an Al-only layer are laminated. Japanese Patent Application Laid-Open No. 6-275868 discloses that a p-type GaN-based semiconductor layer is formed by attaching an alloy containing Cr and / or Ni to a p-type GaN-based semiconductor layer and then annealing the whole. Is disclosed.

[0011]

SUMMARY OF THE INVENTION According to the present invention, n-type and p-type GaN-based semiconductor layers are loaded with an ohmic contact therebetween, and are used as electrodes even when the device is operated at a high temperature. It is an object of the present invention to provide a GaN-based semiconductor device loaded with an electrode that does not lose the function of the GaN-based semiconductor device and a method of manufacturing the same.

[0012]

According to the present invention, an n-type electrode including at least one selected from the group consisting of W, Cr, Ti, and Mo is an n-type G electrode.
G is loaded on the n-type GaN-based semiconductor layer via a coexistence region of Sn and In or a coexistence region of Si and In formed in a surface portion of the aN-based semiconductor layer.
aN-based semiconductor devices (hereinafter referred to as n-type devices), especially
The Sn concentration and the In concentration in the coexistence region of Sn and In are respectively 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ¹⁸ cm ^−3.
And a GaN-based semiconductor device in which the Si concentration and the In concentration in the coexistence region of Si and In are 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or more, respectively. You.

Further, in the present invention, a laminate composed of a Sn layer and an In layer or a Sn—In alloy layer, or a Si layer and an In layer is provided at a place where an electrode is to be loaded on the n-type GaN-based semiconductor layer. Forming a laminated body or a Si—In alloy layer; forming a thin film including at least one selected from the group consisting of W, Cr, Ti, and Mo on the layer; and heating the whole And the constituent material of the layer is n
A method of manufacturing a GaN-based semiconductor device (hereinafter referred to as a first manufacturing method of an n-type device), and a step of epitaxially growing the n-type GaN-based semiconductor. When forming an n-type GaN-based semiconductor layer by using the method described above, when forming at least the electrode loading scheduled portion on the surface layer, Sn and In or Si
Forming a coexistence region of Sn and In or a coexistence region of Si and In by doping with Co and In; and at least one selected from the group consisting of W, Cr, Ti, and Mo on the coexistence region. Forming a n-type electrode including: a method of manufacturing a GaN-based semiconductor device (hereinafter, referred to as a second method of manufacturing an n-type device).

Further, in the present invention, the group consisting of W and Ti
P-type electrode containing at least one selected from the group consisting of p-type Ga
Coexistence of Zn and In formed on the surface of the N-based semiconductor layer
Through the region or the coexistence region of Mg and In
Ga loaded on an aN-based semiconductor layer
N-type semiconductor devices (hereinafter referred to as p-type devices), especially
Zn concentration and In concentration in the coexistence region of Zn and In
But 1 × 10¹⁹cm^-3Above 1 × 10¹⁸cm^-3Less than
And in the coexistence region of Mg and In
When the Mg concentration and the In concentration are 1 × 10¹⁹cm^-3Less than
Above, 1 × 10¹⁸cm ^-3The GaN-based semiconductor device
Provided.

Further, in the present invention, a laminate composed of a Zn layer and an In layer or a Zn—In alloy layer, or a Mg layer and an In layer is provided at a place where an electrode is to be loaded on the p-type GaN-based semiconductor layer. A step of forming a laminate or an Mg-In alloy layer; a step of forming a p-type electrode containing at least one selected from the group consisting of W and Ti on the layer; and heating the entire layer to form the layer Is made of the p-type GaN
A method of manufacturing a GaN-based semiconductor device (hereinafter referred to as a first manufacturing method of a p-type device), which includes a step of thermally diffusing a p-type GaN-based semiconductor into a p-type GaN-based semiconductor. When forming the GaN-based semiconductor layer, at least the portion where the electrode is to be loaded on the surface layer is formed, Zn and In or Mg and In are doped to coexist the Zn and In region or Mg and In.
Forming a p-type electrode including at least one selected from the group consisting of W and Ti on the coexisting region. A method for manufacturing a semiconductor layer device (hereinafter, referred to as a second method for manufacturing a p-type device) is provided.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an n-type device according to the present invention will be described.
An example will be described with reference to FIG. In FIG. 1, an n-type electrode 1 is loaded on a predetermined portion of an n-type GaN-based semiconductor layer 2 formed by an epitaxial growth method.
The material constituting the n-type electrode 1 is W (melting point: 33).
82 ° C), Cr (melting point: 1905 ° C), Ti (melting point: 1)
800 ° C.), Mo (melting point: 2622 ° C.) or 2
It contains at least one species, and is usually in the form of a thin film having a thickness of about 200 to 300 nm.

Specifically, it may be a single layer composed of any one of W, Cr, Ti, and Mo, or a single layer composed of an alloy composed of two or more of these metals.
Further, as shown in FIG. 2, a laminated structure in which thin layers 1a and 1b of different materials such as W and Cr are alternately laminated may be used. Generally, even when operating a GaN-based semiconductor device at a high temperature, the operating temperature is 100 ° C.
It is controlled to 0 ° C. or less. This is because, when the GaN-based semiconductor is operated at a higher temperature, thermal decomposition of the GaN-based semiconductor itself starts and the device function is lost. Therefore, in the case of the n-type electrode 1, its melting point is much higher than the operation limit temperature of the device, and the device does not behave as melting or diffusing when the device is operated at a high temperature. I will not do it.

This n-type electrode 1 is formed on a surface layer 2A of an n-type GaN-based semiconductor layer 2 by a Sn layer formed by a method described later.
It is loaded through a coexistence region of Si and In or a coexistence region of Si and In (these are shown in FIG. 1 as a coexistence region B1). With the coexistence region B1 interposed, n
The adhesion between the mold electrode 1 and the n-type GaN-based semiconductor layer 2 is good, and a good ohmic contact state is realized.

As shown in FIGS. 1 and 2, the coexistence region B1 is partially formed in the surface portion 2A of the n-type GaN-based semiconductor layer 2 with a thickness (t) immediately below the n-type electrode 1. Alternatively, as shown in FIG. 3, it may be formed over the entire surface portion 2A with a certain thickness (t). Further, the entire n-type GaN-based semiconductor layer 2 may be the coexistence region B1.

The coexistence region B1 is composed of a region where Sn and In coexist (hereinafter, referred to as a first coexistence region).
Or a region where Si and In coexist (hereinafter, referred to as
(Referred to as a second coexistence area). In the case of the first coexistence region, the Sn concentration is 1 × 10 ¹⁹ cm ⁻³ or more on average, the In concentration is 1 × 10 ¹⁸ cm ⁻³ or more on average, and the second concentration is 2 × 10 ¹⁸ cm ⁻³ or more. In the case of the coexistence region, the Si concentration is 1 × 10 ¹⁹ cm ^{−3 on} average.
As described above, the In concentration is 1 × 10 ¹⁸ cm ⁻³ or more on average.

If this condition is not satisfied, the first
N-type electrode 1 in the coexistence region and the second coexistence region
, A good ohmic contact state cannot be obtained between the two. However, Sn and In or Si and I
If the concentration of n becomes excessively high, the state becomes equivalent to the situation where impurities are mixed in the GaN-based semiconductor layer 2. Therefore, the upper limits of the concentrations of Sn and In in the first coexistence region are each 5 × 10 ^20. cm ⁻³ and 1 × 10 ²⁰ cm ⁻³ , and the upper limits of the concentrations of Si and In in the second coexistence region are preferably controlled to 5 × 10 ²⁰ cm ⁻³ and 1 × 10 ²⁰ cm ⁻³ , respectively. .

This n-type electrode can be formed as follows. This will be described with an example where the coexistence area B1 is the first coexistence area. First, a first method for forming an n-type electrode will be described. In this method, first, M
An n-type GaN-based semiconductor layer to be loaded with an electrode by forming another epitaxial growth layer required by a known film forming method such as an OCVD method or an MBE method and then epitaxially growing an n-type GaN-based semiconductor on the top layer. Is formed.

Next, as shown in FIG. 5, the Sn layer 3a and the In layer 3b are laminated at the electrode loading planned portions of the n-type semiconductor GaN-based semiconductor layer 2 by applying, for example, a vacuum deposition method to form a laminate 3 To form Further, instead of forming the laminate 3, an Sn—In alloy layer having a predetermined composition may be formed. In this step, it goes without saying that the surface of the n-type GaN-based semiconductor layer other than the above-mentioned electrode loading portion is masked.

Next, on the formed laminated body 3, W, Cr, Ti,
An electrode 1 containing one or two or more types of Mo is formed into a device precursor (see FIG. 5). Thereafter, a heat treatment is performed on the obtained device precursor. Specifically, 500
A heat treatment is performed in a temperature range of ６００600 ° C. for 20 to 60 minutes.

As a result of this heat treatment, the melting points of Sn and In constituting the laminate 3 are 231.9 ° C., respectively.
Since the temperature is as low as 156.4 ° C., it is thermally diffused from the surface of the n-type GaN-based semiconductor layer 2 toward the inside to a depth of about 200 to 300 °, and as a result, as shown in FIGS. The surface portion 2A of the n-type GaN-based semiconductor layer 2 is 200 to 3
It is converted into the first coexistence region B1 having a thickness (t) of about 00 °.

When the laminate 3 is formed, by changing the thickness of the Sn layer 3a and the thickness of the In layer 3b, the Sn concentration in the first coexistence region B1 formed after the above-described heat treatment is reduced. The In concentration can be changed. In the case where an Sn—In alloy is used, the first coexistence region B can be formed by using alloys having different compositions.
1, the Sn concentration and the In concentration can be changed.

For example, Sn in the first coexistence area B1
The concentration and the In concentration are set to 1 × 10 ¹⁹ cm ⁻³ or more, respectively.
When the thickness is 10 ¹⁸ cm ^-3 or more, it is preferable that the thickness of the Sn layer 3a is 90 to 110 °, the thickness of the In layer 3b is 15 to 30 °, and the total thickness is 100 to 140 °. It should be noted that although the temperature varies depending on the combination of the heating temperature and the heating time during the heat treatment, not all the components of the above-described stacked body 3 thermally diffuse to the n-type GaN-based semiconductor layer 2 during the heat treatment. , Generally n-type GaN
The components adjacent to the system semiconductor layer 2 are thermally diffused preferentially, and the components adjacent to the n-type electrode 1 may be left in a metal or alloy state. In the present invention, it is assumed that the first coexistence region is formed. In the present invention, the average value of the Sn concentration and the In concentration in the first coexistence region in that state is referred to as Sn concentration or In concentration in the present invention.

Next, a second method for manufacturing an n-type device will be described. In this method, first, when an n-type GaN-based semiconductor layer on which an n-type electrode is to be loaded is formed by an epitaxial growth method, at least Sn and In are present at the electrode loading planned portions.
Doping. At that time, first, only the n-type GaN-based semiconductor is epitaxially grown, and then, from the time when the surface layer portion 2A having the thickness t as shown in FIGS.
The first coexistence region may be formed by doping n and In. If the n-type GaN-based semiconductor layer 2 doped with Sn and In does not impair the device function, the n-type G
During the epitaxial growth of the aN-based semiconductor, Sn and In are doped from the beginning, and as shown in FIG.
The entire N-type semiconductor layer 2 may be the first coexistence region.

By applying, for example, a vacuum deposition method to the thus formed first coexistence region, the above-mentioned electrode material is deposited into a device. In this case, n
Unlike the case of the first manufacturing method of the mold device, the heat treatment is not necessarily required, but the heat treatment is performed in a temperature range of 400 to 700 ° C.
When the heat treatment is performed for about 30 minutes, the n-type electrode and the n-type Ga
This is preferable because the familiarity with the surface layer portion of the N-based semiconductor layer is improved.

In the case of the second coexistence region where Si and In coexist, an n-type electrode can be formed at a portion where an electrode of the n-type GaN-based semiconductor layer is to be loaded by the same method as described above. . Next, the p-type device will be described. In the p-type device of the present invention, the material of the p-type electrode is made of W or / and Cr, and the p-type electrode is formed by epitaxial growth.
It is the same as the case of the n-type device except that it is loaded on the surface layer of the type GaN-based semiconductor layer.

However, the surface portion of the p-type GaN-based semiconductor layer on which the p-type electrode is loaded is different from that of the above-described n-type GaN-based semiconductor layer. That is, the surface layer portion on which the p-type electrode is to be loaded is located in a region where Zn and In coexist (hereinafter, referred to as a region).
This is referred to as a third coexistence region) or a region where Mg and In coexist (hereinafter, referred to as a fourth coexistence region). The presence of such a coexistence region realizes an ohmic contact state between the p-type electrode and the p-type GaN-based semiconductor layer.

At this time, in the third coexistence area, Z
n concentration is 1 × 10 ¹⁹ cm ⁻³ or more and In concentration is 1 × 10
¹⁸ cm ⁻³ or more, and in the fourth coexistence region, the Mg concentration is 1 × 10 ¹⁹ cm ⁻³ or more and the In concentration is 1 × 10 ¹⁸ cm ⁻³ or more. is important.
Then, for the same reason as described for the n-type device,
In the coexistence region, the upper limit of the Zn concentration is 5 × 10 ²⁰ cm ⁻³ ,
The upper limit of the n concentration is 1 × 10 ²⁰ cm ⁻³ , and in the fourth coexistence region, the upper limit of the Mg concentration is 5 × 10 ²⁰ cm ⁻³ , and the upper limit of the In concentration is 1 × 10 ²⁰ cm ^−3. Is preferred.

This p-type device can be formed by applying the first and second manufacturing methods of the n-type device described for the n-type device. That is, in the first manufacturing method of the p-type device, as a material for forming the coexistence region,
After a device precursor is manufactured using Zn and In or Mg and In, heat treatment may be performed. In the case of forming the third coexistence region, the heat treatment is preferably performed in a temperature range of 450 to 750 ° C. for 5 to 30 minutes because the melting point of Zn is 419 ° C. When forming the fourth coexistence region,
Since the melting point of Mg is 650 ° C., the heat treatment is performed at 650 ° C.
It is preferable to carry out in a temperature range of up to 750 ° C. for 5 to 30 minutes.

In the second method of manufacturing a p-type device, when forming a p-type GaN-based semiconductor layer by an epitaxial growth method, Zn and In (in the case of a third coexistence region) or Mg and In (in the case of the fourth coexistence region) may be doped. Then, after the coexistence region is formed, a p-type electrode may be loaded thereon by, for example, vacuum deposition.

[0035]

【Example】

Examples 1 and 2 and Comparative Examples 1 to 3 On a surface of an n-type GaN layer (n-type dopant is Si) epitaxially grown by a MOMBE method, Sn was deposited by a vacuum evaporation method.
Layers and In layers were alternately laminated to form a laminate. At this time, the thickness of each layer was changed as shown in Table 1.

Next, T was deposited on the laminate by vacuum evaporation.
Two n-type electrodes were loaded by alternately laminating thin layers of i and Mo. The overall thickness of the Ti thin layer was 150 nm, and the overall thickness of the Mo thin layer was 50 nm. Thereafter, the obtained device precursor was subjected to a heat treatment at a temperature of 600 ° C. for 10 minutes.

With respect to each of the obtained devices, the ohmic characteristics between the two electrodes were measured according to the following specifications. Measurement of ohmic characteristics: Current-voltage characteristics between both electrodes were examined by Van der Pauw method. Use a constant voltage source and set the voltage between 0 and
The current value flowing during the test within the range of 100 V was examined.

After the measurement of the ohmic characteristics, the Sn concentration and the In concentration in the diffusion layer formed at the interface between the electrode and the n-type GaN layer were measured according to the following specifications. Measurement of diffusion layer thickness: Secondary ion mass spectrometer (SIM
Using S), while sputtering Ar on the sample surface, the concentration distribution of Sn and In inward from the sample surface,
That is, the concentration distribution of Sn and In in the depth direction is examined, and S
The thickness of the n, In diffusion layer was measured.

The above results are collectively shown in Table 1.

[0040]

[Table 1]

As is clear from Table 1, the Sn concentration at the interface between the n-type electrode and the n-type GaN layer was 1 × 10 ¹⁹ cm ^−3.
As described above, the ohmic contact state is realized only when the condition of the In concentration of 1 × 10 ¹⁸ cm ⁻³ or more is simultaneously satisfied. Examples 3 to 5 and Comparative Examples 5 to 8 On the surface of an n-type GaN layer (n-type dopant is Si) epitaxially grown by the MOMBE method,
Layers and In layers were alternately laminated to form a laminate. At this time, the thickness of each layer was changed as shown in Table 2.

Next, W is deposited on the laminate by vacuum evaporation.
And n thin layers of Cr were alternately stacked to load two n-type electrodes. The overall thickness of the W thin layer was 150 nm, and the overall thickness of the Cr thin layer was 50 nm. Thereafter, the obtained device precursor was subjected to a heat treatment at a temperature of 600 ° C. for 20 minutes.

Various characteristics of the obtained device were measured in the same manner as in Example 1. The results are shown in Table 2.

[0044]

[Table 2]

As is clear from Table 2, the Si concentration is 1
When the In concentration is 1 × 10 ¹⁹ cm ⁻³ or more and the In concentration is 1 × 10 ¹⁸ cm ⁻³ or more, an ohmic contact state is realized with the n-type GaN layer. Examples 6 to 8 and Comparative Examples 8 to 10 The surface of a p-type GaN layer (p-type dopant is Mg) epitaxially grown by the MOMBE method is coated with Zn by a vacuum deposition method.
Layers and In layers were alternately laminated to form a laminate. At this time, the thickness of each layer was changed as shown in Table 3.

Then, W is deposited on the laminate by vacuum evaporation.
And p-type electrodes were loaded by alternately laminating thin layers of Ti and Ti. The overall thickness of the W thin layer was 150 nm, and the overall thickness of the Ti thin layer was 50 nm. Thereafter, the obtained device precursor was subjected to a heat treatment at a temperature of 700 ° C. for 10 minutes.

Various characteristics of the obtained device were measured in the same manner as in Example 1. Table 3 shows the results.

[0048]

[Table 3]

As is clear from Table 3, the p-type GaN layer located under the loaded p-type electrode has a Zn concentration of 1 × 10 ¹⁹
When cm ^-3 or more and the In concentration to form a 1 × 10 ¹⁸ cm ^-3 or more regions, the ohmic contact is realized. Examples 9 to 11 and Comparative Examples 11 to 15 The surface of a p-type GaN layer (p-type dopant is Mg) epitaxially grown by the MOMBE method is coated with Mg by a vacuum deposition method.
Layers and In layers were alternately laminated to form a laminate. At this time, the thickness of each layer was changed as shown in Table 4.

Then, W is deposited on the laminate by vacuum evaporation.
And p-type electrodes were loaded by alternately laminating thin layers of Ti and Ti. The overall thickness of the W thin layer was 150 nm, and the overall thickness of the Ti thin layer was 50 nm. Thereafter, the obtained device precursor was subjected to a heat treatment at a temperature of 700 ° C. for 10 minutes.

Various characteristics of the obtained device were measured in the same manner as in Example 1. Table 4 shows the results.

[0052]

[Table 4]

As is clear from Table 4, the p-type GaN layer has an Mg concentration of 1 × 10 ¹⁹ cm ⁻³ or more and an In concentration of 1 × 1
An ohmic contact between the two regions can be realized only after a region of at least ¹⁸ cm ^-3 is formed and a p-type electrode is loaded therein. Example 12 By applying the method of the present invention described above using an ultrahigh vacuum apparatus having a normal crystal growth chamber and a patterning chamber,
An HBT was manufactured according to the following procedure. This will be described with reference to the drawings.

(1) First, the sapphire substrate 4 is set in the crystal growth chamber, and dimethylhydrazine (3 × 10 ⁻⁶ Torr) is set.
GaN was epitaxially grown on the surface of the sapphire substrate 4 by MBE using GaN and metal Ga (5 × 10 ⁻⁷ Torr) to form a GaN buffer layer 5. The growth temperature is 65
0 ° C. Then, metal Ga (1 × 10 ⁻⁶ Torr), metal Al (5 × 10 ⁻⁷ Torr) and NH ₃ (5 × 10 ⁻⁵ Torr)
And Si (5 × 10 ⁻⁸⁾ as an n-type dopant.
Torr), a low-concentration n-type AlGaN layer 6 and a high-concentration n-type AlGa
N layers 7 were sequentially formed to obtain the laminated structure shown in FIG.
Here, the high-concentration AlGaN layer 7 functions as a collector layer later.

(2) Then, after forming 15 monolayers of metallic Ga on the entire surface of the high-concentration n-type AlGaN layer 7,
10 torr of oxygen is introduced therein, and Ga
An oxide film 8 was formed (see FIG. 7). Then, a metal mask having a pattern opening corresponding to the pattern of the base electrode was arranged on the Ga oxide film 8, and the surface of the Ga oxide film 8 exposed from the pattern opening was irradiated with metal Ga.

Then, by removing the metal mask and heating the whole to a temperature of 550 ° C., only the Ga oxide film 8 on which the metal Ga is adhered is thermally removed, and as shown in FIG. An opening 8a for forming a base layer was formed in the film 8. (3) Then, trimethylgallium (3 × 10 ⁻⁷ Torr) and dimethyl aluminum hydride (1 × 10 ⁻⁷ Torr)
And dimethylhydrazine (5 × 10 ⁻⁵ Torr) and disilane (n-type dopant, 1 × 10 ⁻⁹ Torr), and at a growth temperature of 610 ° C., a high-concentration n-type AlGaN layer 8 exposed from the opening 8a. After the low-concentration n-type AlGaN is selectively grown on the surface of the substrate to form a low-concentration n-type AlGaN layer 9, trimethylgallium (3 × 10 ⁻⁷ To
rr) and dimethyl aluminum hydride (1 × 10 ⁻⁷⁾
Torr) and metallic Mg (p-type dopant; 3 × 10 ^-9 Torr)
And dimethylhydrazine (5 × 10 ⁻⁵ Torr),
High-concentration p-type AlGaN was selectively grown at a temperature of 610 ° C. to form a high-concentration p-type AlGaN layer 10 (see FIG. 9).

Here, the high-concentration p-type AlGaN layer 10 functions as a base layer. (4) Next, a monolayer of metallic Ga is applied to the entire surface.
After forming the layer, 10 Torr of oxygen was introduced therein, and a Ga oxide film 11 was formed under light irradiation. Then, Ga
A metal mask having a pattern opening corresponding to the pattern of the emitter electrode is arranged on the oxide film 11, the surface of the Ga oxide film 11 exposed from the pattern opening is irradiated with metal Ga, and the metal mask is removed. By heating to a temperature of 550 ° C., only the Ga oxide film 11 on which the metal Ga is adhered and the Ga oxide film 8 located immediately below the Ga oxide film 11 are thermally removed, and the Ga oxide film 11 and the Ga oxide film 8 are removed.
Then, an opening 11a for an emitter layer was formed (see FIG. 10).

(5) Then, trimethylgallium (3 × 1
0 ^-7 Torr), dimethylhydrazine (5 × 10 ^-5 Torr), and disilane (n-type dopant: 1 × 10 ^-9 Torr) at a growth temperature of 610 ° C. and a high concentration exposed from the opening 11a. After the n-type GaN is selectively grown on the surface of the n-type AlGaN layer 7 to form the n-type GaN layer 12, trimethylgallium (3 × 10 ⁻⁷ Torr) and dimethylhydrazine (5 × 10 ⁻⁵ Torr) are further formed thereon. Torr), dimethyl aluminum hydride (1 × 10 ^-7 Torr) and disilane (n
Type dopant: 1 × 10 ^-9 Torr) and a growth temperature of 6
High-concentration n-type AlGaN was selectively grown at 10 ° C. to form a high-concentration n-type AlGaN layer 13 (see FIG. 11).

This high-concentration n-type AlGaN layer 13 subsequently functions as an emitter layer. Thereafter, the whole is heated at a temperature of 630 ° C. in a vacuum atmosphere, and the Ga oxide film 1 is heated.
1 and the Ga oxide film 8 were all removed thermally (see FIG. 12). (6) Then, a metal mask having a pattern opening corresponding to the pattern of the emitter electrode and the pattern of the collector electrode was arranged on the entire surface. Then, the surface of the high-concentration n-type AlGaN layer 13 and the high-concentration n-type AlGaN layer 7, which are exposed from the pattern openings,
A Sn—In alloy layer 3 consisting of 95% by weight of n and 5% by weight of In is formed to a thickness of 13 nm, and a thin film (n) having a total thickness of the thin Ti layer and the thin Mo layer of 50 nm is formed thereon. A mold electrode 14 was formed (see FIG. 13).

(7) Then, a metal mask having a pattern opening corresponding to the pattern of the base electrode was arranged on the entire surface. Then, on the surface of the high-concentration p-type AlGaN layer 10 exposed from the pattern opening, a Zn-In alloy layer 3 'consisting of 95% by weight of Zn and 5% by weight of In is formed to a thickness of 15 nm. A thin film body (p-type electrode) 15 in which the W thin layer has an overall thickness of 150 nm and the Ti thin layer has an overall thickness of 50 nm by alternately laminating a W thin layer and a Ti thin layer thereon.
Was formed (see FIG. 14).

(8) Finally, the whole is heated to a temperature of 650 ° C.
For 20 minutes. As a result, as shown in FIG. 15, the high-concentration n-type AlGaN layer 13 located below the n-type electrode (emitter electrode) 14 and the high-concentration n-type AlGaN layer 13 located below another n-type electrode (collector electrode) 15. A diffusion layer B1 having a thickness of about 30 ° is recognized in each of the p-type AlGaN layers 7, and a diffusion layer B1 having a thickness of about 50 ° is formed in the high-concentration p-type AlGaN layer 10 located below the p-type electrode (base electrode) 15. Layer B1 'was observed.

[0062]

As is apparent from the above description, the device manufactured by the method of the present invention can be used to load n-type (or p-type).
(Type) electrode and an n-type (or p-type) GaN-based semiconductor layer, an ohmic contact state is realized. Therefore, according to the method of the present invention, it is possible to reliably manufacture various devices using a GaN-based semiconductor. become able to. Since these electrodes are made of a high melting point metal such as W, Cr, Ti, and Mo, they do not melt even under high-temperature operation of the device and do not lose their function as electrodes.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a state in which an n-type electrode is loaded on a surface layer of an n-type GaN-based semiconductor layer.

FIG. 2 is a sectional view showing another example of an n-type electrode.

FIG. 3 is a cross-sectional view showing another state in which an n-type electrode is loaded on a surface portion of an n-type GaN-based semiconductor layer.

FIG. 4 is a cross-sectional view showing still another state in which an n-type electrode is loaded on a surface portion of an n-type GaN-based semiconductor layer.

FIG. 5 shows that S is located at the electrode loading position of the n-type GaN-based semiconductor layer.
It is sectional drawing which shows the state which loaded the n-type electrode via the laminated body of the n single layer and the In single layer.

FIG. 6 shows a GaN-based buffer layer on a sapphire substrate,
It is sectional drawing which shows the state which laminated | stacked the low concentration n-type AlGaN layer and the high concentration AlGaN layer.

FIG. 7 is a cross-sectional view showing a state in which a Ga oxide film is formed on a high-concentration AlGaN layer.

FIG. 8 is a cross-sectional view showing a state in which an opening is formed in a Ga oxide film.

FIG. 9 is a cross-sectional view showing a state where a base layer is formed.

FIG. 10 is a sectional view showing a state in which an opening for forming an emitter layer is formed in the Ga oxide film further formed.

FIG. 11 is a cross-sectional view showing a state where an emitter layer is formed.

FIG. 12 is a cross-sectional view showing a state where a Ga oxide film has been removed.

FIG. 13 is a sectional view showing a state where an emitter electrode and a collector electrode are loaded.

FIG. 14 is a sectional view showing a state where a base electrode is loaded.

FIG. 15 is a cross-sectional view showing an HBT manufactured by applying the method of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 n-type electrode 1 a, 1 b thin layer of electrode material 2 n-type GaN-based semiconductor layer 2 A surface portion of n-type GaN-based semiconductor layer 3, 3 ′ laminated body 3 a, 3 b laminated material layer B1 coexistence region (diffusion layer 4) Sapphire substrate 5 GaN buffer layer 6 Low-concentration n-type AlGaN layer 7 High-concentration n-type AlGaN layer 8 Ga oxide film 8a Opening of Ga oxide film 8 9 Low-concentration n-type AlGaN layer 10 High-concentration p-type AlGaN layer 11 Ga Oxide film 11a Opening of Ga oxide film 11 12 n-type AlGaN layer 13 high concentration n-type AlGaN layer 14 n-type electrode 15 p-type electrode

Claims (8)

[Claims] An n-type electrode including at least one selected from the group consisting of W, Cr, Ti, and Mo is formed on a surface region of an n-type GaN-based semiconductor layer in a coexistence region of Sn and In or with Si. A GaN-based semiconductor device, wherein the GaN-based semiconductor device is loaded on the n-type GaN-based semiconductor layer via a region coexisting with In. 2. S in the coexistence region of Sn and In
n concentration and In concentration are respectively 1 × 10 ¹⁹ cm ⁻³ or more,
1 × 10 ¹⁸ cm ⁻³ or more, and the Si concentration and the In concentration in the coexistence region of Si and In are respectively 1
2. The size is not less than × 10 ¹⁹ cm ^{−3 and not} less than 1 × 10 ¹⁸ cm ^−3.
GaN-based semiconductor device. 3. A laminate comprising an Sn layer and an In layer or an Sn-
A step of forming an In alloy layer, or a laminate composed of a Si layer and an In layer or a Si—In alloy layer; on the layer, at least one selected from the group consisting of W, Cr, Ti, and Mo; Manufacturing a GaN-based semiconductor device, comprising: a step of forming a thin film including the same; and a step of heating the whole to thermally diffuse the constituent material of the layer into the n-type GaN-based semiconductor layer. Method. 4. When forming an n-type GaN-based semiconductor layer by epitaxially growing an n-type GaN-based semiconductor, at least forming a portion of the surface layer where an electrode is to be loaded is doped with Sn and In or Si and In. And S
forming a coexisting region of n and In or a coexisting region of Si and In; and forming an n-type electrode containing at least one selected from the group consisting of W, Cr, Ti, and Mo on the coexisting region. Forming step;
A method for manufacturing a GaN-based semiconductor device, comprising: 5. At least one selected from the group consisting of W and Ti
A p-type electrode containing seeds is loaded on the p-type GaN-based semiconductor layer via a coexisting region of Zn and In or a coexisting region of Mg and In formed in a surface layer of the p-type GaN-based semiconductor layer. A GaN-based semiconductor device. 6. Z in the coexistence region of Zn and In
n concentration and In concentration are respectively 1 × 10 ¹⁹ cm ⁻³ or more,
1 × 10 ¹⁸ cm ⁻³ or more, and the Mg concentration and the In concentration in the coexistence region of Mg and In are 1
6. The size is not less than × 10 ¹⁹ cm ^{-3 and not} less than 1 × 10 ¹⁸ cm ^-3.
GaN-based semiconductor device. 7. A laminated body composed of a Zn layer and an In layer or a Zn-
A step of forming an In alloy layer, or a laminate composed of an Mg layer and an In layer, or a Mg—In alloy layer; p containing at least one selected from the group consisting of W and Ti on the layer;
Forming a mold electrode; and heating the whole to thermally diffuse the constituent material of the layer into the p-type GaN-based semiconductor layer. 8. When a p-type GaN-based semiconductor is epitaxially grown to form a p-type GaN-based semiconductor layer, Zn and In or Mg and In are doped at least when an electrode loading scheduled portion is formed at least on a surface layer. And Z
forming a coexisting region of n and In or a coexisting region of Mg and In; and forming a p-type electrode including at least one selected from the group consisting of W and Ti on the coexisting region; A method for manufacturing a GaN-based semiconductor device, comprising: