JPH10224683A - Image data processing unit and image data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image data processing unit that converts an inverted image into an erected image and converts noninterlace scanning into interlace scanning. SOLUTION: The device is provided with a means that instructs either the erected mode MD or the inverted mode, a means that writes image data sequentially in the unit of lines to a 1st buffer 10, a means that writes the image data stored in the 1st buffer to a memory 11 by one frame, a means that reads image data from the memory by scanning the data by the interlace system in an opposite direction to the scanning direction for memory write and writes the image data to a 2nd buffer 12 in the unit of lines, and a means that reads sequentially the image data from the 2nd buffer 12 in the unit of lines and provides an output of the image data by the interlace system in the unit of frames received at an input terminal while inverting the data depending on the mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to image data processing, and more particularly to an image data processing technique for converting image data supplied from a video source into a format suitable for display.

[0002]

2. Description of the Related Art FIG. 6A is a front view of a video camera in normal use, and FIG. 6B is a side view thereof.

The video camera 40 has a lens 46 and a liquid crystal display (LCD) 44. The photographer photographs the subject through the lens 46. The subject is a liquid crystal display 44
Will be displayed. The photographer can shoot while checking the subject displayed on the liquid crystal display 44.

A subject is imaged through a lens 46 on a solid-state image pickup device having a photodiode and a charge-coupled device (hereinafter, referred to as a CCD). The CCD transfers charges in the order of pixels according to the interlaced or non-interlaced method. The liquid crystal display 44 receives an image signal generated by the solid-state imaging device and displays an image.

[0005] The video camera 40 has housings 41 and 42. The housings 41 and 42 are connected by a shaft 43 and are mutually rotatable. The housing 41 includes a liquid crystal display 44
, And the housing 42 has a lens 46.

When the housing 41 is fixed and the shaft 42 is rotated about the shaft 43 as a rotation axis, the video camera 40
(C) and (D).

FIG. 6C is a front view of the video camera after rotation, and FIG. 6D is a side view thereof.

[0008] The lens 46 is directed in the direction of the photographer (frontward in the figure), so that the photographer can photograph himself. The liquid crystal display 44 displays the subject itself.

[0009] However, simply rotating the housing 42 may cause the subject to be photographed upside down and left and right. That is, the subject displayed on the liquid crystal display device 44 of the video camera after the rotation shown in FIG. 6C is inverted in the vertical and horizontal directions with respect to the one before the rotation shown in FIG.

Hereinafter, the state of the video camera shown in FIGS. 6A and 6B is called an upright state, and the state of the video camera shown in FIGS. 6C and 6D is called an inverted state. FIG.
An image in which the vertical and horizontal directions of the image are the same as that of the subject, such as the image displayed on the liquid crystal display 44 in FIG. 6A, is called an erect image, and is displayed on the liquid crystal display 44 in FIG. An image in which the vertical and horizontal directions of the image are opposite to those of the subject, such as an inverted image, is called an inverted image.

It is desirable that the video camera can capture an upright image whether it is in an upright state or an inverted state. When the video camera is in the inverted state, there is a method of displaying an erect image by changing the driving method of the CCD or the liquid crystal display from the normal state. That is, the direction of scanning the subject when generating the image signal is reversed. Alternatively, the direction of scanning on the display screen when displaying is reversed.

However, the control for changing the driving method of the CCD or the liquid crystal display is complicated. Further, since the above-described special control cannot be performed with a general-purpose CCD or liquid crystal display, it is necessary to prepare a dedicated CCD or liquid crystal display.

In addition to changing the driving method of the CCD or the liquid crystal display, there is a method of photographing an erect image using a frame memory for two frames. In other words, this method is a method in which an inverted image is once fetched into the frame memory and then converted into an erect image. However, since two frames of memory are required, the cost increases and the device becomes larger.

Video sources (image signal sources) including the above-mentioned solid-state image sensor include those that output signals in an interlaced manner and those that output signals in a non-interlaced manner. On the other hand, many display devices (television monitors) including the above-described liquid crystal display generally input signals in an interlaced manner.

When a video source outputs image data in a non-interlaced format, it is necessary to convert the image data from the non-interlaced format to an interlaced format and supply the converted data to a display device. That is, non-interlaced / interlaced conversion is necessary for normal display on the display device.

FIG. 7 shows two examples of a conventional non-interlace / interlace converter.

In FIG. 7A, a VRAM (Video)
The conversion is performed by controlling the writing and reading of image data to and from the (RAM) 51. The non-interlaced signal NIL from the video source 50 is
1 is stored in a DRAM (not shown).

Image data for one line is sequentially transferred from one frame of image data stored in the DRAM to a SAM (Serial RAM, not shown) in the VRAM 51. At the time of this transfer, for example, the read address is controlled so that the data of the field composed of the odd-numbered lines is read after the data of the field composed of the even-numbered lines are all read in line units. The interlaced image data is displayed by sequentially reading out the image data IL from the SAM to the display device 52 sequentially.

FIG. 7B shows two parallelly arranged DRAMs.
Non-interlaced / interlaced conversion is performed by using 53 and 54. The non-interlaced signal NIL from the video source 50 is, for example,
One frame of data is written to M53. At this time, on the output side, the DRAM 54 is selected by the switch 55. From the DRAM 54, for example, by reading all the data of the fields of the even-numbered lines in line units and then reading the data of the fields of the odd-numbered lines, the interlace signal IL is formed and output to the display device 52.

After the writing to the DRAM 53 is completed,
The switch 54 selects the DRAM 54. DRA
New frame data is written to M54. At the same time, the DRAM 53 is selected on the output side by the switch 55. The DRAM 53 outputs the interlace signal IL to the display device 52.

By repeating the above, non-interlaced data can be converted to interlaced data.

The VRAM used in the case of FIG. 7A is twice as expensive as a general DRAM, and the VRAM of FIG. 7B requires two DRAMs.
There is a problem that the cost as a conversion device becomes high.

[0023]

In order to capture an upright image when the video camera is turned upside down, (1) C
There is a method of changing the drive method of the CD or the liquid crystal display, or (2) a method of using a two-frame memory. However, in the method of (1), the control is complicated and a dedicated CCD or liquid crystal display is required. The method 2) requires a large-capacity memory.

In order to perform non-interlace / interlace conversion, there are a method using a VRAM as shown in FIG. 7A and a method using two DRAMs as shown in FIG. 7B. There are, however, all of these costs are high.

An object of the present invention is to provide an image data processing technique capable of converting an inverted image into an erect image and converting a non-interlaced system into an interlaced system at a low cost when the video camera is in an inverted state. To provide.

[0026]

According to one aspect of the present invention, first and second buffers, each capable of buffering one line of image data, and storing one frame of image data. Memory, an input terminal for inputting frame-based image data in a non-interlaced manner, and first buffer writing means for sequentially writing image data input to the input terminal to the first buffer in line units And writing the image data stored in the first buffer into the memory at a speed twice or more the writing speed of the first buffer writing means, and storing the image data for one frame in the memory. Memory writing means, and the memory writing means writes to the memory at the same speed as the writing speed of the memory writing means. The 査 direction by scanning in an interlaced manner in the opposite direction reads the image data from said memory,
A second buffer writing means for writing to the second buffer line by line; and sequentially reading out image data in line units from the second buffer and inverting the frame-by-frame image data input to the input terminal. An image data processing apparatus having output means for outputting in a race system is provided.

By using a memory in the high-speed access mode, an image input to the input terminal can be inverted / erected and non-interlaced / interlaced and output. That is, when image data of an inverted image is input to the input terminal in a non-interlaced manner, the output means outputs image data of the upright image in an interlaced manner.
For example, an upright image can be displayed or photographed even when the video camera is in an inverted state.

According to another aspect of the present invention, a first and a second buffer each capable of buffering half the image data of one line, and a memory capable of storing the image data. An input terminal for inputting image data in a frame unit in a non-interlaced manner, and a first buffer for sequentially writing the image data input to the input terminal to the first buffer by substantially halving the data for one line by half. And writing the image data stored in the first buffer into the memory at the same speed as the writing speed of the first buffer writing means, and storing the image data for one frame in the memory. A memory writing unit, and a scanning direction in which the memory writing unit writes to the memory at the same speed as the writing speed of the memory writing unit. A second buffer writing means for reading image data from the memory by scanning in the reverse direction and writing the image data in the second buffer in units of lines thinned out by a factor of two; Output means for sequentially reading out image data in line units thinned out, interpolating the read out image data, inverting frame unit image data inputted to the input terminal, and outputting the inverted image data in an interlaced manner. An image data processing device is provided.

By thinning out the image data and storing it in the memory, the image input to the input terminal can be inverted / erected and non-interlaced / interlaced and output. The image data is substantially 1 in the horizontal direction.
/ 2 is decimated and stored in the memory. The memory does not need to have a small capacity and can be written or read at high speed.

[0030]

FIG. 1 is a block diagram of an image data processing apparatus according to a first embodiment of the present invention, and FIG. 2 is a signal timing chart of the apparatus of FIG. In the following description of the apparatus of FIG. 1, (a) to (i) show the timing chart of FIG.

The address generator 13 has an input address generator 13a and an output address generator 13b. The input address generator 13a receives the input vertical synchronizing signal V1.
By using (a) as a reset signal, a write address to the DRAM 11 is generated. The output address generator 13b
A read address from the DRAM 11 is generated using the output vertical synchronization signal V2 (h) as a reset signal.

The upright / inverted switching signal MD is a signal indicating whether the video camera shown in FIG. 6 is in the upright state or the inverted state. For example, the erect state (FIG. 6A,
(B)), the signal MD = 0, and in the inverted state (FIGS. 6C and 6D), the signal MD = 1. The signal MD may be generated based on a mechanical switch that operates when the casing of the video camera is rotated, or may be generated based on a switch operation performed by a photographer.

As described above with reference to FIG. 6, when the signal MD = 0 (erect state), the non-interlace signal NIL of the erect image is supplied from the video source, and the signal MD = 1 (inverted state). In the state (state), a non-interlace signal NIL of an inverted image is supplied from a video source.

When the signal MD = 0, the image data processing device simply performs non-interlace / interlace conversion, and when the signal MD = 1, performs non-interlace / interlace conversion, as well as inverted / erect conversion. . The address generator 13 generates two types of addresses according to the signal MD.

First, the case where the signal MD = 0, that is, the case where the video camera is in the upright state will be described.

Non-interlaced image data NIL (c) is transferred from a video source such as a CCD (not shown) to an input buffer memory (line memory) 10 at a predetermined transfer rate. The image data NIL is sequentially written in the input buffer memory 10 line by line in synchronization with the horizontal synchronization signal (b), and is temporarily stored (d). One line of image data of the input buffer memory 10 is written into the DRAM 11 via the bus 14 at the timing of the next horizontal synchronizing signal at a writing speed twice (or more) than the transfer speed for one line unit. (E). At this time, the write address is controlled by the input address generator 13a, and the image data is written to the DRAM 11 in the order of addresses.

The DRAM 11 is a high-speed write mode EDO (Extended Data Output).
t) DRAM with mode function or general-purpose DR
Synchronous DRAM that can be accessed faster than AM
Etc. are used. Although such a high-speed access DRAM is somewhat expensive compared to a general-purpose DRAM, the conventional V
The cost is much lower than when two RAMs or DRAMs are used.

The image data written to the DRAM 11 is read out via the bus 14 at the same speed as the double-speed writing speed during a period when writing to the DRAM 11 is not performed. The output address generator 13b reads the even line field (first field) asynchronously with the input address generator 13a (however, it may be synchronized) and then reads the odd line field (second field).
A read address is generated so as to read the data.

The input address generator 13a synchronizes with the input vertical synchronizing signal V1 (a) and outputs the output address generator 1a.
3b generates an address in synchronization with the output vertical synchronization signal V2 (h).

The input address generator 13a designates a write address to the DRAM 11 in a non-interlaced manner, and the output address generator 13b designates a D-address in an interlaced manner.
A read address from the RAM 11 is specified.

The image data read from the DRAM 11 is sequentially written into the output buffer memory (line memory) 12 line by line and temporarily stored (f).
The output buffer memory 12 sequentially outputs the held one line of image data and generates an interlace signal IL (g). At this time, the image data is read from the output buffer memory 12 at the same speed as the writing speed to the input buffer memory 10. The interlace signal IL is synchronized with the output vertical synchronizing signal V2 (h) and the output horizontal synchronizing signal (i), and is supplied to an interlaced display device (not shown) so that interlaced display can be performed normally. it can.

When the video camera is in the upright state (MD = 0) and when the video camera is in the inverted state (MD = 1), only the address generation method of the address generator 13 is different, and the others are the same.

FIG. 3A shows a DRAM in an upright state.
2 shows an address map of the first embodiment. As an example, 640 pixels × 48
A case where an image of line 0 is stored in the DRAM will be described.

First, a method of writing non-interlaced image data will be described. The image data is stored in DRAM address order. That is, the image data of the first line is stored in a memory cell having a row address of 0 (ROW = 0), and the image data of the 480th line is stored in a memory cell having a row address of 479 (ROW = 479). You. Further, the first pixel in one line is stored in a memory cell having a column address of 0, and the 640th pixel in one line is stored in a memory cell having a column address of 639. Non-interlaced image data of an erect image is stored in the DRAM in order of address.

When reading out image data, scanning is performed in an interlaced manner (every other row) in the direction of address order, and
By reading from the RAM, an erect image can be displayed in an interlaced manner.

FIG. 3B shows a DRAM in an inverted state.
2 shows an address map of the first embodiment. As an example, 640 pixels × 48
A case where an image of line 0 is stored in the DRAM will be described.

First, a method of writing non-interlaced image data will be described. The image data is in the order reverse to the address order of the DRAM (hereinafter referred to as the reverse address order)
Is stored in That is, the image data of the first line is
The row address is stored in the memory cell of address 479 (ROW = 479), and the image data of the 480th line is stored in the memory cell of row address 0 (ROW = 0). Further, the first pixel in one line is stored in a memory cell having a column address of 639, and the 640th pixel in one line is stored in a memory cell having a column address of 0.

The DRAM is supplied with image data of an inverted image in a non-interlaced manner. By writing the inverted image in the reverse address order, the erect image is stored in the DRAM. When reading image data, an erect image can be displayed in an interlaced manner by scanning in the interlaced manner in the address order direction and reading out from the DRAM, as in the case described above.

Although the write address to the DRAM is changed between the upright state (MD = 0) and the inverted state (MD = 1), the write address may be the same and the read address may be changed. In other words, in both the upright state and the inverted state, writing is performed by scanning in the direction of address in a non-interlaced manner. In the upright state, scanning may be performed in an interlaced manner in the direction of address order for reading, and in the inverted state, scanning may be performed in an interlaced manner in the direction of reverse address for reading.

In the inverted state, scanning is performed in an interlaced manner in the direction opposite to the scanning direction in which data is written to the DRAM.
By reading the image data from the, the inverted image can be converted into an erect image.

In the above-described first embodiment, a DRAM capable of high-speed access is used. In the second embodiment described below with reference to FIGS. 4 and 5, one general-purpose DRAM is used. To perform inverted / erect conversion and non-interlace / interlace conversion.

FIG. 4 is a block diagram of an image data processing apparatus according to a second embodiment of the present invention, and FIG. 5 is a signal timing chart of the apparatus of FIG. In this embodiment, the image to be interlaced is an image obtained by thinning out the image data from the video source, which is effective when the display image does not require a particularly high resolution. In the following description of the apparatus of FIG. 4, (a) to (f) show the timing chart of FIG.

The address generator 24 has an input address generator 24a and an output address generator 24b, and changes the address generation method according to the erect / inverted switching signal MD. When the signal MD = 0, the inverted / erect conversion is not performed. When the signal MD = 1, the inverted / erect conversion is performed.

Non-interlaced image data NIL (b)
Are transferred from a video source such as a CCD (not shown) to the thinning circuit 21 at a predetermined transfer rate in synchronization with the input horizontal synchronization signal (a). The image data NIL is reduced by 1 in the horizontal and vertical directions by the thinning circuit 21.
The data is decimated by / 2 and written to the input buffer memory 20. The thinning method at this time may be a simple extraction method, a filtering process, or the like. Vertical thinning is performed by inputting one line of data for every two lines into the input buffer memory 20.
This is done by writing to.

The input buffer memory 20 temporarily holds half the image data of one line (c). The image data from the video source is decimated by 水平 in the horizontal line and で も in the vertical direction, and stored in the input buffer memory 20.

Next, the image data of one half of one line of the input buffer memory 20 is transferred via the bus 26 at the timing of the next horizontal synchronizing signal at the same speed as the writing speed to the input buffer memory 20. (D).

At this time, the write address is controlled by the input address generator 24a, and the image data is written to the DRAM 11. When the signal MD = 0, FIG.
As in (A), image data is written in address order. When the signal MD = 1, image data is written in reverse address order in the same manner as in FIG. However, since the image data is thinned out, the amount of the image data is 1 /
It becomes 4.

Since the DRAM 22 stores の of the original image data amount supplied from the video source for one screen, the DRAM 22 has the memory capacity of the first embodiment (FIG. 1). ), Which is about 1/4 less than that of the DRAM 11.

As the DRAM 22, an inexpensive general-purpose DRAM that does not require a high-speed write mode can be used. D
The image data written to the RAM 22 is read out via the bus 26 at the same speed as the writing speed during a period in which writing to the DRAM is not performed, and is temporarily stored in the output buffer memory 23 line by line. (E).

The output buffer memory 23 stores half the image data of one line. After that, the image data is read from the output buffer memory 23, and the interpolation circuit 25 interpolates the image data, and outputs twice the amount of image data to the display device. With this interpolation,
The amount of image data in the horizontal direction can be restored. As the interpolation method, it is possible to copy the immediately preceding data, perform a filtering process, or the like.

In both the first field and the second field, by reading out the image data of all the lines stored in the DRAM 22, vertical interpolation is performed to restore the vertical image data amount. Can be. The image data of the first field and the image data of the second field are output as the same data.

When data is read from the DRAM 22, an interlace signal is generated by generating a read address asynchronously with writing (however, it may be synchronized) as in the first embodiment (FIG. 1). IL (e) is obtained.

The image data IL is read from the output buffer memory 23 at the same speed as the writing speed to the input buffer memory 20 and output to an interlaced display device (not shown), whereby the erect image can be interlaced normally. Can be displayed in the format.

Note that, also in the second embodiment, the signal MD
Instead of changing the write address, the read address may be changed with the same write address.

Also, the case where the thinning circuit 21 thins out each half in the horizontal direction and the vertical direction has been described. However, even if thinning is performed only in the horizontal direction, the inverted / erect conversion and the non-interlace / interlace Conversion can be performed. In that case, the DRAM has 1
/ 2 image data is written and interpolated only in the horizontal direction and output.

According to the first or second embodiment, the inverted / erect conversion can be performed using a general-purpose CCD and display device without changing the driving method of the CCD or display device.
An erect image can be displayed whether the video camera is in the upright state or the inverted state. By using a general-purpose CCD and display device, the cost can be reduced.

Further, non-interlace / interlace conversion can be performed using a small-capacity memory without using a VRAM. The cost can be reduced by using a small-capacity memory instead of the VRAM.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0069]

As described above, according to the present invention,
By using the memory in the high-speed access mode, an image input to the input terminal can be output at low cost after inverted / erect conversion and non-interlace / interlace conversion. For example, even when the video camera is in an inverted state, an upright image can be displayed or photographed in an interlaced manner.

Further, by thinning out the image data and storing it in the memory, the image input to the input terminal can be output at low cost after inverted / erect conversion and non-interlace / interlace conversion. . The memory does not need to have a small capacity and can be written or read at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image data processing device according to a first embodiment of the present invention.

FIG. 2 is a signal timing chart of the device of FIG.

FIG. 3A is a diagram illustrating an address map of a DRAM in an upright state, and FIG. 3B is a diagram illustrating an address map of a DRAM in an inverted state.

FIG. 4 is a block diagram of an image data processing device according to a second embodiment of the present invention.

FIG. 5 is a signal timing chart of the device of FIG. 4;

6 (A) is a front view of the video camera in an upright state, FIG. 6 (B) is a side view thereof, and FIG. 6 (C) is a front view of the video camera in an inverted state, and FIG. D) is a side view thereof.

FIG. 7 is a block diagram of a conventional non-interlace / interlace conversion device.

[Explanation of symbols]

 10, 20 Input buffer memory 11, 22 DRAM 13, 24 Address generator 12, 23 Output buffer memory 14, 26 Bus 21 1/2 decimation circuit 25 Double interpolation circuit 40 Video camera 41, 42 Housing 43 Rotation axis 44 Liquid crystal Display 46 Lens 50 Video source 51 VRAM 52 Display 53, 54 DRAM 55, 56 Switch

Claims (13)

[Claims] 1. A first and a second buffer, each of which can buffer one line of image data; a memory, which can store one frame of image data; An input terminal for inputting in an interlaced manner, a first buffer writing unit for sequentially writing image data input to the input terminal to the first buffer line by line, and a writing speed of the first buffer writing unit. Memory writing means for writing image data stored in the first buffer to the memory at twice or more speed and storing image data for one frame in the memory; and a writing speed of the memory writing means. At the same speed,
A second buffer writing unit that reads in image data from the memory by scanning in an interlaced manner in a direction opposite to a scanning direction in which the memory writing unit writes into the memory, and writes the image data to the second buffer in line units; Output means for sequentially reading out image data in line units from the second buffer, and inverting the image data in frame units input to the input terminal and outputting the inverted data in an interlaced manner. 2. The memory writing means is means for writing pixel data to the memory by scanning in the direction opposite to the address order of the memory, and wherein the second buffer writing means comprises an address of the memory. 2. A means for reading out pixel data from said memory by scanning in a forward direction.
An image data processing device as described in the above. 3. An instructing means for instructing one of an upright mode and an inverted mode, wherein the second buffer writing means writes the data into the memory when the inverted mode is instructed. The image data is read from the memory by scanning in a direction opposite to the scanning direction, and when the erecting mode is instructed, the memory writing means scans in the same direction as the scanning direction in which the image data is written into the memory, and reads the image data from the memory. Reading means, when the inverted mode is instructed, the output means inverts and outputs the frame-based image data input to the input terminal, and when the erect mode is instructed, inputs the input data to the input terminal 2. The image data processing apparatus according to claim 1, wherein the image data in the frame unit is erected and output. 4. The memory writing means for writing pixel data in the memory by scanning in the direction opposite to the address order of the memory when the inverted mode is instructed, wherein the second buffer writing is performed. 4. The image data processing apparatus according to claim 3, wherein said means is means for reading out pixel data from said memory by scanning in an address order direction of said memory when an inverted mode is designated. 5. The second buffer writing means, when reading image data from the memory in an interlaced manner, reads out even-numbered line data and odd-numbered line data of one frame of image data. 5. The image data processing apparatus according to claim 1, wherein the steps are alternately performed in synchronization with a vertical synchronization signal. 6. A first and a second buffer, each capable of buffering half the image data of one line, a memory capable of storing image data, and a non-frame image data. An input terminal for inputting in an interlaced manner, a first buffer writing means for substantially thinning out image data input to the input terminal by ラ イ ン for one line and sequentially writing the image data in the first buffer; Memory writing means for writing image data stored in the first buffer to the memory at the same speed as the writing speed of the first buffer writing means, and storing one frame of image data in the memory; At the same speed as the writing speed of the means,
A second buffer writing unit that reads image data from the memory by scanning in a direction opposite to a scanning direction in which the memory writing unit writes data in the memory, and writes the image data in the second buffer in line units thinned out by half The image data is sequentially read from the second buffer in line units thinned by half, the read image data is interpolated, and the image data in frame units input to the input terminal is inverted. An image data processing device having output means for outputting in an interlaced mode. 7. The first buffer writing means, wherein the image data input to the input terminal is substantially decimated to に つ い て for each line, and sequentially written to the first buffer every other line. The image data processing device according to claim 6, wherein 8. The image data processing apparatus according to claim 7, wherein said output means outputs the same data for the image data of the first field and the image data of the second field when outputting the image data in the interlaced mode. . 9. The memory writing means is means for writing pixel data to the memory by scanning in the direction opposite to the address order of the memory, and wherein the second buffer writing means is an address of the memory. 7. A means for reading pixel data from said memory by scanning in a forward direction.
An image data processing device according to any one of claims 1 to 8. 10. An instructing unit for instructing one of an erect mode and an inverted mode, wherein the second buffer writing unit writes the memory into the memory when the inverted mode is instructed. The image data is read from the memory by scanning in a direction opposite to the scanning direction, and when the erecting mode is instructed, the memory writing means scans in the same direction as the scanning direction in which the image data is written into the memory, and reads the image data from the memory. Reading means, when the inverted mode is instructed, the output means inverts and outputs the frame-based image data input to the input terminal, and when the erect mode is instructed, inputs the input data to the input terminal 9. The image data processing device according to claim 6, wherein the image data processing device is means for erecting and outputting the image data in frame units. 11. The memory writing means for writing pixel data to the memory by scanning in the direction opposite to the address order of the memory when the inverted mode is instructed, wherein the second buffer writing means is provided. 2. The means for reading pixel data from the memory by scanning in the address order direction of the memory when the inverted mode is instructed.
0. An image data processing apparatus according to claim 1. 12. A step of inputting frame-based image data in a non-interlaced manner; a step of sequentially writing the input image data in a line-by-line manner to a first buffer; Writing the image data stored in the first buffer into the memory at a speed of, and storing the image data for one frame in the memory; and writing the image data into the memory at the same speed as the writing speed into the memory Scanning image data from the memory by scanning in an interlaced manner in a direction opposite to the scanning direction and writing the image data to the second buffer line by line; and sequentially reading the image data line by line from the second buffer; Inverting the input frame-based image data and outputting the inverted data in an interlaced manner. Method. 13. A step of inputting image data in a frame unit in a non-interlaced manner; a step of substantially thinning out the input image data by half for one line and sequentially writing the input image data in a first buffer; Writing the image data stored in the first buffer into the memory at the same speed as the writing speed, and storing one frame of image data in the memory; and writing the image data at the same speed as the writing speed into the memory. Scanning image data from the memory by scanning in a direction opposite to the scanning direction in which the data is written to the memory, and writing the image data to a second buffer in units of decimated lines; / 2, sequentially reads out image data in units of lines thinned out to / 2, interpolates the read image data, and converts the input image data in frame units. Image data processing method comprising the step of outputting an interlaced manner by standing.