JPH1022449A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the system cost, increase the degree of freedom in wiring design within an interconnecting network, improve the signal transmission property, and improve the efficiency of interprocessor data transfer, by forming a processor portion and an interconnecting network portion using separate semiconductor chips, respectively, and unifying these portions in a COC structure. SOLUTION: A semiconductor device has a COC structure in which a PE chip 11 on the upper surface and an interconnecting network forming chip 13 on the lower surface are bonded, with active surfaces thereof facing each other. The junction between-the chips 11 and 13 is realized by connecting area electrode pads 16, 18 formed in the PE chip 11 and the interconnecting network forming chip 13 by a bump 17. Thus, the PE including a micro-processor and DSP, which is a constituent element, may be produced in the minimum possible size. Also, the latest process enables designing which emphasizes performance, thus enabling improvement in degree of freedom in designing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of microprocessors or DSPs are operated in parallel, and more particularly to a method of configuring a system in which an interconnection network is formed between a plurality of processors. Things.

[0002]

2. Description of the Related Art In recent years, with the increasing speed and function of various system devices, various parallel processing technologies have been introduced together with the improvement of the processing speed of a single semiconductor device, and approaches to increase the total performance of the system have been actively performed. ing. This is, for example, compression / decompression of image data.
Complex and high-speed processing is performed by multiple processors
The total processing speed is improved by distributing elements (PE) and operating processors having standard processing performance in parallel.

A conventional multiprocessor configuration will be described below with reference to the drawings. FIG. 5 shows a form of a general tightly-coupled interconnection network, and is a block diagram showing a multiprocessor system. In FIG. 5, 31 is a processor element P
E and 32 are interconnection networks, and 33 is a control unit of PE. The interconnection network 32 includes a crossbar type, a mesh type, a hypercube type, and an ADENA type (hypercross type).
And the like.

Next, FIG. 6 shows the four PEs shown in FIG.
FIG. 2 is a block diagram of a crossbar interconnection network between them. In FIG. 6, 34 indicates a crossbar switch, and 35 indicates a crossbar wiring. As shown in FIG. 6, four PEs 31 are connected so as to cross each other, and a crossbar switch 34 is provided at each connection point. A portion surrounded by a dotted line in the figure indicates an interconnection network. The number of crossbar wires 35 is determined by the bandwidth of data transfer and the frequency of signal transmission. For example, the data transfer rate is improved by increasing the number of bits to 8, 16, 32, 64, and so on, but this generally leads to an increase in mounting cost and an increase in mounting scale.

An example of a hardware implementation of the crossbar-type PE configuration shown in FIG. 6 will be described below. FIG. 7 is a plan view of a conventional semiconductor device having a crossbar-type interconnection network, showing the configuration of the most orthodox form of individual element chips.

In FIG. 7, 36 is a packaged PE, 37 is a packaged crossbar switch, 38
Is an interconnection network wiring formed in the circuit board, and 39 is a circuit board. In this case, each chip is individually packaged and mounted on a circuit board to form a system. The semiconductor device shown in FIG.
It shows an example of a package.

On the other hand, FIG. 8 shows an example in which all the components are formed in a one-chip LSI, contrary to the QFP package shown in FIG. FIG. 8 is a plan view showing a functional block layout in a chip of a semiconductor device having a conventional crossbar interconnection network. In FIG.
40 is a PE block, 41 is a block of an interconnection network including a crossbar switch, 42 is an electrode pad arranged around the chip, and 43 is a semiconductor chip. In this example, all components such as a PE, a crossbar switch, and interconnect wiring are integrated on one chip. For example, 0.35μ
A tightly-coupled network of a plurality of PEs can be realized on a single chip by a state-of-the-art miniaturization process such as m, a multilayer wiring technique of three, four or more layers. Specifically, there is a configuration in which four floating operation DSP cores are crossbar-coupled. The chip further includes a RISC processor core for controlling parallel processing.

[0008]

However, in the conventional structure shown in FIG. 7, since each chip is individually packaged and mounted on a circuit board, a signal transmission delay between the LSI chips occurs. For example, when the operation speed is 60 MHz or more, problems such as signal reflection, noise, and crosstalk occur.

Further, in the example of FIG. 8, since all the elements are integrated on one chip, the physical size is advantageous as compared with the example of FIG. Also, because it is formed in one chip,
Higher speed operation is possible. However, since the scale of the integrated circuit increases, the chip size increases even when a finer manufacturing process is used. For example, a semiconductor device in which the above-mentioned four floating operation DSP cores are crossbar-coupled has a very large size of 18 mm square. This is because the crossbar connection network occupies a considerable area.

[0010] An increase in the chip size, ie, an increase in chip cost, poses a serious problem in application to actual applications. In addition, it is necessary to prepare a design tool for integrating the interconnection network with general-purpose logic into one chip.

Further, when it is necessary to change the form of the interconnection network between the PEs depending on the application, it is necessary to implement an LSI each time, which requires a development man-hour and a development period.

Therefore, the present invention is to improve the signal transmission characteristics and the efficiency of data transfer between processors by minimizing the system cost and increasing the degree of freedom in wiring design in the interconnection network. An object of the present invention is to provide a semiconductor device capable of improving design flexibility and design efficiency.

[0013]

To achieve the above object, a semiconductor device according to the present invention has a structure in which electrode pads of a semiconductor chip are electrically connected to each other such that active surfaces of a plurality of semiconductor chips face each other. , One of the opposing semiconductor chips is a plurality of microprocessors or a controller LSI for controlling data transfer between the microprocessors, and the other is a mutual coupling for realizing a data transfer network between the microprocessors. It is configured to be a chip on which a net is formed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the above-described 4PE crossbar network will be described as an example.

(Embodiment 1) FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. In FIG. 1, 11 is a PE chip, 12 is a PE block, 13 is a chip for forming an interconnection network, 14 is an area for forming an interconnection network, 15 is a crossbar switch circuit, and 16 is an upper surface P
Reference numeral 17 denotes an area electrode pad of the E chip, reference numeral 17 denotes a bump, reference numeral 18 denotes an area electrode pad of the lower surface interconnection network forming chip, and reference numeral 19 denotes a peripheral electrode pad of the lower surface chip. As shown in FIG. 1, the semiconductor device according to the present embodiment has a structure in which an upper surface chip and a lower surface chip are bonded with their active surfaces facing each other. This is COC
(Chip-on-chip) structure. In the present embodiment,
The PE chip 11 is arranged on the upper surface, and the interconnection network forming chip 13 is arranged on the lower surface. For bonding between chips, top chip,
Area electrode pads 16, 18 formed in the lower chip
Are connected by bumps 17. The bonding using the above-described bumps can be performed by using, for example, an MBB (micro-bump bonding) technique, and in this case, fine connection with a pitch of 30 μm or less is possible.

FIG. 2 is a plan view of the semiconductor device having the COC structure shown in FIG. 1 as viewed from above. The interconnection network 1 formed in the lower chip 13 in FIG.
The four PE chips 11 are arranged on and electrically connected to each other.

In the interconnection network 14, four crossbar switches 15 as controllers for controlling data transfer between PEs, interconnections between these crossbar switches, and connections to the PE chip 11 on the upper surface are provided. An area electrode pad 18 for performing the operation is formed. FIG. 3 shows the lower chip 1 without the upper PE chip 11 mounted thereon.
FIG. 3 is a plan view showing No. 3; An electrode pad 18 is formed on the upper surface PE chip 11 at a position corresponding to the area electrode pad 16. In this configuration, a portion surrounded by a dotted line in FIG. 6 is cut out and formed in the lower surface chip. That is, the PE and the interconnection network are formed by separate chips, and integrated by the COC bonding technology.

As a result, it is possible to fabricate the PE, which is a component, such as a microprocessor or a DSP, as small as an individual chip. In addition, it is possible to design with emphasis on performance by the latest process, and it is possible to improve design flexibility. For example, the total cost of semiconductor devices can be reduced by making the upper surface chip by the latest 0.35 μm process and the lower surface interconnection network forming chip by the older generation, for example, 0.5 or 0.8 μm process. It is.

Further, the PE chip is formed with standard specifications, and the form of the interconnection network can be changed according to the requirements of the system. That is, by changing only the lower surface chip, a network configuration such as a mesh type or a hypercube type can be adopted in addition to the crossbar connection described above. At this time, unlike the one-chip process, it is possible to respond by changing only the interconnection network chip, so that it is possible to greatly reduce the design and development period and reduce the development cost.

Embodiment 2 Hereinafter, a semiconductor device according to another embodiment of the present invention will be described. FIG.
Shows a cross-sectional view of the semiconductor device in the present embodiment.

In the embodiment shown in FIG. 4, a plurality of PE blocks 12 are formed in one chip on the upper surface.
The difference from the semiconductor device in the embodiment shown in FIG. 1 described above is the number of PEs per chip. This can be optimized according to the circuit scale and the degree of integration (process).

Note that the crossbar switch in the interconnection network in the above embodiment is formed as a separate chip,
It can also be provided on the upper surface of the structure.

[0023]

As described above, the semiconductor device of the present invention can be used in a multiprocessor system in which a plurality of microprocessors or DSPs are tightly coupled.
The processor section and the interconnection network section are formed of separate semiconductor chips, respectively, and are integrated by a COC structure. For this reason, it is possible to apply the optimum process to each of the processor unit and the interconnection network, and it is possible to minimize the system cost.

Further, since the degree of freedom in wiring design in the interconnection network can be increased, the signal transmission characteristics can be improved and the efficiency of data transfer between processors can be improved by optimizing the wiring width and wiring thickness. . In addition, it is possible to use a common processor unit and construct a system by changing only the interconnection network. This improves design flexibility, design efficiency, and increases the cost performance of the total system. The effect can be produced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a plan view of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a sectional view of a semiconductor device according to an embodiment of the present invention;

FIG. 5 is a block diagram showing a system having a multiprocessor configuration.

FIG. 6 is a block diagram showing a crossbar interconnection network;

FIG. 7 is a plan view showing a conventional semiconductor device having a crossbar interconnection network.

FIG. 8 is a plan view showing a conventional semiconductor device having a crossbar interconnection network.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 PE chip 12 PE block 13 Interconnection network formation chip 14 Interconnection network formation area 15 Crossbar switch circuit 16 Upper surface chip area electrode pad 17 Bump 18 Lower surface chip area electrode pad 19 Lower surface chip peripheral pad 31 Processor element (PE) 32 Interconnection Network 33 PE control unit 34 Crossbar switch (logically) 35 Crossbar wiring 36 PE package component 37 Crossbar switch package product 38 Interconnection network interconnection 39 Circuit board 40 In-chip PE block 41 Interconnection network block 42 Peripheral electrode pad 43 Multiprocessor semiconductor Chips

Claims (3)

[Claims] 1. A semiconductor device having a structure in which active surfaces of a plurality of semiconductor chips face each other and electrode pads of the plurality of semiconductor chips are electrically connected to each other. A semiconductor device having a microprocessor, wherein the other semiconductor chip facing the semiconductor chip having the microprocessor has an interconnection network for performing a data transfer network between the microprocessors. 2. The semiconductor device according to claim 1, wherein said semiconductor chip having a microprocessor has a controller for controlling data transfer between said microprocessors.
13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein said semiconductor chip having an interconnection network for performing a data transfer network between microprocessors has a controller for controlling data transfer between said microprocessors. .