JPH10222123A - Pdp display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for displaying color developments satisfactorily in a plasma display panel(PDP) performing preliminary dischargings every subfield performing gradation display. SOLUTION: A digital video signal S1 equivalent to one field is stored in a field memory 9 and is divided into subfields SF1, SF2,...SF8 of the number of binary digits of the digital video signal and gradation display is performed to a PDP4 by driving an X driver and a Y1 driver with a PDP driving circuit 1. Preliminary dischargings are performed at the first parts of respective subfields SF1, SF2,...SF8. A digit detecting circuit 7 calculates logical sums of RGB three-primary colors every digit of the digital video signal S1 and detects whether signals of respective digits all become zero or not by its outputs. Then, preliminary dischargings of subfields corresponding to digits in which the digital video signal does not all exist are made so as not to be preformed by inputting the output of the digit detecting circuit 7 to a discharge sequence control circuit 8 and controlling the PDP driving circuit 1 with the output of the circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PDP (Plasma Display Panel) display device capable of displaying gradations of television images or the like and having good color development.

[0002]

2. Description of the Related Art In a gray scale display of a video signal of a television or the like in a PDP, one signal is divided into subfields corresponding to each digit of a binary number of a video signal by using the same signal as a digital video signal, and each digit is represented by each digit. A subfield method in which light is emitted with weighted luminance is generally used. If preliminary discharge is performed for each subfield prior to the light emission of each pixel, the discharge start time of each pixel is shortened, the variation is reduced, and gradation display is facilitated. However, every time the preliminary discharge is performed, the entire screen emits white light. For example, when an 8-bit video signal is displayed, the entire screen emits white light eight times in each field period, and the display color of the image is changed. This not only lowers the degree of saturation and deteriorates color development, but also causes a reduction in contrast ratio.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide a technique for displaying a color with good color by a PDP which performs a preliminary discharge for each subfield for performing a gradation display. I do.

[0004]

The presence or absence of a signal of each digit of the same video signal is determined for each range in which the preliminary discharge is performed for each subfield, and the preliminary discharge is not performed in a range where there are no signals in the same digit. In this way, the frequency of the preliminary discharge is reduced.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One of the digital video signals to be displayed
In a PDP display device, a field is divided into subfields corresponding to each digit of a binary number of the video signal, and a preliminary discharge is performed for each subfield, and then a discharge corresponding to each digit is performed to perform gradation display. The signal of each digit of the same video signal is determined for each range in which the pre-discharge is performed for each subfield, and the pre-discharge is not performed in a range where no signal is present in all the same digits.

The determination of the signal of each digit of the video signal is performed on the entire screen for each subfield, so that the preliminary discharge of the entire screen of the subfield in which the digit is completely absent is not performed.

For each digit, there is provided an AND circuit of the video signal and its clock signal and a flip-flop circuit which is set by the output of the same circuit and reset by a vertical synchronizing signal, and a latch circuit which latches the output for one field. Then, it is detected whether or not all the video signals of all the screens in each subfield have no signal.

The determination of the signal of each digit of the video signal is performed for each line in each subfield, and the preliminary discharge of the line without any signal is not performed in each subfield.

A flip-flop circuit is set for each digit at the output of the AND circuit for the video signal and its clock signal and reset by a horizontal synchronizing signal, and a memory circuit for holding the output for each line is provided. , It is detected whether or not the video signal of the line is completely absent for each digit.

[0010]

1 is a (A) schematic block diagram and (B) a schematic timing diagram of a subfield system of an embodiment of a PDP display device according to the present invention. An X driver and a Y1 driver are driven by a PDP driving circuit 1 with a digital video signal S1 of, for example, an 8-bit configuration composed of three primary colors of RGB.
A gradation is displayed on the PDP 4. In this gradation display, the video signal for one field of the video signal is stored in the field memory 9 and the subfield S of the binary digit number of the digital video signal is stored.
F8 is divided into F1, SF2,... SF8, and discharge is performed a number of times in proportion to the weight of each digit to emit light from the PDP. A preliminary discharge is performed in the first part of each of the subfields SF1, SF2,... To facilitate writing of the video signal to each pixel for gradation display, thereby reducing discharge delay and variation in discharge start. The preliminary discharge is performed by applying a discharge voltage to the Y1 driver and the Y2 driver, and between the horizontal electrodes LY11, LY12,... Connected to the Y1 driver, and the common horizontal electrode Y2 connected to the Y2 driver. After the preliminary discharge, a voltage is sequentially applied to each of the horizontal electrodes LY1, LY2,.
Each pixel is selected by a voltage corresponding to a video signal from the X driver, and writing of pilot light is performed. After that, discharge is performed by the number of weights of the digit by the sustain voltage by the Y1 driver and the Y2 driver to perform gradation display.

In the digit detecting circuit 7, the digital video signal S
The logical OR of the three primary colors RGB is obtained for each digit of 1 and whether or not all the signals of each digit (each subfield) have no signal is detected based on the output. The output of the digit detection circuit 7 is input to the discharge sequence control circuit 8, which controls the PDP drive circuit 1 so that the pre-discharge of the subfield corresponding to the digit where no video signal is present is not performed. .

FIG. 2 shows an embodiment of a digit detection circuit for a digital video signal of a PDP display device according to the present invention. The logical product circuit 21 obtains the logical product of the logical sum signal S21 of the video signals of the three primary colors RGB and the clock signal S22 of the same video signal for each digit, sets the flip-flop circuit 22, and resets it with the vertical synchronization signal S23. The output S24 is
If there is even one pixel in that digit, it becomes 1, and the negation means that the video signal represents a subfield corresponding to the digit without any signal. In order to hold this signal for one field, it is latched by the latch circuit 23 with the vertical synchronizing signal S23. Using the output S25 of the latch circuit 23,
As described above, the discharge control circuit 8 or the like prevents the preliminary discharge of the entire screen of the subfield corresponding to the digit where no video signal is present.

FIG. 3 shows another embodiment of the digit detection circuit of the digital video signal of the PDP display device according to the present invention. Similarly to the above, the logical product circuit 31 calculates the logical product of the logical sum signal S21 of the RGB three primary color video signals and the clock signal S22 of the same video signal for each digit, and
By setting 2 and resetting with the horizontal synchronizing signal S25, an output signal S34 which becomes 1 if at least one pixel is present at that digit of the line is obtained. The output signal S34 is stored in the memory 33 for one field for each line, and
By using the output S35 of No. 3 as described above, the discharge control circuit 8 and the like do not perform the preliminary discharge of the line corresponding to the digit where no video signal is present. The write address of the memory 33 is generated by, for example, a counter 34 that counts the horizontal synchronization signal S25 during the vertical synchronization signal S23.

[0014]

According to the present invention, the presence or absence of a signal of each digit of the same video signal is determined for each sub-field in which pre-discharge is to be performed. By reducing the frequency of discharge, the frequency of white light emission is reduced. Therefore, the problem that white emission due to the pre-discharge reduces the degree of saturation of the display color of an image and deteriorates the color development is reduced, and the display color of the PDP is improved. In addition, the contrast ratio of the display is improved.

[Brief description of the drawings]

1A is a schematic block diagram of an embodiment of a PDP display device according to the present invention, and FIG. 1B is a schematic timing diagram of a subfield method.

FIG. 2 is an embodiment of a digit detection circuit of a digital video signal of a PDP display device according to the present invention.

FIG. 3 is another embodiment of a digit detection circuit of a digital video signal of a PDP display device according to the present invention.

[Explanation of symbols]

 S1 Digital video signal 1 PDP drive circuit 2 X driver 3 Y1 driver 4 PDP 5 Y2 driver 7 digit detection circuit 8 Discharge sequence control circuit SF1, SF2,... Subfield S21 OR signal of video signal S22 Clock signal S23 Vertical video signal Reference Signs List 21 AND circuit 22 Flip-flop circuit 23 Latch circuit S25 Horizontal synchronization signal 31 AND circuit 32 Flip-flop circuit 33 Memory 34 Counter

Claims (5)

[Claims] 1. A field of a digital video signal to be displayed is divided into subfields corresponding to each digit of a binary number of the video signal, and a preliminary discharge is performed for each subfield, and then a discharge corresponding to each digit is performed. PDP that performs gradation display
(Plasma display panel) In the display device, the presence or absence of a signal of each digit of the same video signal is determined for each range in which the preliminary discharge is performed for each subfield, and the preliminary discharge is not performed in a range where there are no signals in the same digit. A PDP display device, characterized in that: 2. The method according to claim 1, wherein the determination of the presence or absence of a signal of each digit of the video signal is performed for every screen of each subfield, and the preliminary discharge is not performed in the subfield where all the digits have no signal. The PDP display device according to claim 1. 3. A flip-flop circuit which is set by an AND circuit of the video signal and its clock signal and reset by a vertical synchronizing signal and a latch circuit which latches the output for one field for each digit. 3. The PDP display device according to claim 2, wherein the PDP display device is provided to detect whether or not all video signals of the entire screen are absent for each digit. 4. The determination of the presence or absence of a signal of each digit of the video signal is performed for each line in each subfield, and the preliminary discharge of a line in which no signal is present in all the digits of each subfield is performed. 2. The method according to claim 1, wherein
DP display device. 5. An AND circuit for the video signal and its clock signal, and a flip-flop circuit which is set by an output of the circuit and reset by a horizontal synchronizing signal, and a memory circuit which holds the output for each line is provided for each digit. 5. The PDP display device according to claim 4, wherein the PDP display device is provided to detect whether or not all the video signals of the line have no signal for each digit.