JPH10214250A - マイクロプロセッサホストモジュール - Google Patents

マイクロプロセッサホストモジュール

Info

Publication number
JPH10214250A
JPH10214250A JP9301181A JP30118197A JPH10214250A JP H10214250 A JPH10214250 A JP H10214250A JP 9301181 A JP9301181 A JP 9301181A JP 30118197 A JP30118197 A JP 30118197A JP H10214250 A JPH10214250 A JP H10214250A
Authority
JP
Japan
Prior art keywords
bus
module
configuration
data
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9301181A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10214250A5 (cg-RX-API-DMAC7.html
Inventor
Yuen Chan Tai
− ユエン チャン タイ
D Kruger Steven
ディー．クルーガー スチーブン
H Shell Johnathan
エィチ．シェル ジョナサン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH10214250A publication Critical patent/JPH10214250A/ja
Publication of JPH10214250A5 publication Critical patent/JPH10214250A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Automotive Seat Belt Assembly (AREA)
JP9301181A 1996-10-31 1997-10-31 マイクロプロセッサホストモジュール Pending JPH10214250A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3026096P 1996-10-31 1996-10-31
US030260 1996-10-31

Publications (2)

Publication Number Publication Date
JPH10214250A true JPH10214250A (ja) 1998-08-11
JPH10214250A5 JPH10214250A5 (cg-RX-API-DMAC7.html) 2005-07-07

Family

ID=21853337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9301181A Pending JPH10214250A (ja) 1996-10-31 1997-10-31 マイクロプロセッサホストモジュール

Country Status (4)

Country Link
US (1) US6085269A (cg-RX-API-DMAC7.html)
EP (1) EP0859320B1 (cg-RX-API-DMAC7.html)
JP (1) JPH10214250A (cg-RX-API-DMAC7.html)
DE (1) DE69721474T2 (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7788420B2 (en) * 2005-09-22 2010-08-31 Lsi Corporation Address buffer mode switching for varying request sizes

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US6134622A (en) * 1995-12-27 2000-10-17 Intel Corporation Dual mode bus bridge for computer system
US5857086A (en) * 1997-05-13 1999-01-05 Compaq Computer Corp. Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits
WO1999021127A1 (fr) * 1997-10-17 1999-04-29 I-O Data Device Inc. Support sous forme de carte et carte pour ordinateur personnel
US6167476A (en) * 1998-09-24 2000-12-26 Compaq Computer Corporation Apparatus, method and system for accelerated graphics port bus bridges
US6249831B1 (en) * 1999-01-29 2001-06-19 Adaptec, Inc. High speed RAID cache controller using accelerated graphics port
JP3895071B2 (ja) * 1999-03-12 2007-03-22 インターナショナル・ビジネス・マシーンズ・コーポレーション バス・ブリッジ回路、情報処理システム、及びカードバス・コントローラ
US6535939B1 (en) 1999-11-09 2003-03-18 International Business Machines Corporation Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations
US6581115B1 (en) * 1999-11-09 2003-06-17 International Business Machines Corporation Data processing system with configurable memory bus and scalability ports
US6724390B1 (en) * 1999-12-29 2004-04-20 Intel Corporation Allocating memory
US7107383B1 (en) * 2000-05-03 2006-09-12 Broadcom Corporation Method and system for multi-channel transfer of data and control information
US6789154B1 (en) * 2000-05-26 2004-09-07 Ati International, Srl Apparatus and method for transmitting data
US7162554B1 (en) * 2001-07-11 2007-01-09 Advanced Micro Devices, Inc. Method and apparatus for configuring a peripheral bus
WO2004105278A1 (en) * 2003-05-20 2004-12-02 Philips Intellectual Property & Standards Gmbh Time-triggered communication system and method for the synchronization of a dual-channel network
US8775112B2 (en) 2003-09-15 2014-07-08 Nvidia Corporation System and method for increasing die yield
US8732644B1 (en) 2003-09-15 2014-05-20 Nvidia Corporation Micro electro mechanical switch system and method for testing and configuring semiconductor functional circuits
US8775997B2 (en) 2003-09-15 2014-07-08 Nvidia Corporation System and method for testing and configuring semiconductor functional circuits
US8711161B1 (en) 2003-12-18 2014-04-29 Nvidia Corporation Functional component compensation reconfiguration system and method
US8723231B1 (en) * 2004-09-15 2014-05-13 Nvidia Corporation Semiconductor die micro electro-mechanical switch management system and method
US8711156B1 (en) 2004-09-30 2014-04-29 Nvidia Corporation Method and system for remapping processing elements in a pipeline of a graphics processing unit
US7483422B2 (en) * 2005-02-10 2009-01-27 International Business Machines Corporation Data processing system, method and interconnect fabric for selective link information allocation in a data processing system
US8021193B1 (en) * 2005-04-25 2011-09-20 Nvidia Corporation Controlled impedance display adapter
US7793029B1 (en) 2005-05-17 2010-09-07 Nvidia Corporation Translation device apparatus for configuring printed circuit board connectors
US8412872B1 (en) * 2005-12-12 2013-04-02 Nvidia Corporation Configurable GPU and method for graphics processing using a configurable GPU
US8417838B2 (en) * 2005-12-12 2013-04-09 Nvidia Corporation System and method for configurable digital communication
US8724483B2 (en) * 2007-10-22 2014-05-13 Nvidia Corporation Loopback configuration for bi-directional interfaces
US8687639B2 (en) * 2009-06-04 2014-04-01 Nvidia Corporation Method and system for ordering posted packets and non-posted packets transfer
US9176909B2 (en) 2009-12-11 2015-11-03 Nvidia Corporation Aggregating unoccupied PCI-e links to provide greater bandwidth
US9331869B2 (en) * 2010-03-04 2016-05-03 Nvidia Corporation Input/output request packet handling techniques by a device specific kernel mode driver
US9330031B2 (en) 2011-12-09 2016-05-03 Nvidia Corporation System and method for calibration of serial links using a serial-to-parallel loopback
CN106130859A (zh) 2016-06-23 2016-11-16 北京东土科技股份有限公司 一种工业互联网现场层宽带总线配置管理实现方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4509113A (en) * 1982-02-02 1985-04-02 International Business Machines Corporation Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation
US4534011A (en) * 1982-02-02 1985-08-06 International Business Machines Corporation Peripheral attachment interface for I/O controller having cycle steal and off-line modes
US4604683A (en) * 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory
GB2252432B (en) * 1991-02-01 1994-09-28 Intel Corp Method and apparatus for operating a computer bus using selectable clock frequencies
US5553245A (en) * 1994-05-11 1996-09-03 Macronix International Co., Ltd. Automatic configuration of multiple peripheral interface subsystems in a computer system
US5828877A (en) * 1994-07-14 1998-10-27 Dell Usa, L.P. Circuit and method for optimizing creation of a compressed main memory image
US5617572A (en) * 1995-01-31 1997-04-01 Dell Usa, L.P. System for reducing power consumption in computers
US5926404A (en) * 1995-05-23 1999-07-20 Dell Usa, L.P. Computer system with unattended operation power-saving suspend mode
US5881247A (en) * 1995-11-30 1999-03-09 Allen-Bradley Company Llc System having a plurality of frame bytes capable of identifying addressed recipients and assert a busy signal onto the backplane bus to forthrightly abort the message transfer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7788420B2 (en) * 2005-09-22 2010-08-31 Lsi Corporation Address buffer mode switching for varying request sizes

Also Published As

Publication number Publication date
US6085269A (en) 2000-07-04
DE69721474D1 (de) 2003-06-05
DE69721474T2 (de) 2004-04-08
EP0859320A1 (en) 1998-08-19
EP0859320B1 (en) 2003-05-02

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