JPH10210237A - Image reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost as a whole by reducing a memory capacity and the hardware to the utmost without losing a function of sure switching of image read density to an object density under the condition that a speed of a stepping motor is kept constant. SOLUTION: The reader is provided with a gate enable signal generating means 11 that generates a gate enable signal EN for each step pulse SP and with an enable control means 14 that decides directly whether or not an input gate signal (line gate signal) received for each line is set to be an output gate signal (valid line gate signal) based on the priority of the gate enable signal EN generated from the gate enable signal generating means 11 so as to eliminate the need for the hardware such as a pulse counter, a comparator and a timing generator which have been required conventionally.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus such as an image scanner, a facsimile, and a scanner of a digital copying machine.

[0002]

2. Description of the Related Art Conventionally, there has been known a digital image reading apparatus which optically reads image information of a document and converts the image information into an electric signal. And a so-called book scanner that reads an original set on a contact glass by scanning an optical system. In a sheet scanner, a stepping motor is used as a driving source for transporting a document, and in a book scanner, a stepping motor is used as a driving source for scanning an optical system.

[0003] Regardless of the type of scanner, the image reading density can normally be switched, and the main scanning direction is dealt with by electrical processing related to a line sensor. Regarding the image reading density in the sub-scanning direction,
It is sufficient to change the moving speed of the stepping motor for moving the document or the optical system, but the maximum and minimum speeds of the motor are naturally limited. So, usually,
The speed of the stepping motor is made constant in accordance with the highest image reading density, and the image is read by thinning out the line gate signal according to the ratio between the reference image reading density and the target image reading density determined by this speed. By determining the effective line gate signal, the image reading density in the sub-scanning direction is apparently adjusted to the target image reading density. This type of method is disclosed in, for example,
It is known from Japanese Patent No. 74961.

[0004] For example, the resolution of one step pulse of the stepping motor is set to 120 corresponding to the reference image reading density.
Assuming that the resolution is 0 dpi, if it is desired to read at an image reading density of 200 dpi, one line of image data may be read once with a 6-step pulse. If it is desired to read at an image reading density of 240 dpi, one line of image data may be read once with a 5-step pulse. 220d
In the case of an image reading density at which a fraction occurs, such as pi, it is sufficient to average the values taking into account the remainder as in an example described later.

However, when the stepping motor is operating at a constant speed, the method of calculating the number of step pulses for thinning out the next time each time a line interrupt occurs for each line requires a long operating time in the interrupt processing. The load on the CPU increases.

In this regard, Japanese Patent Application Laid-Open No. 7-226831 discloses a technique capable of reducing the load on the CPU. This is because the number of motor steps of the stepping motor is calculated in advance before the image data reading operation is started and stored in the table, and at the time of the actual reading operation, the number of motor steps for each line stored in the table is used. The count value obtained from the number of step pulses of the stepping motor being driven is compared with each other, and if they match, the next line data is taken in as effective line data.

FIG. 19 shows a configuration example disclosed in the publication. First, the motor step number MS for changing the image reading density (dpi) in a state where the speed of the stepping motor is kept constant is calculated for each line before the start of the image data reading operation. A table counter 1 for storing a data cycle DF until the remainder of the number becomes 0 is provided, and a table 2 for sequentially storing the number of motor steps MS for each data cycle together with address information is provided. On the other hand, a pulse counter 3 for counting a step pulse SP sent from a control device (motor driver) for driving the stepping motor is provided, and a count value TP counted by the pulse counter 3 is provided.
And a comparator 4 for comparing the motor step number MS output from a predetermined address of the table 2 with the motor step number MS. As a result of the comparison by the comparator 4, when the count value TP matches the motor step number MS, the read timing signal EN indicating that the next line is an effective line at a predetermined timing via the timing generator 5.
(Enable enable signal) is output. Note that what can be actually read depends on a line gate signal indicating one line of image data, and is output as an output gate signal that becomes finally effective after being determined by the enable control unit 6. . At this timing, the pulse counter 3 is cleared to zero, and the table counter 1 also updates the table address by +1 so that the table value read from the table 2, that is, the next step as the motor step number MS is updated and set. I do.

[0008]

With respect to the conventional system shown in FIG. 19, it is assumed that one step of a stepping motor driven to rotate at a constant speed has a resolution of 1200 dpi, and under this condition, the image reading density is changed to 200 dpi. If image reading is to be performed by
It can be said that the line data input once may be read. In this case, first, the motor step number “6” is written into the table 2 as (TA + 1) (up to the address A) as the table value while updating the table address by the table counter 1 before the reading operation starts. On the other hand, in the actual reading operation, when the pulse counter 3 counts the step pulse SP up to “6”, the comparator 4 generates an enable signal EN to the timing generator 5 to indicate that the line is an effective line.

Further, the target image reading density is 220d.
In the case of pi, the first line (1200 + 0) ÷ 220 = 5 remainder 100 second line (1200 + 100) ÷ 220 = 5 remainder 200 third line (1200 + 200) ÷ 220 = 6 remainder 80 fourth line (1200 + 80) ) ÷ 220 = 5 Remainder 180 The number of step pulses (MS) is taken into consideration by taking the remainder into account as follows.
Are calculated to be 5, 5, 6, 5,... And stored in the table 2.

Therefore, in the conventional example, considering the hardware configuration, if the target image reading density is 220 dpi with respect to the reference image reading density of 1200 dpi, the table 2 has the table values of 5 and 5 in the address order.
., And when the target image reading density is 200 dpi, the same table values 6, 6, 6, 6,. That is, the address for the table 2 (TA + 1) is always required as the memory for the table 2 irrespective of the table value and the like, and at least 3 bits are required as the memory capacity of each table value and the bit number of the pulse counter 3. (For example, “6” = “110”, and 3 bits are required). That is, although the configuration is not particularly hindered in the operation control, it cannot be said that the memory or hardware is always used effectively, and the memory capacity can be saved by using the memory effectively. Has an aspect that can be reduced, and is an insufficient configuration.

Therefore, the present invention reduces the memory capacity and hardware as much as possible without impairing the function of reliably switching to the target image reading density under the condition that the speed of the stepping motor is kept constant. It is an object of the present invention to provide an image reading device capable of reducing costs.

[0012]

According to the first aspect of the present invention,
The stepping motor receives as input a step pulse sent from a control device for controlling the speed of the stepping motor at a constant speed and a line gate signal sent from an image processing unit as a signal indicating one line of image data. The image reading in the sub-scanning direction is performed by determining the effective line gate signal for performing the image reading by thinning out the line gate signal according to the ratio between the reference image reading density determined by the speed of the image and the target image reading density. In an image reading apparatus for controlling the density, whether or not a line gate signal input for each line is used as an effective line gate signal is determined based on the availability of a gate enable signal generated for each step pulse. According to a second aspect of the present invention, there is provided a gate enable signal generating means for generating a gate enable signal for each step pulse, and generating a gate enable signal for determining whether or not a line gate signal input for each line is an effective line gate signal. And an enable control means for determining whether or not the gate enable signal is generated by the means.

Therefore, whether or not a line gate signal input for each line is used as an effective line gate signal is directly determined by the availability of a gate enable signal generated for each step pulse. Hardware such as a pulse counter, a comparator, and a timing generator can be eliminated. Further, the memory for storing the enable / disable information of the gate enable signal, which is included in the gate enable signal generating means, only needs to be one bit indicating the enable / disable, and the memory can be saved.

According to a third aspect of the present invention, there is provided a memory for storing a gate enable signal generating means together with an address in advance with information on availability of a gate enable signal in accordance with a ratio between a reference image reading density and a target image reading density. Address control means for outputting address information for sequentially reading the gate enable signal from the memory in synchronization with the step pulse. Therefore, the memory requires only one bit to indicate whether or not the gate enable signal is available for each line = 1 address. The memory can be saved, and the memory is read from the memory in synchronization with the step pulse. Control corresponding to
The image reading density can be changed relatively accurately.

According to a fourth aspect of the present invention, the address control means includes setting means for setting a start address and an end address for reading the gate enable signal from the memory. Therefore, even if the enable / disable information of the gate enable signal corresponding to a plurality of target image reading densities is previously written in the memory, only the necessary amount can be read out by specifying the address later. Already, the usability is improved. In addition, since the repetition of the gate enable signal read from the memory can be freely performed in accordance with the designated address, it is possible to create memory data with a high degree of freedom so as to make use of the periodicity of the availability information of the gate enable signal.

According to a fifth aspect of the present invention, the address control means includes a circular read control means for reading out the gate enable signal from the memory up to the set end address and then returning to the head address. Therefore, the reading of the gate enable signal is repeated between the end address and the head address, so that the periodicity of the availability information of the gate enable signal can be utilized, and the head address is automatically restored, so that the hardware can be further saved.

According to a sixth aspect of the present invention, the gate enable signal generating means is configured to generate the gate enable signal at the timing of the rising edge and the timing of the falling edge of the step pulse. Therefore,
Since high-speed operation can be performed without increasing the frequency of the step pulse, measures against radio interference and simplification of control can be achieved.

According to a seventh aspect of the present invention, as the valid edge of the step pulse for generating the gate enable signal,
An effective edge selection setting means for selecting only the rising edge of the step pulse, only the falling edge, or any one of the rising edge and the falling edge is adopted. The motor driver that drives the stepping motor includes one that operates only at the rising edge of the step pulse, one that operates only at the falling edge, and one that operates at both the rising edge and the falling edge. Which edge is to be activated is selected and set by the valid edge selection and setting means according to the above, so that the specification of the motor driver can be flexibly dealt with.

According to an eighth aspect of the present invention, the gate enable signal generating means is provided when the signal indicating whether or not the corresponding line gate signal is inputted after the gate enable signal has become active level is at a predetermined level. There is an off condition regulating means for turning off the gate enable signal to an inactive level. Therefore, even if the phase relationship between the change in the line gate signal and the step pulse input for each line is asynchronous, the condition for turning off the once generated gate enable signal to the inactive level is controlled by the off condition regulating means. Since a signal indicating whether or not a corresponding line gate signal has been input after the enable signal has become active level is restricted only when the signal is at a predetermined level, the gate enable signal is substantially set to the line gate signal standby state. , And the probability that an effective line gate signal can be actually output corresponding to the line gate signal is increased.

According to the ninth aspect of the present invention, since the gate enable signal generating means has active level priority means for forcibly fixing the gate enable signal to the active level, the read operation is particularly performed when thinning processing is not required. Accuracy can be improved.

[0021]

FIG. 1 shows a first embodiment of the present invention.
A description will be given based on FIG. This embodiment presupposes a system for switching the image reading density as shown in the above-mentioned Japanese Patent Application Laid-Open No. 7-226831, and controls the speed of a stepping motor (not shown in this embodiment) to a constant speed. A step pulse SP sent from a control device (not shown; for example, a CPU to be described later) and an input gate signal sent from an image processing unit (not shown) as a signal indicating one line of image data. (Line gate signal), an effective line gate that actually performs image reading by thinning out an input gate signal in accordance with a ratio between a target image reading density and a reference image reading density determined by the speed of the stepping motor. Image reading apparatus provided with an image processing apparatus for controlling the image reading density in the sub-scanning direction by determining the signal as an output gate signal It is applied. In such a presupposed configuration, in the present embodiment, a gate enable signal generated for each step pulse SP determines whether or not an input gate signal input for each line is an output gate signal that is an effective line gate signal. E
It is basically configured to be determined according to N.

For this reason, the image processing apparatus 1 of the present embodiment
In the case of 0, first, a gate enable signal generating means 11 for generating a gate enable signal EN for each step pulse SP is provided. The gate enable signal generating means 11 stores in advance the enable / disable information ("1""0" information) of the gate enable signal for each line together with the address and a RAM table 12 as a memory, and in synchronization with the step pulse SP. It comprises a table counter 13 serving as an address control means for updating and outputting address information for sequentially reading the gate enable signal EN from the RAM table 12.

Here, the data creation algorithm for the RAM table 12 is the same as that of the above-mentioned publication, but the format of the table value is different. For example, the basic image reading density of 1200 dp, which is one of the specific examples described above.
Assuming that i is changed to the target image reading density of 220 dpi, conventionally, the motor step number MS is set as the table value, and therefore, the table values are 5, 5, 6, 5,... In the present embodiment, address 0 table value 0 = 0 address 1 table value 1 = 0 address 2 table value 2 = 0 address 3 table value 3 = 0 address 4 table value 4 = 1 address 5 table value 5 = 0 address 6 Table value 6 = 0 Address 7 Table value 7 = 0 Address 8 Table value 8 = 0 Address 9 Table value 9 = 1 Address 10 Table value 10 = 0 Address 11 Table value 11 = 0 Address 12 Table value 12 = 0 Address 13 Table Value 13 = 0 Address 14 Table value 14 = 0 Address 15 Table value 5 = 1 (the same applies to the following), the enable / disable information of the gate enable signal (“1” indicates enable, “0” indicates no) in one address and one bit corresponds to the line position to be actually read. Has been written. In the above example, addresses 0 to 4 are for the first line, addresses 5 to 9 are for the second line, addresses 10 to 1
5 is for the third line, and.

On the other hand, the input of the input gate signal and the gate enable signal EN read from the memory 12 are set to 1
An enable control circuit 14 is provided which is an enable control means that receives an input gate signal for each line and determines whether or not the input gate signal is used as an effective line gate signal depending on the availability of a gate enable signal EN.

In such a configuration, during the actual image reading operation, the table counter 13 counts up each time one step pulse SP is output, so that the address to be read from the RAM table 12 is +.
It is updated one by one (TA + 1), and output to the enable control circuit 14 as a gate enable signal EN in order from address 1 (0h). At this time, the enable control circuit 14
An input gate signal is also appropriately input to the input terminal. If the input gate signal is input when the gate enable signal EN of “1” is input, the internal processing of the enable control circuit 14 is performed based on the input gate signal. A gate enable signal is created and output as an output gate signal indicating that it is valid.

Referring to the time chart shown in FIG. 2, basically, of the input gate signals, the input gate at the position (line) where the reading operation is to be actually performed in accordance with the target image reading density. Only the signal is passed as the output gate signal. First, the address of the RAM table 12 is updated by the table counter 13 at the rising edge of the step pulse SP. As a result, the enable / disable information of the gate enable signal EN, which is a table value in the RAM table 12, is read for each step pulse SP, and is provided to the enable control circuit 14. On the other hand, when a gate enable signal EN having information “1” (permitted) is given to the enable control circuit 14, an internal gate enable signal is generated in the enable control circuit 14 at a predetermined timing. When an input gate signal is supplied while the internal gate enable signal is "1", the signal can pass through as it is, is output as an output gate signal (L level), and indicates that the line is a read line. At this time, when the input gate signal changes from "0" to "1", the internal gate enable signal also returns from "1" to "0", and the next "1"
Wait for a gate enable signal EN having the following information.

According to the present embodiment, the RAM table 1
2 requires only one bit for one address and stores the enable / disable information of the gate enable signal, which is directly used for each line. Therefore, the conventional pulse counter 3, comparator 4, timing generation Hardware such as the device 5 can be reduced as much as possible. Also, as can be seen from the time chart shown in FIG.
Since the gate enable signal EN is read in synchronization with the control of the enable control circuit 14, the density conversion process can be performed with relatively high accuracy. That is, when the step pulse SP moves by the target density position, the gate enable signal EN can be output relatively quickly without going through circuit processing such as a comparator.

Next, a second embodiment of the present invention will be described with reference to FIG. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted (the same applies to the following embodiments). In the image processing apparatus 10 of the present embodiment, a comparator 15 that outputs a reset signal for resetting the table counter 13 at a predetermined count value is added. That is, when the count value of the table counter 13 reaches the designated value set in the comparator 15, the comparator 15 regards this as an end address and resets the operation so as to return to reading from the head address again. It constitutes read control means.

According to such a configuration, for example, in the above-described specific example of 220 dpi, the RAM table 1
Considering the periodicity of the data in 2, the 5, 5, and 6 can be regarded as one cycle, so if the designated value in the comparator 15 is set to 16 (corresponding to the number of data of 5 + 5 + 6), the address 16 Desired control can be performed only by repeatedly using data, and the amount of memory used in the RAM table 12 can be saved.

Incidentally, the same operation can be performed by initializing the address of the RAM table under the control of the CPU. However, if the load on the CPU increases and the step pulse becomes faster, there is a limit in the operation by the CPU. . In this regard, in this embodiment, since the hardware is the comparator 15, there is no such inconvenience.
In particular, since it is not necessary to specify an address, the hardware configuration is simplified.

A third embodiment of the present invention will be described with reference to FIG. In the image processing apparatus 10 of the present embodiment, the RAM counter 12
An address setting device 16 for setting a start address and an address setting device 17 for setting an end address in reading the gate enable signal EN from the device are added as setting means. Here, the address setting unit 16 instructs the start of reading from the set address, and outputs a counter set address to the table counter 13. The address setting unit 17 instructs the end of reading at the set address, and outputs a counter reset address to the table counter 13.

According to such a configuration, the reading from the RAM table 12 can be repeated between the start address and the end address set in the table counter 13, so that the RAM table 12 is extremely effective with a small memory capacity. Available to For example, reference image reading density 1
Under the condition of 200 dpi, 0, 0, 0, 0, 0,
If the enable / disable information of the gate enable signal is stored, such as 0 or 1, and the start address is 0 and the end address is 5, the specification conforms to 200 dpi. Even in the same RAM table 12, the start address is 3 and the end address is 3. If 5 is set to 5, the specification is compatible with 400 dpi. Furthermore, RAM
In table 12, the address from address 6 to address 2
1 for 220 dpi described above for 16 addresses up to 2
If the availability information of the gate enable signal for the cycle is stored and can be read out by designating the start address and the end address, the RAM table 12 corresponding to various target image reading densities can be created. Calculations and the like can be performed only once, and the degree of freedom in memory creation is high, so that usability is improved.

FIGS. 5 and 6 show a fourth embodiment of the present invention.
It will be described based on. Image processing device 18 of the present embodiment
The gate enable signal generating means 11 functions to update the memory address at both the rising edge timing and the falling edge timing of the step pulse SP to generate the gate enable signal EN.
Is used. The time chart of FIG. 5 shows this state, in which the rising edge of the step pulse SP,
At the timing of the falling edge, the table counter 13 counts up to update the memory address of the RAM table 12, and an enable signal based on the RAM data stored in the RAM table 12 is output to the enable control circuit 14.

By the way, in the first embodiment shown in FIG. 2, the memory address is updated only at the timing of the rising edge of the step pulse SP, and one address is updated by one step pulse SP. In this regard, in the present embodiment, the memory address is updated at the timing of both edges of the step pulse SP, and two addresses are updated with one step pulse SP, so that the frequency of the step pulse SP is substantially 1 / 2. As a result, countermeasures and control for radio wave interference become easier.

In the present embodiment, the step pulses SP for the image processing device 18 and the motor driver 20 for driving the stepping motor 19 are generated by the CPU 21 as a control device as shown in FIG. Supplied. Here, the motor driver 20 includes one that operates only at the rising edge of the step pulse SP, one that operates only at the falling edge, and one that operates at both the rising edge and the falling edge. Absent.

By the way, when the motor driver 20 operates at both the rising edge and the falling edge of the step pulse SP, and when the image processing apparatus 10 operating at the rising edge shown in FIG. 1 and the like is used. 7, the edge detection circuit 22 is required as shown in FIG. 7 as a reference example, and the cost increases accordingly. That is, the step pulse S supplied from the CPU 21
An edge detection circuit 22 for converting both the rising edge and the falling edge of P into a pulse rising edge is required (see FIG. 8). This edge detection circuit 2
2 is, for example, as shown in FIG.
, And an exclusive OR gate 24 to which a step pulse SP passing through the delay circuit 23 and a step pulse SP not passing through the delay circuit 23 are input. In this regard, according to the present embodiment, since the image processing apparatus 18 itself functions so as to operate at the rising edge and the falling edge of the step pulse SP, the CPU 21 can be directly connected. Can be realized without the need.

A fifth embodiment of the present invention will be described with reference to FIG. In this embodiment, a processing device 26 is configured by adding an effective edge selection setting circuit (effective edge selection setting means) 25 to the input section of the step pulse SP for the image processing device 10 having the configuration shown in FIG. I have.
The valid edge selection setting circuit 25 is provided with the edge detection circuit 2
7, an inverting circuit 28, and a selector 29 to which a pulse that has passed through the edge detecting circuit 27, a pulse that has passed through the inverting circuit 28, and an unprocessed pulse among the step pulses SP supplied from the CPU 21 are input. ing. The edge detection circuit 27 is the same as the edge detection circuit 22 and has a function of converting a pulse rising at both a rising edge portion and a falling edge portion in the step pulse SP. Used for falling edge. The inverting circuit 28 inverts the H level and the L level of the step pulse SP, and has a function of converting a falling edge of the step pulse SP into a rising edge. The selector 29 inputs only one of the three step pulses SP into the image processing apparatus 10 in accordance with a selection signal from the CPU 21. The CPU 2 outputs a selection signal according to the specification of the motor driver 20 to be used.

In such a configuration, when the motor driver 20 to be used operates only at the rising edge of the step pulse SP, the selector 29 selects the unprocessed step pulse SP in response to the selection signal from the CPU 21 and performs image processing. Output to the table counter 13 in the device 10. That is, functionally, the configuration is the same as that shown in FIG. 1, and the memory address of the RAM table 12 is updated at the timing of the rising edge of the step pulse SP. When the motor driver 20 to be used operates only at the falling edge of the step pulse SP, the selector 29 selects the step pulse SP inverted by the inverting circuit 28 in response to a selection signal from the CPU 21, and the image processing apparatus 10 Output to the inside table counter 13. Accordingly, the table counter 13 sets the signal RA at substantially the timing of the falling edge of the step pulse SP.
The memory address of the M table 12 is updated. further,
When the motor driver 20 to be used operates at both the rising edge and the falling edge of the step pulse SP, the selector 29 selects a pulse that has passed through the edge detection circuit 27 according to a selection signal from the CPU 21, and the image processing apparatus 10 Output to the inside table counter 13. Therefore, the table counter 13 updates the memory address of the RAM table 12 substantially at the timing of the rising edge and the falling edge of the step pulse SP. In this manner, any specification of the motor driver 20 to be used can be flexibly dealt with only by changing the software of the CPU 21 and the hardware configuration of the processing device 26 does not need to be changed. In particular, since the image processing apparatus 10 according to the present embodiment is often implemented as an IC, there is almost no increase in cost as long as the number does not exceed a certain number of gates. In particular, the addition of a circuit such as the effective edge selection setting circuit 25 shown in FIG.

A sixth embodiment of the present invention will be described with reference to FIGS. The present embodiment is designed to reduce the deterioration of the reading accuracy that can occur when the change between the input gate signal (line gate signal) and the step pulse SP is asynchronous.

As a prerequisite, for example, the method of FIG. 5 in the above-described fourth embodiment will be reviewed. In other words, the memory address of the RAM table 12 is updated at both the rising edge timing and the falling edge timing of the step pulse SP to generate the gate enable signal EN. When the phase relationship between the input gate signal and the step pulse has a synchronous relationship as shown in FIG. 5, the gate enable signal becomes active at the timing when the RAM data becomes "1", and the input gate signal is enabled. Thereafter, the enable signal is made inactive at the rising edge of the input gate signal, so that a desired output gate signal is obtained as shown in the figure.

However, when the phase relationship between the change of the input gate signal and the change of the step pulse SP is asynchronous as shown in FIG. 17, the image reading line may be greatly shifted to cause image deterioration. is there. That is, in the case of the asynchronous state as shown in FIG. 17, the input gate signal is already active at the timing when data (enable signal) is read from the RAM table 12, so that the output gate signal is not applied until the next input gate signal is input. This is because the data may not be output (t8, t11, t12).

This point will be described in detail using a specific example.
Now, when one pulse of the step pulse SP is generated, the distance traveled by the reading unit corresponds to one line of 1100 dpi (that is, one line).
1/1100 (9.1 × 10 to ⁴ inches), and assume that the target image reading density is 400 dpi. In this case, the thinning pattern is as follows: 1st line (1100 + 0) ＝ 400 = 2 remainder 300 2nd line (1100 + 300) ÷ 400 = 3 remainder 200 3rd line (1100 + 200) ÷ 400 = 3 remainder 100 4th line (1100 + 100) ÷ 400 = 3 The remainder is 0. Therefore, the data pattern written in the RAM table 12 is a repetition of 01 001 001 001... As shown in the RAM data in FIG. Also, as described in the fourth embodiment,
It is assumed that a stepping motor having a specification of rotating at the rising edge and the falling edge of the step pulse SP is used.

Under such a premise, as can be seen from the RAM data, if four input gate signals are passed as output gate signals while eleven step pulses SP are output, an image reading density of 400 dpi is obtained. The operation timing at this time is shown in FIG. First, when the step pulse SP advances by two pulses (t1), the memory address advances to 0 and 1, and by reading data "1" from the RAM table 12 (t2), the gate enable signal becomes "1" (t2). t3). At this time (actually, immediately after), when an input gate signal is input (t4),
An output gate signal is also output (t5). Subsequently, at the fifth pulse of the step pulse SP, the data in the RAM table 12 becomes "1" (t6), and a gate enable signal is output (t7). However, at this time, since the input gate signal has already been activated, no output gate signal is output (t8). The same applies to other data “1” timings (t9, t10), and no output gate signal is output (t11, t12). In this state, the image reading position is shifted for three lines, and the read image is greatly deteriorated.

From the above, in the present embodiment,
As shown in FIG. 11, the gate enable signal generation circuit 30
Is added. The gate enable signal generation circuit 30 constitutes a main part of the gate enable signal generation means 11 described above.
The gate enable signal E based on the RAM data in the table 12, particularly, the data "1" and the input gate signal.
It has a function of generating N. The gate enable signal generation circuit 30 receives the input gate signal and RA as shown in FIG.
A gate enable signal reset signal generating circuit 31 functioning as an off condition restricting means using the RAM data of the M table 12 as an input; a falling edge detecting circuit 32 for detecting a falling edge of the input gate signal; An AND gate 33 for calculating the logical product of the output signals of the reset signal generation circuit 31 and the falling edge detection circuit 32;
A rising edge detection circuit 34 for detecting a rising edge of "1" data in the AM data; and a gate enable signal EN which is set by the output of the rising edge detection circuit 34 to output the AND gate 3
3 and a 1-bit storage element 35 having a flip-flop configuration that is reset by the output of C.3.

Here, as shown in FIG. 13, the gate enable signal reset signal generation circuit 31 includes a falling edge detection circuit 36 for detecting a falling edge of the input gate signal, and " A rising edge detection circuit 37 for detecting a rising edge of data "1" and a 1-bit storage element 38 of a flip-flop configuration which is reset by the output of the falling edge detection circuit 36 and reset by the output of the rising edge detection circuit 37. It is configured. The falling edge detection circuit 36 is, for example, as shown in FIG.
As shown in (1), an AND which receives a signal obtained by delaying the input gate signal by the delay circuit 39 and an inverted signal of the input gate signal as inputs
It is constituted by a gate 40. For example, as shown in FIG. 15, the rising edge detection circuit 37 delays the data "1" in the RAM data by the delay circuit 39 and further inverts the signal to "1" in the RAM data.
And an AND gate 40 to which the following data is input. As a result, the gate enable signal reset signal generation circuit 31 outputs the gate enable signal reset signal indicating whether or not the corresponding input gate signal has been input after the gate enable signal once becomes the active level (“1” level). When the gate enable signal is at a predetermined level (H level), it functions to turn off the gate enable signal to an inactive level (“0” level).

In such a configuration, an example of operation control in the present embodiment will be described with reference to a time chart shown in FIG. 18 on the same premise as in FIG. That is, as can be seen from the RAM data, if four input gate signals are passed as output gate signals while eleven step pulses SP are output, the operation timing at the constant speed at which the image reading density becomes 400 dpi is shown in FIG. It is shown. First, when the step pulse SP advances by two pulses (T
1), the memory address advances to 0 and 1, and by reading data "1" from the RAM table 12 (T2), the gate enable signal becomes "1" (T3). This is the same as in the case of FIG. At this time, the gate enable signal reset signal output from the gate enable signal reset signal generation circuit 31 becomes L level because the gate enable signal once rises (T4), but the input gate signal is input immediately (T4). T5), the gate enable signal reset signal immediately returns to the H level (T5).
6). Therefore, immediately after the output gate signal is output (T
7) At the rising edge of the input gate signal, the gate enable signal returns to the inactive level (T8). That is, the gate enable signal is reset under the condition that the gate enable signal reset signal is at the H level. Subsequently, the data of the RAM table 12 becomes "1" at the fifth pulse of the step pulse SP (T9), and even if the gate enable signal is output (T10), the input gate signal is already active at this point. Therefore, the point that the output gate signal is not output (T11) is the same as in the case of FIG. Thus, in this case, one line is missing.

However, at this time, since the gate enable signal reset signal remains at the L level at the rise of the gate enable signal (T12), the gate enable signal is not reset to the inactive level (T13). That is, the gate enable signal is in a standby state waiting for the input of the next input gate signal, and when the input gate signal is input (T14), the output gate signal is output (T15). The same applies at the time (T16) when the next input gate signal is input, and the output gate signal is output (T17).

Therefore, according to the present embodiment, as can be seen from the comparison with FIG. 17, even if the phase relationship of the change between the input gate signal and the step pulse SP is asynchronous,
The reading error for the line is reduced to, for example, an error for one line, and the degree of deterioration of the read image quality is improved.

A seventh embodiment of the present invention will be described with reference to FIG. In the present embodiment, the enable control circuit 14 of the gate enable signal reset signal generation circuit 31
An OR gate 43 is interposed on the output side with respect to. The OR gate 43 receives the output of the gate enable signal reset signal generation circuit 31 and an external selective forced enable signal, and functions as active level priority means.

According to the present embodiment, when the thinning process is not particularly required, a forced enable signal is supplied from the outside so that the state of the gate enable signal from the gate enable signal reset signal generating circuit 31 can be reduced. Therefore, the gate enable signal can be forcibly fixed to the active level. Therefore, it is possible to output an output gate signal in accordance with the input gate signal, thereby performing an image reading operation without thinning. Therefore, reading without deteriorating the image quality can be performed at any time.

[0051]

According to the first and second aspects of the present invention, whether a line gate signal input for each line is set as an effective line gate signal is directly determined by the availability of a gate enable signal generated for each step pulse. A gate enable signal generating means for generating a gate enable signal for each step pulse;
And an enable control means for determining whether or not a line gate signal input for each line is an effective line gate signal according to whether or not the gate enable signal generated by the gate enable signal generation means is provided. Hardware such as a pulse counter, a comparator, and a timing generator can be made unnecessary. In addition, a memory for storing the enable / disable information of the gate enable signal, which is included in the gate enable signal generating means, also has a 1 bit indicating whether or not it is available And save memory.

According to the third aspect of the present invention, the memory in which the gate enable signal generating means stores in advance the availability information of the gate enable signal together with the address in accordance with the ratio between the reference image reading density and the target image reading density. And address control means for outputting address information for sequentially reading the gate enable signal from the memory in synchronization with the step pulse, so that the memory determines whether or not the gate enable signal is available for each line = 1 address. Since only one bit is required, the memory can be saved, and the data is read from the memory in synchronization with the step pulse. Therefore, direct control corresponding to the actual situation of the stepping motor is achieved, and the image reading density can be relatively accurately adjusted. Can be changed.

According to the fourth aspect of the present invention, the address control means has the setting means for setting the start address and the end address for reading the gate enable signal from the memory. Even if the enable / disable information of the gate enable signal corresponding to the image reading density is written, only the necessary portion can be read later by specifying the address, and the setting to the memory can be performed only once, thereby improving the usability. In addition, the repetition of the gate enable signal read from the memory can be freely performed according to the designated address, so that the memory data with a high degree of freedom can be created so as to make use of the periodicity of the availability information of the gate enable signal.

According to the fifth aspect of the present invention, after reading the address control means up to the end address set for reading the gate enable signal from the memory,
With the configuration including the cyclic read control means for returning to the head address, the periodicity of the availability information of the gate enable signal can be utilized, and the hardware can be further saved by automatically returning to the head address.

According to the sixth aspect of the present invention, the gate enable signal generating means is configured to generate the gate enable signal at the timing of the rising edge and the timing of the falling edge of the step pulse. Therefore, high-speed operation can be performed without increasing power consumption, and thus countermeasures and control for radio wave interference can be made easier.

According to the seventh aspect of the present invention, as the effective edge of the step pulse for generating the gate enable signal, only the rising edge of the step pulse, only the falling edge, or both of the rising edge and the falling edge Since the configuration is provided with an effective edge selection setting means for selecting one, a motor driver that drives the stepping motor operates only at the rising edge of the step pulse, operates only at the falling edge, and operates at the rising edge. Some of them operate on both falling edges. However, depending on the specifications of the motor driver to be used, which edge is to be made valid is selected and set by the valid edge selection setting means.
It is possible to flexibly cope with the specifications of the motor driver without changing the hardware.

According to the eighth aspect of the present invention, the gate enable signal generating means has a signal indicating whether or not a corresponding line gate signal has been input after the gate enable signal has become active level at a predetermined level. Sometimes, there is an off condition regulating means for turning off the gate enable signal to the inactive level, so that the phase relationship between the change of the line gate signal input for each line and the step pulse is asynchronous. Also, the condition for turning off the once generated gate enable signal to the inactive level is changed to a predetermined level by a signal indicating whether or not the corresponding line gate signal has been input after the gate enable signal has become active level by the off condition regulating means. By restricting only at certain times, the gate enable signal is effectively line-gated. Can be maintained in preparative signal standby state, thus increasing the probability that can be actually output valid line gate signal to correspond to the line gate signal, it is possible to suppress the deterioration of the read image quality.

According to the ninth aspect of the present invention, since the gate enable signal generating means has active level priority means for forcibly fixing the gate enable signal to the active level, thinning processing is particularly necessary. If not, the reading accuracy can be easily improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart showing an operation.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

FIG. 5 is a time chart showing a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing the configuration.

FIG. 7 is a block diagram showing a reference example.

FIG. 8 is a time chart showing the operation of the reference example.

FIG. 9 is a block diagram illustrating a configuration of an edge detection circuit in the reference example.

FIG. 10 is a block diagram showing a fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a sixth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of the gate enable signal generation circuit.

FIG. 13 is a block diagram showing a configuration of the gate enable signal reset signal generation circuit.

FIG. 14 is a block diagram showing a configuration of the falling detection circuit.

FIG. 15 is a block diagram showing a configuration of the rise detection circuit.

FIG. 16 is a time chart illustrating an operation control example.

FIG. 17 is a time chart showing a reference example.

FIG. 18 is a block diagram showing a seventh embodiment of the present invention.

FIG. 19 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Gate enable signal generation means 12 Memory 13 Address control means 14 Enable control means 15 Circulation read control means 16, 17 Setting means 19 Stepping motor 21 Control device 25 Effective edge selection setting means 31 Off condition restriction means 43 Active level priority means

Claims (9)

[Claims] 1. A step pulse sent from a control device for controlling the speed of a stepping motor to a constant speed, and a line gate signal sent from an image processing unit as a signal indicating one line of image data are input. By decimating the line gate signal according to the ratio between the reference image reading density determined by the speed of the stepping motor and the target image reading density to determine an effective line gate signal for performing image reading, In an image reading apparatus that controls the image reading density in the scanning direction, whether or not a line gate signal input for each line is set as an effective line gate signal is determined based on the availability of a gate enable signal generated for each step pulse. An image reading apparatus characterized in that: 2. A step pulse sent from a control device for controlling the speed of a stepping motor to a constant speed, and a line gate signal sent from an image processing unit as a signal indicating one line of image data are input. By decimating the line gate signal according to the ratio between the reference image reading density determined by the speed of the stepping motor and the target image reading density to determine an effective line gate signal for performing image reading, In an image reading apparatus for controlling an image reading density in a scanning direction, a gate enable signal generating means for generating a gate enable signal for each step pulse, and determining whether a line gate signal input for each line is an effective line gate signal. Whether the gate enable signal is generated by the gate enable signal generating means. An image reading apparatus comprising: an enable control unit that determines whether or not a signal is available. 3. A gate enable signal generating means, comprising: a memory in which information on the availability of a gate enable signal for each line is stored in advance along with an address in accordance with a ratio between a reference image reading density and a target image reading density; 3. An image reading apparatus according to claim 2, further comprising address control means for outputting address information for sequentially reading a gate enable signal from said memory in synchronization with said image data. 4. The image reading apparatus according to claim 3, wherein the address control means has a setting means for setting a start address and an end address for reading the gate enable signal from the memory. 5. The cyclic read control unit according to claim 3, wherein the address control unit includes a cyclic read control unit that reads the gate enable signal from the memory up to the end address set and then returns to the start address. Image reading device. 6. The image reading apparatus according to claim 2, wherein said gate enable signal generating means generates a gate enable signal at each of a rising edge timing and a falling edge timing of the step pulse. 7. An effective edge selection for selecting only a rising edge of a step pulse, only a falling edge, or any one of both a rising edge and a falling edge as an effective edge of a step pulse for generating a gate enable signal. The image reading apparatus according to claim 2, further comprising a setting unit. 8. A gate enable signal generating means for inputting a gate enable signal when a signal indicating whether or not a corresponding line gate signal has been input is at a predetermined level after the gate enable signal goes to an active level. 8. The image reading apparatus according to claim 2, further comprising an off condition restricting means for turning off the active level. 9. The image reading apparatus according to claim 8, further comprising: active level priority means for forcibly fixing the gate enable signal to the active level for the gate enable signal generating means.