JPH0758912A - Facsimile controller - Google Patents

Abstract

PURPOSE:To compress a circuit scale by setting the driving-pulse width of both stepping motors for original feeding and recording paper feeding on the same storage means arbitrarily. CONSTITUTION:A picture width conversion control circuit 209 starts the counting operation of a counter 210 in a state where a selector 213 selects a register 217 when a read enable signal S202 from an interface control circuit 201 is turned on. The counter 210 counts a clock generated in the inside from picture information synchronous clock from a reading part setting the register 217 as an initial value, and outputs a carry signal when the counter counts a full count value. When such carry signal is outputted, the picture width conversion control circuit 209 turns on a buffer input enable signal on a signal path S206, and simultaneously, switches the selector 213 to a register 218 side. In other words, an effective picture signal can be selected from a read input signal, which enables variable setting to be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a facsimile control device for controlling the flow of image information, paper feed, etc. in a facsimile device or the like.

[0002]

2. Description of the Related Art Facsimile apparatuses differ in the structure of a sub-scanning (paper feed) mechanism of a recording unit and a reading unit, the type of a step motor used therein, the reading speed and the recording speed, etc., depending on the model. Therefore, it is necessary to apply the control conditions for image information transfer between the line buffer control unit and the reading unit or the recording unit and the driving conditions for the step motor to each model.

In the conventional facsimile machine, the control circuit used for controlling the transfer of image information and the drive of the step motor is newly provided with a dedicated control circuit when developing a new model of the facsimile machine. The reality is that it is designed. Further, when the design of the reading unit or the recording unit is changed in the process of developing the model, the control circuit is also designed at the same time.

[0004]

However, in the above-mentioned conventional configuration, the control circuit for controlling the transfer of image information and the drive of the step motor cannot easily change the condition of the control unit and lacks versatility, and thus the facsimile is not available. There was a problem that the development cost of the device was reduced and the development period was shortened.

The present invention has been made to solve the above-mentioned conventional problems, and the driving control conditions of the step motor and the like can be arbitrarily set by an external microcomputer. It is an object of the present invention to provide a general-purpose reading control device capable of arbitrarily setting a value corresponding to the drive pulse width of the stepping motor which is also used for transporting the same, and which can be commonly applied to different types of facsimile machines. .

[0006]

In order to achieve the above-mentioned object, the present invention provides a stepping motor which is used for a predetermined value arbitrarily set by a microcomputer, that is, for conveying an original document and a recording paper. Storage means for holding a value corresponding to the drive pulse width, and means for outputting a drive signal for the stepping motor based on a predetermined value read from the storage means both at the time of carrying a document and at the time of carrying a recording sheet. It is equipped with.

[0007]

According to the present invention, with the above-described structure, a value corresponding to the drive pulse width of the stepping motor used for conveying the original and the recording sheet from the microcomputer can be arbitrarily written in the storage means. . This allows
It is possible to realize a versatile reading control device that can be applied to different types of facsimile machines, and a recording means having the same drive pulse width of the stepping motor for conveying the original and the drive pulse width of the stepping motor for conveying the recording paper. The recording means can be effectively used.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below by taking a facsimile machine as an example.

FIG. 1 is a block diagram showing the overall construction of a reading control apparatus according to an embodiment of the present invention. In the figure, 1 is a clock control unit, 2 is an image information control unit, 3 is a counter control unit, and 4 is an interface control unit. All these units are internal bus S16
Are connected to each other.

The interface control unit 4 has a data bus S14 and an interface S15 for address and other control signals with an MPU (not shown) of the facsimile machine, and each of the other units 1, 2 through the internal bus S16. Data is read from and written to the registers in 3 under the control of the MPU. It is also possible to directly connect the internal registers of the units 1, 2, and 3 to the data bus S14 and the interface S15 and directly control them from the MPU. In that case, the interface control unit 4 may be omitted. .

A detailed block diagram of the clock control unit 1 is shown in FIG. In the figure, 101 is an oscillating circuit for generating a signal S101 having a constant cycle determined by the natural frequency of the crystal pendulum 5. Reference numeral 102 denotes a frequency dividing circuit, which generates a basic clock S1, a counting clock S7, an internal clock S102, and an external clock S2 by dividing the frequency of the signal S101. The external clock S2 is supplied to the MPU and its frequency dividing circuit. Reference numerals 103, 105 and 107 are registers controlled through the internal bus S16. 104 and 106 are counters, and 108 and 109 are selectors.

The counter 104 counts the internal clock S102 using the set value of the register 105 as an initial value, and generates a constant speed step pulse S103. Therefore, register 1 on the MPU side
By changing the set value of 05, the cycle of the constant speed step pulse S103 can be arbitrarily changed. One of the constant speed step pulse S103 and the variable speed step pulse S3 for reading input from the image information control unit 2, which is designated by the control signal S105 output from the register 103, is selected by the selector 108 and the facsimile apparatus Step pulse S5 for sub-scanning drive of the reading unit (not shown)
Is sent to the outside as. The other selector 109 is
One of the constant speed step pulse S103 and the variable speed step pulse S4 for recording input from the image information control unit 2 is selected according to the control signal S104 from the register 103, and the recording unit (not shown) of the facsimile apparatus is selected. ) Is sent to the outside as a step pulse S6 for driving the sub-scan. That is, the MPU can switch the step pulses S5 and S6 by controlling the set value of the register 103. The counter 106 generates an image information synchronization clock S8 to be supplied to the image information control unit 2 by counting a clock S9 input from the outside using the setting value of the register 107 as an initial value. The cycle of this image information synchronizing clock S8 is also set by the register 107 to the MPU.
It can be controlled from the side.

A detailed block diagram of the image information control unit 2 is shown in FIG. In the figure, S10 is an interface with a reading unit, S11 is an interface with a recording unit, and S12 is an interface with a line buffer control unit (not shown) of the facsimile apparatus.

Reference numerals 201, 202, and 203 denote interface control circuits for the reading unit, the recording unit, and the line buffer control unit, respectively. Image information is stored in these interface control circuits 20
It is given and received via 1, 202, 203. 204 is an image information processing circuit, 207 is a delay recording control circuit, 209 is an image width conversion control circuit,
20 8 and 210 are counters, 212 and 213 are selectors, and 215 to 218
Is a register. By the cooperation of these units, the transfer of image information between the line buffer control unit and the reading unit or the recording unit is controlled, and the response delay correction of the recording operation and the image in the main scanning direction, which will be described later, are controlled through the control. Information is reduced and width is converted. As parameters required for these processes, the response delay time, the deletion / addition width, and the effective width are set in the registers 216, 217, 218 from the internal bus S16. A circuit for generating a clock as described later and supplying it to a necessary part exists in the unit, but it is omitted in the figure.

205 is a variable speed step pulse generation control circuit, 206 is a counter, 211 is a selector, 214 is a register, 2
Reference numeral 19 is a sub-scanning reduction control circuit. These units generate variable speed step pulses S3 and S4 used for sub-scanning driving of the reading unit and the recording unit. Variable speed step pulse S3
The cycle of S4 is set in the register 215, and the stop waiting time (described later) is set in the register 214. The sub-scanning reduction control circuit 219
When the image is reduced in the sub-scanning direction, the variable speed step pulse S4 is thinned out.

It is necessary to switch the method of controlling the transfer of the image information and the method of controlling the generation timing of the variable speed step pulses S3 and S4 depending on the operation mode (reception, transmission, copy) of the facsimile apparatus. A register 220 is provided for setting control information (including information for instructing reduction as will be described later) according to this operation mode from the MPU, and the contents set therein are the signal pulse S220. After that, each of the above circuits 204, 205, 207, 209, 2
Given to 19. The register 220 is connected to the internal bus S16 and can be controlled by the MPU.

FIG. 4 is a block diagram showing the detailed arrangement of the counter control unit 3. 302 is a selector and 303 is a counter. 301 is a register for controlling the selector 302 and the counter 303, and 304 and 305 are registers for setting an initial value of the counter 303. Reference numerals 306 and 307 are registers for reading the count value of the counter 303 into the MPU. These registers 301, 304 to 307 are connected to the internal bus S16 and can be controlled by the MPU.

The selector 302 selects one of the reading step pulse S5, the recording step pulse S6, and the counting clock S7 according to the designation from the register 301, and inputs it to the counter 303. When started by the register 301, the counter 303 counts the output of the selector 302 with the values of the registers 304 and 305 as initial values. That carry signal S13
Is sent as an interrupt signal to the MPU.

Next, the operation of the facsimile controller will be described in detail in the order of the transmission mode, the reception mode and the copy mode.

First, the transmission mode will be described. In this mode, when the input ready signal on the interface S12 is turned on by the line buffer control unit, the interface control circuit 203 activates the circuits 205 and 209 by the signal on the signal path S201 (the delay recording control circuit 207 Do not start). Since the transmission mode is specified by the signal path S220, the image information processing circuit 204 synchronizes with the internally generated clock based on the image information synchronization clock input from the reading unit and reads the image information on the signal path S203. Is taken in and output to the signal path S205. Signal path S205
The above image information is transferred from the interface control circuit 203 to the interface S12 with the line buffer control section.

When the read enable signal S202 from the interface control circuit 201 is turned on, the image width conversion control circuit 209 causes the selector 213 to select the register 217 and start the counting operation of the counter 210. The counter 210 uses the register 217 as an initial value, counts the number of clocks generated internally from the image information synchronizing clock from the reading unit, and outputs a carry signal when the full count is reached. When this carry signal is output, the image width conversion control circuit 209 causes the signal path S2
At the same time when the buffer input enable signal on 06 is turned on, the sector 213 is switched to the register 218 side. That is,
The register 217 selects a valid image signal from the read input signals, and in the present invention, this is variably set by the microcomputer. As a result, even in various facsimile apparatuses having different reading reference positions, various original sizes can be satisfactorily read simply by setting a value that defines the reading / erasing width in the register.

On the other hand, the counter 210, after being reset, counts with the set value of the register 218 as an initial value, and outputs a carry signal when the full count is reached. When this carry signal is output, the image width conversion control circuit 209 turns off the buffer input enable signal and stops the counter 210. Even when the read enable signal S202 for the next line is turned on, if it does not appear on the start prohibition signal path S201 such as busy of the line buffer control unit, the image width conversion control circuit 209 outputs the same buffer input enable signal as described above. Take control. In this way, the read image information is transferred line by line to the line buffer controller.

On the other hand, a variable speed step pulse generation control circuit
When the read enable signal S202 is turned on, the 205 activates the counter 206 while keeping the selector 211 selecting the register 215. The counter 206 uses the value of the register 215 as an initial value and counts a clock (not shown) internally generated based on the reference clock S1. When the carry signal is output from the counter 206, the variable speed step generation control circuit 205 outputs one pulse S204 and stops the counter 206. For the next line, the same operation is performed when the read enable signal S202 is turned on, but the signal path S2
It does not operate when the start prohibition signal appears on 01. The pulse S204 is output to the outside as a reading variable speed step pulse S3 through the sub-scanning reduction control circuit 219.

The clock control unit 1 is provided until the paper is fed to the reading start position in the reading section.
The selector 108 in the selector 30 in the counter control unit 3 selects the constant speed step pulse S103.
2 is controlled by the MPU via the registers 103 and 301 so as to select the reading step pulse S5. Therefore, the counter 303 counts the constant speed step pulse S103. During this time, the operations of the image width conversion control circuit 209 and the variable speed step pulse generation control circuit 205 are suppressed by the MPU via the register 220. When a predetermined time (set in the registers 304 and 305) has passed and the paper has been fed to the reading start position, a carry signal S13 is output from the counter 303 and the MPU is interrupted. When the MPU receives this interrupt, each of the above circuits 20 is sent through the register 220.
At the same time as releasing the suppression of 5,209, the selector 108 is switched to the variable speed step pulse S3 side through the register 103. The MPU also resets the registers 304 and 305 in order to monitor the end of reading, and causes the counter 303 to count the reading step pulse S5. When it is interrupted by the carry signal S13, the MPU determines that the reading of one page is completed and stops the above-mentioned transmission operation. In the middle of the process, the MPU can read the count value of the counter 303 through the registers 306 and 307 to know the progress of the read operation.

Next, the operation in the reception mode will be described. When the output ready signal of the interface S12 of the line buffer control section is turned on, the interface control circuit 203 activates each circuit 205, 207, 209 through the signal path S201.

Variable speed step pulse generation control circuit 205
Immediately sends out one pulse S207 and causes the selector 211 to start the counting operation of the counter 206 with the register 215 selected. The counter 206 counts the clock generated from the basic clock S1 as the set value of the register 215. Variable speed step pulse generation control circuit 205
Sends out one pulse S207 each time a carry signal is output from the counter 206. When the number of pulses 207 sent reaches a predetermined number, the selector 211 is switched to the register 215 side from the time when the carry signal is output from the counter 206. . afterwards,
The signal S221 is turned on until the carry signal is output from the counter 206, and the output of the signal S208 from the delay recording control circuit 207 is suppressed. When the carry signal is output from the counter 206, the variable speed step pulse generation control circuit 205 turns off the signal S221 and stops the counter 206. The pulse 207 is transmitted as a recording variable speed step pulse S4.

The delay recording control circuit 207 is
The counter 208 starts counting with the selector 212 switched to the register 216 side. Counter 208 has register 21
A clock (not shown) internally generated from the image information synchronizing clock S8 is counted with the set value of 6 as an initial value, and when the full count is reached, a carry signal is output. The delay recording control circuit 207 switches the selector 212 to the register 215 side by the first carry signal of the counter 208, and outputs the signal S208 each time the carry signal is output. However, when the signal S211 turns on, the counter 208 is stopped and the signal S208 is not output.

When the signal 208 is output, the image width conversion control circuit 209 turns on the recording enable signal S211 and switches the selector 213 to the register 217 side to activate the counter 210. The counter 210 uses the value of the register 217 as an initial value and counts the same clocks as the counter 208. When the carry signal is output from the counter 210, the image width conversion control circuit 209 turns on the buffer output enable signal on the signal path S206 and, at the same time, switches the selector 213 to the register 218 side. The counter 210 starts the counting operation with the set value of the register 218 as an initial value. When the next carry signal is output, the image width conversion control circuit 209 turns off the buffer output enable signal (S206) and switches the selector 213 to the register 217. After that, when a carry signal is output from the counter 210, the image width conversion control circuit 209 causes the recording enable signal S211.
Is turned off and the counter 210 is stopped at the same time. The buffer output enable signal on the signal path S206 is transmitted to the line buffer control unit through the interface S12, and the image information for one line is input from the interface S12 during the ON period of the signal. This image information is sent from the interface control circuit 203 through the signal path S209 to the image information processing circuit.
Sent to 204.

The image information processing circuit 204 takes in the image information on the signal path S209 in synchronism with the internally generated clock from the image information synchronizing clock S8, and takes it in the signal path S2.
Output to 10. The interface control circuit 210 outputs the recording enable signal S211 and the image information (S210) to the recording interface S11.

The MPU controls the selector 109 through the register 103 at the constant speed step pulse S at the start of the receiving operation.
After switching to the 103 side and setting the registers 304 and 305,
The selector 302 selects the recording step pulse S6 through the register 301 to activate the counter 303, and the register 220 causes the circuits 205 and 20 in the image information control unit 2 to operate.
Stop 7,209. When the recording unit feeds the paper to the recording start position, the carry signal S13 of the counter 303 is sent.
Occurs and the MPU is interrupted. The MPU switches the selector 109 to the variable speed step pulse S4 side through the registers 103 and 220, and also makes each circuit 205, 207, 209 in the image information control unit 2 operable. Also M
The PU resets the registers 304 and 305 and restarts the counter 303 through the register 301. When the recording for one page is completed, M is generated by the interrupt of the carry signal S13.
The PU is notified. On the way, the MPU can read the value of the counter 303 by the registers 306 and 307 as needed and monitor the progress of the receiving operation.

Next, the operation in the copy mode will be described. The copy mode is executed on a line-by-line basis by a combination of a transmission operation and a reception operation.

That is, the read enable S20 from the reading unit.
2 as it is signal path S206, interface control circuit
It is sent to the line buffer control unit through 203 and the interface S12. The read image information is sent to the line buffer control unit through the signal path S203, the image information processing circuit 204, the signal path S205, the interface control circuit 203, and the interface S12.

On the other hand, when the output ready signal from the line buffer control unit is turned on and the interface control circuit 203 activates the signal path S201, the variable speed step pulse generation control circuit 205 and the image width conversion control circuit 209 receive the above-mentioned reception. Works like mode. However, the variable speed step pulse generation control circuit 205 does not select the register 214, and simultaneously sends the periodic pulses S204 and S207 determined by the selector 215. The image information output from the line buffer control is the interface S12, the interface control circuit 203,
Signal path S219, image information processing circuit 204, signal path S210,
Interface control circuit 202, interface S11
Is sent to the recording unit for recording.

The MPU selects the selector at the start of the copy operation.
108 and 109 are switched to the constant speed step pulse S103 side, and the counter control circuit 3 is controlled similarly to the start of the operation in the transmission mode (or the reception mode). When the carry signal S13 is generated at the end of reading one line, the MPU switches the input selection of the selectors 108 and 109 and enables the circuits 205 and 209 of the image information control unit 2 to operate.
The subsequent control by the MPU is the same as in the case of the reception mode or the transmission mode described above.

The MPU may use a counter 303 if necessary.
Can also be caused to count the counting clock S7.

The image width conversion processing in each of the above operation modes will be described with reference to the enable signal waveform diagram of FIG.

FIG. 5A shows an enable signal waveform diagram in the case of no processing, which corresponds to the case where the delete / addition width is designated as 0 by the register 217 in the transmission mode, the reception mode and the copy mode. In the transmission mode (and the transmission operation in the copy mode), i is the read enable signal S20.
2 and ii correspond to the buffer input enable signal (S206), respectively. α is the effective width specified by the register 218. In receive mode, i is the input enable signal (S20
6) and ii correspond to the recording enable signal S211.

FIG. 5B is a waveform diagram of the enable signal in the case of reducing the image width, which corresponds to the transmission mode. iii is a read enable signal S202, and iv is a buffer output enable signal (S206). e is the deletion width specified by the register 217, and f is the effective width specified by the register 218.

FIG. 5C is a waveform diagram of the enable signal in the case of the image information adding process, which corresponds to the recording operation in the reception mode and the copy mode. v is an input enable signal (S206), and vi is a recording enable signal S211. g is an additional width specified by the register 217, and h is an effective width specified by the register 218. In this way, the image width conversion process is executed by controlling the enable signal. However, each enable signal is shown ignoring the delay in the image information control unit 2, and strictly speaking, delay correction is performed.

Next, the sub-scanning control in the image information control unit 2 will be further described. FIG. 6 is an explanatory diagram of sub-scanning control for the printing unit. In the figure, A is a step pulse for sub-scanning drive of the recording portion, B is a response of the sub-scanning drive system to the step pulse A (displacement-time characteristic).
Indicates. c is a recording enable signal.

As shown in the figure, the response of the sub-scanning drive system to the application of the step pulse A is delayed as shown by B. This response delay time differs depending on each sub-scanning drive system.
Correction of this response delay is one of the sub-scanning control functions. That is, the appropriate response delay time is set in the register 21.
It is set at 6, and the supply opening of the recording enable signal c (S211 in FIG. 3) is delayed by the set time 1. By this timing correction, the arrangement of the recording dot row of each line is changed to D
Can be even as shown in.

Further, a stop waiting time k is required after the supply of the step pulse A is stopped until the sub-scanning drive system is completely stopped, and if the recording is restarted during this time, the recording operation becomes unstable. Since this stop waiting time k also changes depending on the individual sub-scanning drive system, it is necessary to control the timing of the step pulse A and the recording enable signal c. The register 214 is set with this waiting time k,
The retransmission of the step pulse A is made to wait for the time set in the register 214 (obviously, the output of the enable signal is also made to wait).

Furthermore, it is necessary to control the cycle j of the step pulse A and the cycle m of the recording enable signal c according to the recording speed and the like. Register 215 sets this cycle.
The period of the step pulse A and the recording enable signal c is controlled according to the set value.

The image information control unit 2 has a function of reducing an image in both the main and sub scanning directions. This reduction processing is performed in the transmission mode and the copy mode only when the reduction instruction is set in the register 202 from the MPU.
The reduction processing in the main scanning direction is executed by the image information processing unit 204,
In the transmission mode, it is performed for the read image information sequence, and in the copy mode, it is performed for the image information sequence input from the line buffer control unit. Reduction in the sub-scanning direction is performed by the sub-scanning reduction control circuit.
219 and the image width conversion control circuit 209. That is, in the transmission mode, the image width conversion control circuit 209 suspends the transmission of the buffer input enable signal (S206) for one line out of seven lines of the read image information. As a result, the read image information is thinned out not to be sent to the line buffer control unit by one line per seven lines. That is, 7
Each line is reduced by one line in the sub-scanning direction.

In the copy mode, the image width conversion control circuit 209 is used when the read image information is transferred to the line buffer control unit.
Similar thinning is performed by. On the other hand, when the image information (reduced) input from the line buffer control unit is sent to the recording unit for recording, the sub-scanning reduction control circuit 219 sends the variable speed step pulse S4 for recording for one line per seven lines. stop. In this way, the reduction in the sub-scanning direction in the copy mode is executed.

As described above in detail, according to the present embodiment, the cycle and timing of the step pulse, and the transfer of the image information between the reading unit and the recording unit and the line buffer control unit are set by the register setting from the MPU. The control method can be arbitrarily changed. Further, the transfer rate of the image information from the line buffer control unit to the recording unit is also determined by the image information synchronization clock (S
It can be changed arbitrarily from the MPU by setting the cycle of 8). Since the synchronous clock of the read image information is generated based on the black input from the reading unit, the read image information can be transferred at a speed adapted to the reading speed of the reading unit.
Further, even if the cycle or timing of the step pulse is arbitrarily changed, the step pulse is counted by the counter, so that the paper feeding management of the recording unit and the reading unit and other time management for communication control can be performed without any trouble. be able to. Therefore, the facsimile control apparatus of the present embodiment can be commonly used for different types of facsimile machines, and is extremely versatile. Further, the facsimile controller of this embodiment is M
It is possible to perform various image width conversion processing and reduction processing by register setting from the PU, and it is possible to cope with multifunctionalization of the facsimile apparatus.

The present invention is not limited to the configuration of the present embodiment, and it goes without saying that it can be appropriately modified and implemented. Further, the facsimile control device according to the present invention is
It can be realized by using a disk lead component or can be realized as a one-chip or multi-chip integrated circuit.

[0048]

As is apparent from the above description, according to the present invention, both the driving pulse width of the stepping motor for conveying the original document from the microcomputer and the driving pulse width of the stepping motor for conveying the recording paper are the same. It is possible to reduce the circuit scale and to provide a versatile read control device which can be commonly applied to different types of facsimile machines by arbitrarily setting the storage means.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a facsimile control apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a clock control unit in FIG.

3 is a block diagram showing a detailed configuration of an image information control unit in FIG.

FIG. 4 is a block diagram showing a detailed configuration of a counter control unit in FIG.

FIG. 5 is a waveform diagram of an enable signal for explaining the image width conversion processing.

FIG. 6 is an explanatory diagram of sub-scanning control for a recording unit.

[Explanation of symbols]

 1 clock control unit 2 screen information control unit 3 counter control unit 4 interface control unit 103, 105, 107, 214 to 218, 301, 304 to 307 register 104, 106, 206, 210, 303 counter 108, 109, 211 to 213 , 302 selectors 201 to 203 interface control device 204 image information processing circuit 205 variable speed step pulse generation control circuit 207 delay recording control circuit 209 image width conversion control circuit S10 interface with reading unit S11 interface with recording unit S12 line buffer control unit Interface S14 MPU data bus S15 MPU interface S16 internal bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Yamatani 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd.

Claims (2)

[Claims] 1. A stepping motor based on a storage means for holding a predetermined value arbitrarily set by a microcomputer, and a predetermined value read from the storage means both at the time of carrying a document and at the time of carrying a recording sheet. And a means for outputting a drive signal of the facsimile control apparatus. 2. The facsimile control apparatus according to claim 1, wherein the predetermined value is a value corresponding to a drive pulse width of the stepping motor.