JPH10209310A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep good the characteristics of a bipolar transistor, by forming an emitter and collector regions on a base region with specified spacing, and providing an electrode on the base region between the emitter and collector region, using a conductive film formed through an insulating film with the same potential given to the electrode. SOLUTION: On the base region 4 surface between an emitter and collector regions 6, 7 a thin Si oxide film 14 is formed when forming a silicon oxide film as a gate insulation film in a CMOS step. On the film 14, a polysilicon electrode 18 is formed to cover the base region 4 with a polysilicon film formed when forming a conductive polysilicon film for a gate electrode in the CMOS step and connected so as to have the same electric potential as that of the emitter region 6. This eliminates the influences of the surface level and surface crystal defects on the minority carrier, thereby keeping good the transistor characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device to which a Bi-CMOS process is applied, and more particularly to a lateral bipolar transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the advance of semiconductor technology, the development of ICs in which analog circuits and digital circuits are integrated on the same semiconductor substrate has been activated. This includes bipolar and CMOS
(Bi-CMO) on the same semiconductor substrate
S process). The conventional lateral PNP transistor (hereinafter referred to as L
-PNP) will be described with reference to FIG. In the figure, 1 is a P ⁻ -type single crystal silicon substrate, 2 is an N ⁺ -type buried layer, 3 is an element isolation region composed of a P ⁻ -type epitaxial layer, 4 is a base region formed by an N ⁻ -type diffusion region, 5 is a base contact region formed of an N ⁺ type diffusion region, 6 and 7 are emitter and collector regions each formed of a P ⁺ type diffusion region, 8 is a metal film covering the base surface, and 9 is an N ⁻ type diffusion region. N-type well region, 10 is a well contact region formed by an N ⁺ -type diffusion region, 11 and 12 are drain and source regions each formed of a P ⁺ -type diffusion region, 13 is a gate electrode made of polysilicon, and 14 is a thin silicon oxide. Reference numeral 15 denotes a thick LOCOS oxide film, 16 denotes a metal wiring, and 17 denotes an interlayer insulating film between the polysilicon film and the metal wiring.

[0003] Next, L by the Bi-CMOS process
-A method for manufacturing PNP will be described with reference to FIGS. 6 (a) to 6 (d) and FIGS. 7 (a) to 7 (d). An N ⁺ type buried layer 2 and a P ⁻ type epitaxial layer 3 are sequentially formed on a P ⁻ type single crystal silicon substrate 1 (FIG. 6A). An N ⁻ type base region 4 and an N ⁻ type well region 9 are formed in the P ⁻ type epitaxial layer 3 by diffusion (FIG. 6B). After a thin silicon oxide film 14, which is an insulating film, is formed on the surface of the substrate by thermal oxidation, a region other than a predetermined region is further field-oxidized to form a thick LOCOS oxide film 15 (FIG. 6C). A polysilicon film is laminated on the thin silicon oxide film 14, and the gate electrode 13 is formed by etching.
(D)).

[0004] A resist film 19 is coated, and a diffusion window for forming a base contact region and a well contact region is opened in a predetermined region on the substrate by using a photoetching technique. Using this resist film 19 as an implantation mask, high-concentration N ⁺ -type impurities (for example, phosphorus) are selectively ion-implanted. After removing the resist film 19,
A resist film is formed again, and a diffusion window for forming an emitter region, a collector region, a source region, and a drain region is similarly opened. Using this resist film as an implantation mask, high-concentration P ⁺ -type impurities (for example, boron) are selectively ion-implanted. At this time, the gate electrode 13 is used as a part of the mask (FIG. 7A).

After the resist film is stripped, the substrate is subjected to a heat treatment to diffuse impurities introduced into the emitter region, the collector region, the drain region, the source region, the base contact region and the well contact region. Collector electrode 7, Drain electrode 11, Source electrode 1
2. The base contact region 5 and the well contact region 10 are formed. Further, an interlayer insulating film 17 for insulating between the gate electrode 13 made of a polysilicon film and the metal wiring 16 is formed over the entire surface of the substrate (FIG. 7B).

A contact window is opened in the interlayer insulating film 17 by using a photo-etching technique (FIG. 7C). An L-PNP can be formed by forming a metal wiring 16 made of an aluminum alloy wiring (FIG. 7D).

Considering the operation of the L-PNP, minority carriers injected from the emitter region 6 into the base region 4 move to the collector region 7 due to the electric field between the emitter and the collector. The minority carriers move near the surface of the base region 4 between the emitter region 6 and the collector region 7. In addition, trapping centers such as surface levels and surface crystal defects exist on the surface of the silicon crystal, and minority carriers moving there are easily affected by these trapping centers, and the characteristics are unstable due to the long base width. Easy to be. For this reason, in the case of the L-PNP manufactured by the conventional bipolar technology, the metal wiring 16 connected to the emitter region 6 is expanded,
By covering the surface of the base region 4 between the emitter region 6 and the collector region 7 with the metal film 8 via the thin silicon oxide film 14 and the interlayer insulating film 17, a storage layer composed of majority carriers is formed on the base surface at the emitter potential. In addition, minority carriers are kept away from surface levels and surface crystal defects to remove the instability.

[0008]

However, a conventional L-type semiconductor device manufactured by such a Bi-CMOS process has been proposed.
In the case of PNP, since the thick interlayer insulating film 17 is interposed between the metal film 8 covering between the emitter region 6 and the collector region 7 and the surface of the base region 4, the effect of forming a storage layer on the base surface is reduced, and It is not enough to eliminate the effects of levels and surface crystal defects. The current amplification factor (hf) of the conventional L-PNP actually manufactured by the Bi-CMOS process
When e) was obtained, the result as shown in FIG. 7 was obtained. Although this should originally show a flat characteristic like a dotted line, as shown by a solid line, hfe decreases on the low current side, and the degree of the decrease varies from sample to sample.
These have a negative effect on the transistor operation due to the reduced effect of forming the storage layer on the base surface, which is a problem as a characteristic of the transistor.

In order to solve this problem, the interlayer insulating film 17 between the emitter region 6 and the collector region 7 may be eliminated. However, an increase in the number of dedicated masks and steps increases the manufacturing cost. A new problem arises.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and it is desirable to maintain good characteristics of a bipolar transistor manufactured by a Bi-CMOS process, and to reduce steps and manufacturing costs. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device in which a bipolar transistor and a CMOS transistor are formed on the same semiconductor substrate. A base region of one conductivity type, an emitter region and a collector region of the other conductivity type formed at a predetermined interval on the base region, and a CMOS transistor on the base region between the emitter region and the collector region. The gist of the present invention is to have an electrode formed of a conductive film with a thin insulating film the same as the gate insulating film and having the same potential as the emitter region. With this configuration, the effect of forming the accumulation layer on the surface of the base region is increased, and the effects of surface states and surface crystal defects can be eliminated.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the insulating film is a silicon oxide film, and the conductive film is a polysilicon film. With this configuration, it is possible to achieve high integration with ease of manufacture.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
In a method of manufacturing a semiconductor device in which a bipolar transistor and a CMOS transistor are formed on the same semiconductor substrate, a thin insulating film is formed simultaneously with a gate insulating film for the CMOS transistor on a base region of one conductivity type constituting the bipolar transistor. And forming an electrode on the insulating film to give the same potential as the emitter region of the bipolar transistor at the same time as forming the gate electrode for the CMOS transistor. With this configuration, it is possible to form a thin insulating film and an electrode on the base region of the bipolar transistor without increasing the number of masks and steps.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the other part of the base region is implanted with an impurity of the other conductivity type by using the electrode as a part of a mask, and the emitter region and the collector are separated by a predetermined distance defined by the electrode width. The point is to have a step of forming a region. With this configuration, the electrode is not misaligned with respect to the emitter region and the collector region, and the electrode is accurately formed on the base region between the emitter region and the collector region.

[0015]

According to the semiconductor device of the first aspect, the bipolar transistor has a base region of one conductivity type,
An emitter region and a collector region of the other conductivity type formed at a predetermined interval on the base region; and a CMO on the base region between the emitter region and the collector region.
Since an electrode formed of a conductive film through the same thin insulating film as the gate insulating film of the S transistor and having the same potential as the emitter region is provided, the effect of forming a storage layer on the base surface is increased, and the surface level and the Since the influence of surface crystal defects on minority carriers can be eliminated, favorable transistor characteristics can be maintained.

According to a third aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a thin insulating film simultaneously with a gate insulating film for a CMOS transistor on a conductive type base region forming a bipolar transistor; Forming an electrode for giving the same potential as the emitter region of the bipolar transistor at the same time as forming the gate electrode for the CMOS transistor on the insulating film. Can be reduced.

According to the semiconductor device manufacturing method of the present invention, the other conductivity type impurity is implanted into the base region using the electrode as a part of the mask, and at a predetermined interval defined by the electrode width. Since the step of forming the emitter region and the collector region is provided, an electrode is accurately formed on the base region between the emitter region and the collector region, and the effect of forming the storage layer on the surface of the base region and the shielding effect can be further enhanced. .

[0018]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. In this embodiment mode, the gate electrode in the CMOS process will be described as a polysilicon film, but any conductive film that satisfies the gist of the present invention may be used, and is not limited to the polysilicon film. 1 to 3, the same or equivalent members as those in FIG. 5 are denoted by the same reference numerals as those described above, and redundant description will be omitted.

First, the configuration of an L-PNP manufactured by Bi-CMOS will be described with reference to FIG. In the present embodiment, on the surface of base region 4 between emitter region 6 and collector region 7, only thin silicon oxide film 14, which is formed simultaneously with the silicon oxide film as the gate insulating film in the CMOS process, is formed. . Similarly, a polysilicon electrode 18 is formed on the thin silicon oxide film 14 so as to cover the base region 4 with a polysilicon film formed simultaneously with a polysilicon film which is a conductive film for a gate electrode in a CMOS process.
Are formed. The polysilicon electrode 18 is electrically connected so as to have the same potential as the potential of the emitter region 6.

As described above, the L-PNP of the present embodiment
Is to form a polysilicon electrode 18 on the surface of the base region 4 between the emitter region 6 and the collector region 7 via the thin silicon oxide film 14 and make the polysilicon electrode 18 the same potential as the emitter potential. The effect of forming a storage layer in the base region can be enhanced, and the effect of the trapping center, which adversely affects minority carriers, can be eliminated, so that the characteristics of the transistor can be kept good. FIG. 4 shows an example of L-PNP measurement results to which the present invention is applied. From this result, it can be seen that flat hfe characteristics can be obtained even on the low current side.

Next, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 2A to 2D and 3A to 3D. An N ⁺ type buried layer 2 and a P ⁻ type epitaxial layer 3 are sequentially formed on a P ⁻ type single crystal silicon substrate 1 (FIG. 2A). P ^- type epitaxial layer 3
Next, an N ⁻ type base region 4 and an N ⁻ type well region 9 are formed by diffusion (FIG. 2B). After a thin silicon oxide film 14, which is an insulating film, is formed on the substrate surface by thermal oxidation, field oxidation is performed further on a region other than a predetermined region to form a thick LOCOS oxide film 15 (FIG. 2C). A polysilicon film is stacked on the thin silicon oxide film 14, and a polysilicon electrode 18 and a gate electrode 13 are formed by etching (FIG. 2D).

A resist film 19 is coated, and a diffusion window for forming a base contact region and a well contact region is formed in a predetermined region on the substrate by using a photoetching technique. Using this resist film 19 as an implantation mask, high-concentration N ⁺ -type impurities (for example, phosphorus) are selectively ion-implanted. After removing the resist film 19,
A resist film is formed again, and a diffusion window for forming an emitter region, a collector region, a source region, and a drain region is similarly opened. Using this resist film as an implantation mask, high-concentration P ⁺ -type impurities (for example, boron) are selectively ion-implanted. At this time, the polysilicon electrode 1
8 is used as a part of the mask (FIG. 3A).

After the resist film is stripped, the substrate is subjected to a heat treatment to diffuse the impurities introduced into the emitter region, the collector region, the drain region, the source region, the base contact region and the well contact region. Collector region 7, drain region 11, source region 1
2. The base contact region 5 and the well contact region 10 are formed. Further, an interlayer insulating film 17 for insulating the polysilicon electrode 18 and the gate electrode 13 from the polysilicon film and the metal wiring 16 is formed on the entire surface of the substrate (FIG. 3B).

A contact window is opened in the interlayer insulating film 17 by using a photoetching technique (FIG. 3C). An L-PNP can be formed by forming the metal wiring 16 made of an aluminum alloy film (FIG. 3D).

As described above, according to the method of manufacturing a semiconductor device of the present embodiment, the step of forming the polysilicon electrode 18 on the surface of the base region 4 via the thin silicon oxide film 14 is performed by a thin CMOS process. By sharing the step of forming the gate oxide film and the step of forming the polysilicon film for the gate electrode, the number of masks and steps does not increase, and thus the manufacturing cost does not increase. Further, since the polysilicon electrode 18 is used as a mask for introducing impurities for forming the emitter region 6 and the collector region 7, no mask shift occurs.

In the above embodiment, L-PNP
Has been described, but L-type with N-type and P-type interchanged
Similar functions and effects can be obtained with NPN.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a process chart for describing an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a process drawing following FIG. 2 for describing the embodiment of the method for manufacturing a semiconductor device.

FIG. 4 is a diagram for explaining the operation and effect of the present embodiment.

FIG. 5 is a longitudinal sectional view of a conventional semiconductor device.

FIG. 6 is a process chart for describing a method of manufacturing the semiconductor device in FIG.

FIG. 7 is a process chart for describing a method of manufacturing the semiconductor device in FIG.

FIG. 8 is a diagram illustrating characteristics of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 4 Base region 6 Emitter region 7 Collector region 11 Drain region 12 Source region 13 Gate electrode 14 Thin silicon oxide film (insulating film) 18 Polysilicon electrode

Claims (4)

[Claims] In a semiconductor device having a bipolar transistor and a CMOS transistor formed on the same semiconductor substrate, the bipolar transistor is formed with a base region of one conductivity type and at a predetermined interval on the base region. On the other hand, a conductive film is formed on the base region between the emitter region and the collector region by a conductive film via the same thin insulating film as the gate insulating film of the CMOS transistor. A semiconductor device having an electrode to which a potential is applied. 2. The semiconductor device according to claim 1, wherein said insulating film is a silicon oxide film, and said conductive film is a polysilicon film. 3. A method of manufacturing a semiconductor device in which a bipolar transistor and a CMOS transistor are formed on the same semiconductor substrate, wherein a bipolar transistor and a gate insulating film for the CMOS transistor are simultaneously formed on a base region of one conductivity type constituting the bipolar transistor. Forming a thin insulating film, and forming an electrode on the insulating film to give the same potential as the emitter region of the bipolar transistor at the same time as forming the gate electrode for the CMOS transistor. Semiconductor device manufacturing method. 4. A step of implanting impurities of the other conductivity type into the base region using the electrode as a part of a mask to form an emitter region and a collector region at predetermined intervals defined by the electrode width. 4. The method for manufacturing a semiconductor device according to claim 3, wherein: