JPH10209286A - Micro cell and its layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a wiring from an input and an output terminals exsisting in a micro cell to the outside of the micro cell from becoming unwired due to a wiring and a wiring forbidden region in the micro cell. SOLUTION: In basic function cells having I/O terminals which are led out outside a micro cell, basic function cells of the same function which have I/O terminals of the same leading out direction are made groups. After the number of arrangement steps are decided, the basic function cells having the same function are arranged. In order to lead out wirings from the I/O terminals outside the micro cell, a wiring forbidden region wherein the equal number of wirings to the number of arrangement steps is possible is formed in the periphery of the I/O terminals, and wiring for connecting the parts between the basic function cells in the micro cell is performed. Since wiring between the micro cells is performed after the wiring forbidden region is eliminated, wirings can be easily led out from the micro cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a macro cell and a layout method thereof, and more particularly, to an ASIC (Application Speech) such as a gate array and a cell-based IC.
The present invention relates to a macro IC having a macro cell composed of basic function cells such as a NAND gate and a flip-flop in a semiconductor integrated circuit (IC) and a layout method thereof.

[0002]

2. Description of the Related Art Recently, the circuit scale of a semiconductor integrated circuit has been rapidly increasing, and accordingly, it is common to design chips hierarchically. Referring to FIG. 5, a chip 100 includes a macro cell 101 including a PLL 201, a multiplier 202, a memory block 102 including a RAM 203 and a ROM 204, a user logic circuit 103 that can be freely laid out by a designer, and an input / output buffer. I /
It is composed of an O block 104.

Further, a PLL 201, a multiplier 202, and a user logic circuit 103 are composed of basic function cells 301 such as NAND gates and flip-flops. In a gate array, the basic function cells 301 have a basic unit of 2 NAND gates and the like. The basic cell 401 is configured by using a basic cell row in which a large number of basic cells 401 are repeatedly arranged in a lattice.

As the circuit scale of the semiconductor integrated circuit increases, the circuit scale of the macro cell 101 is also increasing.
It is important to efficiently arrange and wire the devices by using them.

Next, a conventional layout method of the macro cell 101 will be described with reference to the drawings.

FIG. 6 is a flowchart showing a conventional layout method of the macro cell 101.

First, in step S1, master information 1 including base information of a gate array determined by a process and the number of mountable gates, external information of a basic function cell 301, position information on contacts and through holes, and the like, Circuit connection information 2 between basic function cells 301 constituting the macro cell 101 and wiring prohibition information 3 for specifying a wiring prohibition area when wiring between the basic function cells 301 inside the macro cell 101 are input. The cells 301 are automatically arranged with reference to a grid defined on the base.

Next, in step S2, after a schematic wiring between the basic function cells 301 is performed, a step S3 is performed.
In the detailed wiring described above, all wiring between the basic function cells included in the macro cell 101 is automatically performed using a computer.

Next, in step S4, the layout designer determines whether the input / output terminal of the macro cell 101 created in step S3 can be wired outside the macro cell 101 or not.
The determination is made while looking at the T screen or the monitor drawing. If it is determined that wiring is possible, the macro cell data 4 is created. If it is determined that wiring cannot be performed, it is determined in step S5 whether manual correction is possible.

In other words, if manual correction is possible, the arrangement and wiring of the basic function cell 301 relating to the lead-out wiring path from the input / output terminal of the macro cell 101 to the outside of the macro cell 101 are partially corrected in step S6. Thus, the wiring can be drawn out of the macro cell 101 from the input / output terminal of the macro cell 101, and the macro cell data 4 is created.

If the wiring cannot be drawn out of the macro cell 101 from the input / output terminals in the partial layout correction in step S5, the flow returns to step S1 to return to all the basic function cells 30 included in the macro cell 101.
The arrangement of 1 was redone.

Recently, the number of basic function cells 301 included in the macro cell 101 is rapidly increasing, and in many cases, wiring cannot be drawn out of the macro cell 101 from the input / output terminals of the macro cell 101. For this reason, the process from step S1 to step S5 in FIG. 6 is repeated many times, and the design period of the macro cell 101 is very long.

Next, a problem in step S4 of the layout design flow of FIG. 6 will be described with reference to FIGS.

FIG. 7 shows basic function cells 11-1.
FIG. 8 is a schematic plan view showing a macro cell 101A designed using 3, 21 to 23, 31 to 33, and the like. FIG. 8 is an enlarged view of a part of the basic function cells 11 to 13, 21 to 22, and 31 showing the inside of the macro cell 101A. A part of wiring of 61-
FIG. 65 is a schematic plan view shown with 65.

In FIG. 7, a basic function cell 1
Reference numerals 1 to 13, 21 to 23, and 31 respectively designate wiring prohibited areas 41 to 44 and input / output terminals 51 to 5 of the macro cell 101A.
6 are provided.

In FIG. 8, since the basic function cell 11 is located at the lower left corner of the macro cell 101A, the wiring is provided from the input / output terminal 51 located inside the basic function cell 11 to the outside of the macro cell 101A on the lower side or the left side. It is desirable to draw out. Similarly, from the input / output terminals 52, 53, the input / output terminals 54,
It is desirable that the wiring be drawn from the input / output terminal 56 to the left or the lower side, respectively.

By the way, it is possible to lead the wiring from the input / output terminals 51 and 52 to the left and lower sides of the macrocell 101A by the wirings 71 and 72, respectively. Can not be pulled out to the side. The input / output terminals 54 and 55 are connected to the wiring 6 respectively.
1, 64 and wirings 62, 65,
The wiring cannot be drawn out of the macrocell 101A.

As described above, the input / output terminals 51 to 56 for leading out the macro cell 101A existing in the macro cell 101A are connected to the wiring prohibited areas 41 to 44 and the basic function cell 11 constituting the macro cell 101A.
, 13, 21 to 23, 31 to 33, there is a problem that the wiring is restricted by the internal wiring and cannot be drawn out of the macro cell 101A.

As a method for solving the above-mentioned problem, Japanese Patent Laid-Open No. Hei. The technology to be set is described. However, in this known example,
This technique is applied to the macro cell 101 in order to surround a pin in a group and to set a region including a position where lead lines from all the pins in the group can make through holes as a wiring prohibited region.
A, the input / output terminal 5 in the macro cell 101A
There is a problem that automatic wiring processing from 1 to 56 to the outside of the macro cell 101A cannot be performed.

That is, if a wiring prohibited area is provided for the macro cell 101A in addition to the wiring prohibited areas 41 to 44, for example, so as to cover the basic function cells 11 to 13, 21 to 23, and 31 to 33, an automatic computer is used. It is impossible to generate a wiring from the input / output terminals 51 to 56 to the outside of the macrocell 101A.

[0021]

In the above-described conventional layout method of a macro cell, the circuit connection information taken in when arranging the basic function cell includes a circuit connection for wiring from an input / output terminal in the macro cell to the outside of the macro cell. Due to the lack of information, there is a problem that when performing general wiring in the macro cell, wiring cannot be performed from the input / output terminals in the macro cell to the outside of the macro cell.

Further, when the input / output terminals of the macro cell cannot be wired outside the macro cell, all the basic function cells included in the macro cell are rearranged.
There is a problem that the design period is significantly increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a macro cell capable of wiring outside the macro cell even if the degree of integration of the macro cell is increased, and a layout method thereof.

It is another object of the present invention to provide a macro cell layout method which enables wiring from an input / output terminal present in the macro cell to the outside of the macro cell and enables efficient layout of the macro cell. It is in.

[0025]

Therefore, a macro cell according to the present invention is a macro cell comprising a plurality of basic function cells which are basic elements of a logic circuit, wherein the macro cell is an input / output terminal for connecting to the outside of the macro cell. And a wiring prohibited area for drawing a wiring from the input / output terminal to the outside of the macro cell, wherein the wiring prohibited area is an upper side of the basic function cell having the input / output terminal near the input / output terminal. It is characterized in that it is provided so as to be vertical or transverse to the lower side or the left side and the right side.

Furthermore, the method of laying out a macro cell according to the present invention provides a specific function in which a plurality of basic function cells, which are basic elements of a logic circuit, are formed on a semiconductor substrate, and the basic function cells are wired based on circuit connection information. Extracting the basic function cell having an input / output terminal connected to the outside of the macro cell,
Determining the direction of pulling out the input / output terminal;
Grouping the basic function cells having the input / output terminals in the same lead-out direction, arranging the same group of the basic function cells, and proximate to the input / output terminals present in the arranged basic function cells; A step of providing a wiring prohibited area in the macro cell and performing wiring in the macro cell.

[0027]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a first embodiment of a macro cell and a layout method thereof according to the present invention, and FIG. 2 extracts a portion related to the present embodiment of a macro cell 101B designed based on the flowchart of FIG. FIG. 2 is a schematic plan view shown as an example. Note that components and steps common to the conventional example are denoted by common reference characters / numbers.

First, in step S11, a basic function cell having an input / output terminal connected to the outside of the macro cell 101B is extracted from among the basic function cells constituting the macro cell 101B.

Next, in step S12, master information 1 including base information of the gate array determined by the process and the number of mountable gates, outer shape information of the basic function cell 301, position information on contacts and through holes, etc. When wiring between the basic function cells 301 is performed inside the basic cell 101B, the macro cell 101B
Which side of the upper side, lower side, left side and right side of the macro cell 101B
It is determined whether the wiring is drawn out of B. For example, the first
First, the drawing direction is determined on the lower side of the macro cell 101B.

Next, in step S13, basic function cells having input / output terminals in the same drawing direction are grouped together. The grouping of each of the basic function cells into upper, lower, left, and right sides in the drawing direction is performed manually by a layout designer based on the floor plan, connection information between macro cells, and connection information between macro cells and I / O cells 104. Determined or automatically determined based on the above information.

Next, the number of arranging stages of the basic function cells grouped in step S14 is determined.
The basic function cells grouped in 15 are arranged in the macro cell arrangement area. For example, in FIG. 2, the exclusive OR gates 11a to 11c, the flip-flops 12a to 12c, and the adders 13a to 13c each have a vertically stacked configuration of three stages. However, in addition to the exclusive OR gates 11a to 11c, three more exclusive exclusive gates are provided. When the OR gates 11d to 11f are drawn out to the lower side from the input / output terminals, the exclusive OR gates 11a to 11 of a three-stage vertically stacked structure are used instead of the six-stage vertically stacked structure.
Exclusive OR gates 11d to 11f having a three-stage vertically stacked configuration are arranged next to c.

In addition to the flip-flops 12a to 12c, when the two flip-flops 12d and 12e are drawn out from the input / output terminals to the lower side, the flip-flops 12d and 12e are arranged in a two-stage vertically stacked configuration. It is arranged next to the flip-flops 12a to 12c of the configuration.

As described above, the number of arrangement steps is determined by further dividing the group so that the height of the arrangement steps of the grouped basic function cells is as uniform as possible.

Next, in step S16, the same number of wiring prohibited areas as the number of arrangement stages are set around the input / output terminals. In FIG. 2, exclusive OR gates 11a to 11c, flip-flops 12a to 12c, adders 13a to 13c
Are three-stage vertically stacked configurations, and have input / output terminals 51
a to 51c, 52a to 52c, and 53a to 53c, the wires are drawn out to the lower side, respectively.
80d, 81a to 81d and 82a to 82d are each 3
The exclusive OR gates 11a to 11c, the flip-flops 12a to 12c, and the adders 13a to 13c have the same wiring width. Exclusive OR gates 11b and 11c, flip-flop 1
2b, 12c and the placement prohibited areas respectively arranged in the adders 13b, 13c are placement prohibited areas 80a-80.
d, 81a to 81d and 80a to 80d, respectively.

The wiring prohibited areas 80b, 80d, 81
b, 81d, 82b, and 82d are conventional wiring prohibition information 3
In addition to the wiring prohibited areas 41 to 43 based on the I / O terminals 51a, 52a, 53a, the wiring prohibited areas 80a, 80
This is a wiring prohibited area used to draw wiring to the lower side of the macro cell 101B via 0c, 81a, 81c, 82a, 82c.

Next, in step S17, the macro cell 101
It is determined whether or not all the basic function cells having input / output terminals connected to the outside of B are arranged in the macro cell 101B. First, since a group of basic function cells that lead out wiring in the lower side direction of the macro cell 101B is arranged, next, the basic function cell that draws out wiring in the upper side direction of the macro cell 101B is arranged by the above-described method. Similarly, steps S12 to S16 are repeated for the left side and the right side.

Next, after the general wiring is performed in step S2 as in the prior art, the detailed wiring is performed in step S3, and in step S18, the wiring prohibited area set in step S16 is released and the macro cell layout data 4 is created. .

Therefore, when laying out the chip 100 using the macro cell 101B, the memory cell 102, the user logic circuit 103, and the I / O cell 104, the input / output terminals 51
a to 51c, 52a to 52c, 53a to 53c to the wiring prohibited areas 80a to 80d, 81a of the macro cell 101B.
Through the macro cell 101B via the
Can be easily drawn out to the lower side. Further, the basic function cell is repeatedly arranged by trial and error until the input / output terminal can be drawn out of the macro cell, thereby solving the problem of the conventional example that the design period is greatly lengthened.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a flowchart showing a second embodiment of the macro cell and the layout method thereof according to the present invention, and FIG. 4 extracts a portion related to the present embodiment of the macro cell 101C designed based on the flowchart of FIG. FIG. 2 is a schematic plan view shown as an example.

First, in step S19, the designer manually places all basic function cells constituting the macro cell 101C in the arrangement area of the macro cell 101C based on the master information 1, the circuit connection information 2, and the wiring prohibition information 3. Or automatically by using a computer.

Next, at step S11, the macro cell 101
A basic function cell having an input / output terminal connected to the outside of C is extracted. In FIG. 4, 301A, 301B,
An input / output terminal 5 for connecting the three basic function cells 301C to the outside of the macrocell 101C.
7, 58, 59.

Next, at step S20, the input / output terminal 57
The wiring levels of the horizontal and vertical wiring prohibited areas provided in the area extending from the vicinity of the area # 59 to the respective sides of the macrocell 101C are determined. For example, the second and third metal wiring layers are used in the horizontal and vertical directions.

Next, in step S21, a wiring prohibited area connecting the left and right sides of the macro cell 101C and the input / output terminal is provided on the left and right of the input / output terminal. In FIG.
7 are provided with wiring prohibited areas 91a on the left and right sides. Similarly, wiring prohibited areas 91 are provided on the left and right of the input / output terminals 58 and 59, respectively.
b, 91c.

Next, in step S22, step S22 is executed.
Similarly to the case of FIG.
A wiring prohibited area connecting the upper side and the lower side to the input / output terminal is provided. In FIG. 4, a wiring prohibited area 90c is provided above and below the input / output terminal 57. Similarly, wiring prohibited areas 90a and 90b are provided above and below the input / output terminals 58 and 59, respectively. In addition, 45 to 48 are wiring prohibited areas in the basic function cell arranged based on the wiring prohibited information 3.

Next, in step S23, steps S21 and S
It is determined whether or not all the setting of the wiring prohibited area in 22 is completed. If not completed, the process returns to step S21 to continue the setting of the wiring prohibited area, and if completed, the general wiring of step S2 is performed. The subsequent steps are the same as those in the first embodiment, and a description thereof will be omitted.

In this embodiment, the wiring channels leading out of the macro cell 101C are set as the wiring prohibited areas 90a to 90c and the wiring prohibited areas 91a to 91c on the upper, lower, left and right sides of the input / output terminals 57 to 59. The entire wiring group drawn from the input / output terminal to the outside of the macrocell 101C can be drawn with shorter wiring, which is extremely effective for a macrocell that operates at high speed.

The input / output terminal 5 of the macro cell 101C
Since wiring can be drawn out from 7 to 59 to any of the upper, lower, left and right sides, the macro cell 1
The wiring between the 01C and the other macro cells 101, the memory cells 102, and the I / O cells 104 can be easily performed, and the wiring length can be reduced, so that high-speed operation as a chip is possible.

[0050]

As described above, in the macro cell and the layout method thereof according to the present invention, the wiring between the basic function cells constituting the macro cell is provided by providing the wiring prohibited area near the input / output terminal for wiring to the outside of the macro cell. Therefore, it is possible to easily draw a wiring from the input / output terminal to the outside of the macro cell.

Further, since there is no need for manual correction in the layout design of the macro cell, the design period of the macro cell can be greatly reduced.

Further, since the input / output terminals can be drawn out from any side of the macro cell, the wiring property is improved when laying out the chip, and the wiring length is shortened, so that high-speed operation is possible.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a macro cell layout method according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing a macro cell according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing a macro cell layout method according to a second embodiment of the present invention.

FIG. 4 is a schematic plan view showing a macro cell according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a hierarchical structure of a chip.

FIG. 6 is a flowchart showing a conventional macro cell layout method.

FIG. 7 is a schematic plan view showing a conventional macro cell.

FIG. 8 is an enlarged view of a part of FIG. 7;

[Explanation of symbols]

Reference Signs List 1 master information 2 circuit connection information 3 wiring prohibition information 4 macro cell layout data 11 to 13, 21 to 23, 31 to 33, 301, 301
A to 301C Basic function cells 11a to 11c Exclusive OR gates 12a to 12c Flip-flops 13a to 13c Adders 41 to 48, 80a to 80d, 81a to 81d, 82a
To 82d, 90a to 90c, 91a to 91c Wiring prohibited area 51 to 59, 51a to 51c, 52a to 52c, 53a
To 53c I / O terminals 61 to 65 Wirings connecting between basic function cells inside the macrocell 71, 72 Wiring from the I / O terminals to the outside of the macrocell 100 Chip 101, 101A, 101B, 101C Macrocell 102 Memory cell 103 User logic circuit 104 I / O cell 201 PLL 202 Multiplier 203 RAM 204 ROM 401 Basic cell

Claims (8)

[Claims] 1. A method of laying out a macro cell having a specific function, wherein a plurality of basic function cells, which are basic elements of a logic circuit, are formed on a semiconductor substrate, and the basic function cells are wired based on circuit connection information. Extracting the basic function cell having the input / output terminal connected to the outside of the macro cell; determining the drawing direction of the input / output terminal; and grouping the basic function cell having the input / output terminal in the same drawing direction. And arranging the same group of the basic function cells,
A method of laying out a macro cell, comprising the steps of: providing a wiring prohibited area near the input / output terminals existing in these arranged basic function cells, and performing wiring in the macro cell. 2. The basic function cell according to claim 1, wherein said basic function cells are arranged in a basic cell region in which basic cells which are constituent elements of said basic function cell are fixedly arranged in an array on said semiconductor substrate. 2. The layout method of the macro cell according to 1. 3. The method according to claim 1, further comprising the steps of: determining the number of arrangement stages of the basic function cells in the same group; and providing a wiring prohibition region near the input / output terminals through which the same number of interconnection lines can pass. 2. The layout method for a macro cell according to claim 1, wherein: 4. The step of determining the number of stages of basic function cells in the same group, wherein the height of the number of stages is substantially equal to the number of stages of basic function cells in the same group. 4. The layout method for a macro cell according to claim 3, wherein the basic function cells are further divided into groups. 5. The macro cell layout method according to claim 1, wherein in the step of grouping the basic function cells, the same group is composed of basic function cells having the same function. 6. The macro cell layout method according to claim 1, wherein the wiring prohibited area is an area on a straight line reaching at least one side of the macro cell. 7. A macro cell comprising a plurality of basic function cells, which are basic elements of a logic circuit, wherein the macro cell comprises: an input / output terminal for connecting to the outside of the macro cell; A wiring prohibited area for drawing out wiring, wherein the wiring prohibited area vertically or traverses an upper side and a lower side or a left side and a right side of the basic function cell having the input / output terminal near the input / output terminal. A macro cell, wherein the macro cell is provided. 8. A plurality of basic function cells having the same function and having the same wiring lead-out direction from the input / output terminal are arranged adjacent to each other, and the basic function cells adjacent to each other in the wiring prohibited area are arranged. 8. The macro cell according to claim 7, wherein the macro cell is continuous.