JPH10209175A - Junction field-effect transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the resistance of a junction field-effect transistor against impact ionization. SOLUTION: On the surface of an Si substrate 6, protrusions, recesses and slants therebetween are formed by the LOCOS oxidation of silicon. A gate region 2 is formed at the protrusion, source region and drain region 4 are formed in the recess, and low-concn. source region 8 and low-concn. drain region 7 are formed at the slants, i.e., the boundaries between the gate region 2, source region 1 and drain region 4. The gate region 2, source region 1, and drain region 4 do not contact high-impurity concn. regions, and hence the electric field, e.g. at the boundary between the gate region 2 and drain region 4 is low to suppress the impact ionization.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a junction field effect transistor and a method of manufacturing the same, and more particularly, to a junction field effect transistor used in applications requiring high resistance to impact ionization, such as an image sensor. It is suitable for.

[0002]

2. Description of the Related Art A junction type field effect transistor is a MOS transistor.
Like a transistor and a bipolar transistor, it has been widely used as an important single element when configuring various devices using a semiconductor element such as an image sensor. Recently, these semiconductor elements have been highly integrated, and accordingly, further miniaturization of the junction field-effect transistor has been required, and further reduction in the gate length has been required.

The structure of a conventional junction field effect transistor will be described with reference to FIGS. First, FIG. 16 is a plan view for explaining each diffusion region of a conventional junction field effect transistor formed in a semiconductor substrate, and FIG. 15 is a cross-sectional view along the line BB in FIG.
As shown in FIG. 16, the first conductivity type (here, p-type) is sandwiched between the source region 101 and the drain region 104 of the second conductivity type (here, n-type) on the semiconductor substrate 106, respectively.
A gate region 102 of the second conductivity type (that is, n-type here) is formed at the bottom of the gate region 102. Further, as shown in FIG. A back gate region 103 of the first conductivity type is formed at the bottom of 102. In addition,
Actually, respective electrodes, inter-phase insulating films, and the like are formed on the source region 101, the drain region 104, the gate region 102, and the like, but these are omitted in FIGS.

In the conventional junction field effect transistor shown in FIG. 15, the gate region 102 and the back gate region 1
03 is depleted by applying a reverse bias to the source region 101 and the drain region 1.
A current (channel current) flowing through the channel region 105 between the current control circuit and the current control circuit 04 is controlled. Then, the channel current is completely cut off at a certain gate bias value. Here, in order to suppress ionization of electrons in the pinch-off region near the boundary of the drain region 104, that is, generation of hot electrons due to impact ionization, a reverse electric field strength between the gate region 102 and the drain region 104 is set. Need to be improved. That is, it is necessary to reduce the electric field at the end of the drain region 104. Therefore, as a method of forming the source region 101 and the drain region 104, for example, a double diffusion structure in which two types of n-type impurities are diffused one deeply and the other shallowly and the impurity distribution of the diffused region is graded, or LDD that forms a low-concentration diffusion region in contact with a high-concentration diffusion region to make the impurity concentration distribution gentle.
(Lightly Doped Drain) structure etc. have been adopted.

Next, an example of a manufacturing process of such a conventional junction field effect transistor will be described with reference to FIGS. First, as shown in FIG. 17, a first conductivity type back gate region 103 is formed in a semiconductor substrate 106 made of, for example, a silicon substrate. That is, using a normal photolithography technique, the surface of the semiconductor substrate 106 is covered with the resist film 110A except for a region where the back gate region 103 is formed, and boron (B) is accelerated as a p-type impurity for forming the back gate. Ion implantation is performed under the conditions of a voltage of 60 keV and an implantation amount of 1 × 10 ¹² to 1 × 10 ¹³ / cm ² . Then, after cleaning, in a nitrogen (N ₂ ) atmosphere,
Anneal at 150 ° C. for 50 to 200 minutes. FIG.
In FIG. 7, an oxide film 108 is formed on the surface of the semiconductor substrate 106, but the oxide film 108 may not be formed in some cases.

[0008] Next, as shown in FIG. 18, the surface of the semiconductor substrate 106 is covered with a resist film 110 B except for a region where the source region 101 and the drain region 104 are formed by using a normal photolithography technique. Arsenic (As) as an n-type impurity for forming a region
With an acceleration voltage of 120 keV and an injection amount of 1 × 10 ^{15 to} 5 ×
Ion implantation is performed under the condition of 10 ¹⁵ / cm ² , and after the cleaning, annealing is performed at 950 ° C. for about 30 minutes in a nitrogen atmosphere. As a result, the source region 101 is formed in the back gate 103, and the drain region 104 is formed around the back gate 103.
Is formed. When the source / drain regions are formed by a double diffusion method, first, phosphorus (P), which is an n-type impurity, is accelerated at an acceleration voltage of 100 keV and an implantation amount of 1 × 10 ^13.
Ions are implanted under conditions of about 5 × 10 ¹⁴ / cm ² , and after cleaning, annealed at 1000 ° C. for about 30 minutes in a nitrogen atmosphere. Then, after forming a resist film again by using the photolithography technique, arsenic (As) is accelerated at an accelerating voltage of 120 k.
Ion implantation may be performed under conditions of eV and an implantation amount of 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² , and after cleaning, annealing may be performed at 950 ° C. for about 30 minutes in a nitrogen atmosphere. At this time, the arsenic implantation region is set to be inside the phosphorus implantation region.

[0009] Next, as shown in FIG. 19, the surface of the semiconductor substrate 106 is covered with a resist film 110 C except for a region where the channel region 105 is to be formed, using a normal photolithography technique, and n for forming a channel is formed. Phosphorus (P) is implanted as a type impurity under the conditions of an acceleration voltage of 150 keV to 1 MeV and an implantation amount of 1 × 10 ^{12 to} 9 × 10 ¹² / cm ² , and after washing, 950 ° C. to 1100 in a nitrogen atmosphere.
Anneal at about 30 minutes. By this step, a channel region 105 is formed between the source region 101 and the drain region 104.

Then, as shown in FIG. 20, the surface of the semiconductor substrate 106 is covered with a resist film 110D except for a region where a junction field effect transistor is to be formed, using a normal photolithography technique, so as to form a gate region. P
Boron difluoride (BF ₂ ) as a mold impurity is accelerated at a voltage of 100 keV and a dose of 1 × 10 ¹² to 2 × 10 ¹³ / cm.
Ion implantation under conditions ² and after washing 9
Anneal at 50 ° C. for about 30 minutes. Thus, a frame-shaped gate region 102 is formed above the channel region 105 and the back gate region 103.

Next, as shown in FIG.
06, an interlayer insulating film 111 is formed on each of the diffusion regions,
That is, contact holes connected to the gate region 102, the source region 101, and the drain region 104 are formed, electrodes 112A to 112C are formed therethrough, and wiring is performed between the electrodes. In this case, the interlayer insulating film 111 is formed of the electrodes 112A to 112
C and another wiring and electrodes 112A to 112 formed below C
It is formed in order to keep insulation from the wiring of C.

Although heat treatments for activating the implanted impurities are performed in each step in FIGS. 17 to 20, these heat treatments are usually shared in some steps. In addition, the order of forming the respective diffusion regions may be changed. For example, the channel region 10 shown in FIG.
After forming 5, the source region 101 and the drain region 104 shown in FIG. 18 may be formed in some cases.

[0011]

As described above, in the conventional junction field effect transistor, the source / drain region has a double diffusion structure or the drain region has an LDD structure in order to increase the resistance to impact ionization. Was. However, even if such a structure is adopted, as the gate length becomes shorter than about 1 μm, the electric field at the end of the drain region increases, and even if the potential difference between the source region and the drain region is several volts, There is a disadvantage that a gate current is generated due to impact ionization at the end of the drain region. Such a gate current causes noise for the semiconductor device. Further, when the electric field at the end of the drain region is increased, avalanche breakdown occurs between the gate region and the drain region, and the semiconductor element is destroyed.

In view of the above, an object of the present invention is to provide a junction field effect transistor having high resistance to impact ionization. Still another object of the present invention is to provide a method for manufacturing such a junction field effect transistor.

[0013]

A junction field effect transistor according to the present invention has a surface gate region (2) of a first conductivity type (p-type or n-type) and a second gate formed on both sides of the surface gate region. A source / drain region (1, 4) of two conductivity type (n-type or p-type), a channel region (5) of second conductivity type formed below the surface gate region (2), and a source / drain region ( 1, 4) and a first conductivity type back gate region (3) formed below the channel region (5);
In the junction type field effect transistor having the structure, a step in the thickness direction is provided between the surface gate region (2) and the source / drain region (1, 4), and the surface gate region (2) and the source / drain region ( An inclined portion (7, 8) is provided in a region in contact with the boundary with (1, 4) so as to gradually become thicker in a direction away from the boundary. The surface gate region means a gate region formed near the surface of the semiconductor substrate.

According to the present invention, a step in the thickness direction is provided at the boundary between the surface gate region (2) and the source / drain regions (1, 4), and the inclined portion is provided near the boundary. (7, 8) is provided. Normally, different types of impurities are diffused into the surface gate region and the source / drain regions, and a reverse bias voltage is applied. However, the impurity concentrations in the surface gate region and the source / drain regions become lower toward the bottom. Due to the tendency, the two hardly come into contact with each other in a region having a high impurity concentration. Therefore,
The electric field at the boundary between the surface gate region and the source / drain region is reduced, and the resistance to impact ionization is improved.

[0015] Even if the step and the inclined portion are provided only at the boundary between the surface gate region (2) and the drain region (4), the resistance to impact ionization is improved. Further, in the present invention, the concentration gradually decreases in the inclined portions (7, 8) in contact with the boundary between the surface gate region (2) and the source / drain regions (1, 4) in a direction away from the boundary. It is desirable to provide a concentration gradient portion in which impurities are diffused as described above. In the concentration gradient portion, since the potential difference becomes gentle, the intensity of the electric field at the boundary between the surface gate region and the source / drain region is further reduced.

Further, in the method of manufacturing a junction field effect transistor according to the present invention, an oxide film (10) is formed on a predetermined semiconductor substrate (6), and this oxide film is further partially oxidized by a LOCOS method. A first step of forming a projection (6a) and a depression (6b) on the surface of the semiconductor substrate (6), and forming a surface gate region (2) on the projection of the surface of the semiconductor substrate (6). And a second step of forming source / drain regions (1, 4) in the recesses.

In the manufacturing method of the present invention, the LOCOS
The (Local Oxidation Of Silicon) method is to form an oxidation-resistant film partially on the surface of a substrate and then oxidize the surface of the substrate to partially cover the region other than the region where the oxidation-resistant film is formed. Oxidation method for forming an oxide film. By partially further oxidizing the oxide film (10) on the surface of the semiconductor substrate (6) by the LOCOS method, for example, as shown in FIG.
b), and the non-oxidized region is left as a projection (6a). An inclined portion (6c) is formed between the convex portion (6a) and the concave portion (6b). Therefore, the surface gate region (2) is formed in the remaining convex portion and the source / drain region (1, 4) is formed in the concave portion, so that the surface gate region (2) and the source / drain region (1, 2) are formed. A step in the thickness direction and an inclined portion can be easily formed at the boundary with 4).

In this case, in the first step, after an oxide film (10) is formed on the semiconductor substrate (6), an oxidation resistant film (9) is formed partially, and the oxidation resistant film is formed. After the projections (6a) and the recesses (6b) are formed on the surface of the semiconductor substrate (6) by oxidizing by LOCOS so that the oxide film (10) other than the portions that are present is thickened, the recesses (6) are formed.
b) The oxide film (10) is thinned by etching the oxide film (10) thereabove, and the recess (6) is formed in the second step.
It is preferable that the source / drain regions (1, 4) are formed by performing ion implantation on the oxide film (10) on b).

When the LOCOS oxidation is performed as described above, for example, as shown in FIG. 4, both ends of the oxidation resistant film (9) become a thick oxide film (10a). Therefore, when this thick oxide film (10a) is thinned by etching, For example, as shown in FIG. 6, the end portions (9a, 9b) of the oxidation-resistant film (9) are turned up to form a bird's beak, that is, a bird's beak.
k). The deformation of this end becomes greater as the degree of LOCOS oxidation increases, and the present invention utilizes this bird's beak. That is, when ions are implanted through the region including the oxidation resistant film (9), the bird's beak-like end portions (9a, 9a) are formed.
In the case of b), the thickness as viewed from above becomes thinner toward the tip, and the transmission amount of the ion beam gradually increases.
Concentration gradient portions (7, 8) of impurity portions are easily formed in the inclined portion (6c), which is the bottom portion of a, 9b).

Further, by the etching in the first step, the remaining film thickness of the oxide film (10) is reduced to 200Å1500Å.
It is desirable to set within the range. Since the thickness of the oxide film formed by the LOCOS method is, for example, about 8000 °, in this case, about 4/5 or more of the formed oxide film may be removed while leaving about 200 °.
If the remaining film thickness is more than 1500 °, it becomes difficult to form source / drain regions through the oxide film by a normal ion implantation method. In addition, the remaining film thickness is 20
When the thickness is less than 0 °, protection of the surface of the semiconductor substrate becomes insufficient.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In the following embodiments, the first conductivity type is p-type and the second conductivity type is n-type. However, the same applies even if the first conductivity type is replaced with n-type and the second conductivity type is replaced with p-type. It goes without saying that it can be configured.
1 and 2 show the configuration of a single element of the junction field-effect transistor of the present embodiment. FIG. 2 is a plan view of the junction field-effect transistor, and FIG.
It is sectional drawing which follows a line.

In FIG. 2, an n-type source region as a second conductivity type is provided inside and outside a p-type frame-shaped gate region 2 as a first conductivity type formed on a silicon substrate 6 therebetween. 1 and a drain region 4 are formed. As shown in FIG. 1, a gate region 2 is formed of L
The cross section formed on the silicon substrate 6 by oxidation by the OCOS (Local Oxidation Of Silicon) method is formed in a trapezoidal convex portion, and the source region 1 and the drain region 4 are both formed in concave portions in contact with the convex portion. Have been. That is, a step in the thickness direction is formed at the boundary between the gate region 2 and the source region 1 and the drain region 4, and an inclined portion that becomes gradually thicker as the distance from the boundary increases. Gate region 2 is a surface gate region formed on the surface of silicon substrate 6.

The second bottom surface of a part of the gate region 2
An n-type channel region 5 as a conductivity type is formed, and a p-type back gate region 3 is formed at the bottom of the gate region 2 and the channel region 5. Further, a low-concentration drain region 7 in which a low-concentration n-type impurity is diffused is formed at an inclined portion in contact with the inner boundary of the frame-shaped drain region 4. A low concentration source region 8 in which a low concentration n-type impurity is diffused is formed. It should be noted that the low-concentration drain region 7A is also formed on the inclined portion that contacts the outer boundary of the drain region 4. Actually, the concentration distribution of the n-type impurity in the low-concentration source region 8 and the low-concentration drain region 7 becomes gradually thinner in a direction away from the boundary with the gate region 2. Further, electrodes 15B, 15A and 15C are connected to the source region 1, the gate region 2 and the drain region 4, respectively. Although not shown, wiring is performed for each electrode, and the entire surface of the silicon substrate 6 is formed. An oxide film and an interlayer insulating film are formed so as to cover.

As shown in FIG. 1, the gate region 2 of this embodiment is formed in a frame-shaped convex portion on the silicon substrate 6, and the source region 1 and the drain region 4 are formed in concave portions in contact with the convex portion. Is formed at the boundary of. Further, since the gate region 2, the source region 1, and the drain region 4 are diffusion regions formed by injecting impurities from the upper portion and diffusing them by heating or the like, the impurity concentration distribution is higher at the upper portion and lower at the lower portion. . Therefore, the gate region 2 and the source region 1 and the drain region 4 are not in contact with each other at a location where the impurity concentration is high, and the gate region 2 and the source region 1 are different from the conventional junction type field effect transistor shown in FIG. 1 and the effect of relaxing the electric field at the boundary with the drain region 4 is increased. As a result, generation of a gate current due to impact ionization can be suppressed.

Further, since the inclined portion is formed in the direction from the boundary between the gate region 2 to the source region 1 and the drain region 4 toward the center of the gate region 2, the gate region 2, the source region 1 and the drain region are substantially formed. The contact area with the region 4 is further reduced, and the electric field near the boundary is smaller. Furthermore, the low concentration source region 8
And the low-concentration drain region 7 is formed, and since the gradient of the impurity concentration is gentle near the boundary between the gate region 2 and the source region 1 and the drain region 4, the electric field is further reduced, and the resistance to impact ionization is reduced. It is even higher.

In FIG. 1, it is apparent that the effect of alleviating the electric field at the boundary between the gate region 2 and the drain region 4 is large even if the source region 1 is not formed in the concave portion on the surface of the silicon substrate 6. In this example, as described later, the source region 1 and the drain region 4 can be manufactured using the same mask, so that the source region 1 is also formed in a recess in the structure.

Next, a first manufacturing method of the junction field effect transistor of this embodiment will be described with reference to FIGS. 3 to 5 show a silicon substrate 6 by the LOCOS method.
FIG. 3 is a cross-sectional view for explaining a step of forming a convex portion and a concave portion (step). First, as shown in FIG. 3, a silicon oxide film 10 as a protective film is formed on the entire surface of the silicon substrate 6.
To form As described above, when performing oxidation by the LOCOS method described below, the underlying oxide film for the purpose of alleviating the stress of the oxidation-resistant mask is called a “PAD oxide film”. Called oxide film 10. PAD oxidation conditions are, for example, a temperature of 1000 ° C.
The dry oxidation is performed for about 30 to 100 minutes, and the thickness of the PAD oxide film 10 is about 200 to 800 °.

Thereafter, the surface of the silicon substrate 6 excluding the source region and the drain region constituting the junction field effect transistor is oxidized by the LOCOS method (hereinafter referred to as "LO
A nitride film 9 is formed as an oxidation-resistant mask at the time of “COS oxidation”. The thickness of the nitride film 9 is 400 to 1000 Å
Degree. Subsequently, as shown in FIG. 4, LOCOS oxidation is performed using the nitride film 9 as a mask. The conditions for LOCOS oxidation include, for example, pyro oxidation (steam oxidation using a thermal oxidation device) at a temperature of about 1000 ° C. and 100 to 2 times.
Oxidation is performed for about 00 minutes. As a result, the PAD oxide film 10 between the nitride films 9 on the silicon substrate 6 is further oxidized to become a thick oxide film (hereinafter, referred to as "LOCOS oxide film") 10a. The thickness of the LOCOS oxide film 10a (including the PAD oxide film 10) is, for example, about 8000 °. This L
By the OCOS oxidation, the bottom of the LOCOS oxide film 10a becomes the concave portion 6b and the bottom of the nitride film 9 becomes the convex portion 6a on the surface of the unoxidized portion of the silicon substrate 6. However, since the cross-sectional shape of the convex portion 6a and the concave portion 6b is trapezoidal, the boundary between them is the inclined portion 6c. That is, a step structure having an inclination is formed on the surface of the unoxidized portion of the silicon substrate 6 by the LOCOS oxidation.

Next, the thick LOCOS oxide film 10a on the region where the source and drain are to be formed is removed from the surface to a certain depth by etching. The etching method may be either wet etching or dry etching, but it is preferable that the etching method has high selectivity to the nitride film 9 and the nitride film 9 remains as it is. The film thickness to be removed by this etching is set so that the remaining film thickness can reach a sufficient amount inside the silicon substrate 6 when ions are implanted into the source region and the drain region. . As an example, the remaining film thickness of the LOCOS oxide film 10a (including the PAD oxide film 10) is desirably about 1500 ° or less at which ions can sufficiently penetrate, and about 200 ° or more so that the oxide film can reliably remain. . FIG.
Assuming that the thickness of the LOCOS oxide film 10a is about 8000 mm in this case, about 4/5 or more of the film thickness should be removed under the condition that the remaining film thickness is about 200 mm or more.
However, the entire LOCOS oxide film 10a including the PAD oxide film 10 may be removed.

FIG. 5 shows a state in which a part of the LOCOS oxide film has been removed. In FIG. 5, both ends 9a and 9b of the nitride film 9 left on the PAD oxide film 10 are bird's beaks, that is, bird's beaks. (Bird's beak). This is a modification due to the LOCOS oxide film 10a in FIG. Through the above steps, the projections 6a, the inclined portions 6c, and the concave portions 6b are formed on the surface of the non-oxidized portion of the silicon substrate 6, and the nitride film 9 is formed on the projected portions 6a and the inclined portions 6c.
Is left as a mask.

Next, as shown in FIG. 6, arsenic (A) is used as an n-type impurity for forming a source region and a drain region.
s) with an acceleration voltage of about 120 keV and an injection amount of 1 × 10 ¹⁵ to
Ion implantation is performed under the condition of 5 × 10 ¹⁵ / cm ² , and after cleaning, annealing is performed in a nitrogen atmosphere at a temperature of about 950 ° C. for about 30 minutes. As a result, the source region 1 and the drain region 4 are formed inside the concave portion 6b on the silicon substrate 6. Also,
Nitride film 9 used as oxidation resistant mask during LOCOS oxidation
When ions are implanted using the mask as a mask, the thickness of the nitride film 9 in the bird's beak-like ends 9a and 9b in the direction perpendicular to the surface of the silicon substrate 6 gradually changes substantially toward the tip. In addition, the amount of ions transmitted by ion implantation gradually changes toward the tip. Therefore, in the inclined portion 6c at the bottom of the ends 9a and 9b, a low-concentration source region 8 is formed in a region in contact with the source region 1,
A low concentration drain region 7 is provided in a region in contact with the drain region 4.
Is formed. As a result, the impurity concentration gradient at the boundary between the drain regions 4 becomes gentle, and the effect of reducing the electric field at the end of the drain region can be obtained without having the drain region have a double diffusion structure as in the conventional example. .

Next, as shown in FIG.
A p-type back gate region 3 is formed so as to be in contact with the inside of the substrate. For this purpose, after removing the nitride film 9 shown in FIG. 6, the surface of the silicon substrate 6 is covered with a resist film 11 except for a region where a back gate region is to be formed, using a normal photolithography technique. Boron (B) is implanted with an acceleration voltage of about 60 keV and an injection amount of 1 × 10 ¹² to 1 × 10 ^13.
After ion implantation under the condition of / cm ² , annealing is performed in a nitrogen atmosphere at about 1150 ° C. for 50 to 200 minutes. As a result, the back gate region 3 having a diffusion region deeper than the drain region 4 is formed. In this example, the PAD oxide film 10 is left on the surface of the silicon substrate 6, but the PAD oxide film 10 may be entirely removed in the step of FIG.

Next, as shown in FIG.
N above the back gate region 3 between the gate and the source region 1
A channel region 5 is formed. Therefore, first, the surface of the silicon substrate 6 is removed from the resist film 12 except for the region where the channel region is to be formed by using the ordinary photolithography technique.
And phosphorus (P) as a p-type impurity at an accelerating voltage of 15
0 keV to 1 MeV and injection amount 1 × 10 ^{12 to} 9 × 10 ¹²
After ion implantation under the condition of / cm ² , annealing is performed in a nitrogen atmosphere at a temperature of 950 ° C. to 1100 ° C. for about 30 minutes. Thereby, the drain region 4 and the source region 1
Is formed.

Next, as shown in FIG.
The gate region 2 is formed inside the convex portion on the surface of FIG. Therefore, the surface of the silicon substrate 6 is covered with a resist film 13 except for a region where a junction field effect transistor is to be formed using a normal photolithography technique, and difluoride is used as a p-type impurity for forming a gate region. Element (BF ₂ ) with an acceleration voltage of about 100 keV and an injection amount of 1 × 10 ¹² to 2 × 1
Ion implantation is performed under the condition of 0 ¹³ / cm ² , and after cleaning, annealing is performed at about 950 ° C. for about 30 minutes in a nitrogen atmosphere. As a result, a p-type gate region 2 is formed so as to be in contact with the upper portions of the back gate region 3 and the channel region 5 and to surround the source region 1.

Finally, as shown in FIG. 10, an interlayer insulating film 14 is formed on the surface of the silicon substrate 6 (here, covered with the PAD oxide film 10). After the interlayer insulating film 14 is formed, contact holes connected to the gate region 2, the source region 1, and the drain region 4 are formed, and the gate electrode 15A and the source electrode 15B are respectively formed through the contact holes. , And a drain electrode 15C are formed, and wiring of these electrodes is performed. In this case, the interlayer insulating film 14 includes the electrodes 15A to 15A.
It is formed as an insulating film between the wirings of 15C and other wirings formed under those wirings.

As described above, according to the manufacturing method of this embodiment, the junction field effect transistor having the step structure shown in FIG. 1 can be easily manufactured. In the manufacturing method of this example, when the drain region 4 shown in FIG. 6 is formed, high-concentration drain region 4 and source region 1 are formed by ion implantation once using nitride film 9 as a mask on the gate region side.
, A low-concentration drain region 7 and a low-concentration source region 8 in which low-concentration impurities are diffused are formed. That is, in the conventional LDD (Lightly Doped Drain) structure, a special process for forming a low-concentration diffusion region in contact with a high-concentration diffusion region is provided. Since a similar impurity concentration profile can be formed without providing, the manufacturing process can be simplified.

Further, as shown in FIG. 9, in this embodiment, the gate region 2 is formed only by performing ion implantation using a rough mask.
Is formed on the convex portion of the silicon substrate 6. That is, the gate region 2 can be formed by a so-called self-alignment method, and there is no need to consider an allowable value (Alignment tolerance) of a mask overlay error in a photolithography process, which contributes to an improvement in integration. Furthermore, LOC
Since the oxidation process using the OS method can be used in a process for manufacturing CMOS, the junction field-effect transistor of this example can be formed simultaneously with CMOS without increasing the number of manufacturing steps.

In the steps shown in FIGS. 7 to 9,
Although the heat treatment for activating the implanted impurities is performed in each step, the heat treatment may be used in some steps.
Further, the order of forming the respective diffusion regions may be changed. For example, after the channel region 5 shown in FIG. 8 is formed, the back gate region 3 shown in FIG. 7 may be formed. In this example, since the drain region 4 and the source region 1 are simultaneously formed as shown in FIG. 6, a common mask can be used for the drain region 4 and the source region 1. However, for example, it is also possible to form the source region 1 on the convex portion of the surface of the silicon substrate 6 in the same manner as the gate region 2. In this case, an ion implantation step for forming the source region 1 and the drain region 4 is performed. In the previous step of removing the LOCOS oxide film, it is necessary to remove the nitride film on the region to be the source region 1. Further, since the source region 1 and the drain region 4 are not formed by the same mask, it is necessary to keep the alignment error of the mask between the two manufacturing steps within a predetermined allowable range.

Next, a second method of manufacturing the junction field effect transistor of this embodiment will be described with reference to FIGS. This second manufacturing method involves the following steps before the LOCOS oxidation:
Although the first manufacturing method is different from the first manufacturing method in that a part of the impurity diffusion region (the back gate region in the following example) is formed, the structure of the junction field effect transistor finally obtained by the second manufacturing method is as follows. 11 to 14 are the same as those obtained by the first manufacturing method.
Parts corresponding to 0 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIGS. 11 to 14 are sectional views showing the steps of manufacturing the junction field effect transistor according to the second manufacturing method. First, a p-type back gate region 3 is formed on a silicon substrate 6 as shown in FIG. The method of forming the back gate region 3 is the same as the method described with reference to FIG. That is, using a normal photolithography technique, the surface of the silicon substrate 6 is covered with a resist film except for the region for forming the back gate region, and boron (B) is implanted as a p-type impurity at an acceleration voltage of about 60 keV and an implantation amount of 1 ×. Ion implantation is performed under the conditions of 10 ¹² to 1 × 10 ¹³ / cm ² , and after cleaning, 50 to 200 at 1150 ° C. in a nitrogen atmosphere.
Annealing may be performed for a minute. Next, the PAD oxidation is performed on the entire surface of the silicon substrate 6 on which the back gate region 3 is formed, for example, under a dry oxidation condition at a temperature of 1000 ° C. for a processing time of about 30 to 100 minutes and a film thickness of about 200 to 800 °. After the formation of the film 10, except for the source region and the drain region, 400 to 1
A nitride film 9 is formed to a thickness of about 000 °.

Subsequently, as shown in FIG.
Perform oxidation. Specifically, the temperature is about 100 by the pyro-oxidation method.
Oxidation is performed at 0 ° C. for about 100 to 200 minutes to form a partially thick LOCOS oxide film 10 a (film thickness is, for example, 8000 °) on the silicon substrate 6. Next, the LOCOS oxide film 10a on the region where the source region and the drain region are to be formed is removed by etching to a certain depth from the surface. It is desirable that the film thickness removed by this etching be in the range where the remaining film thickness is about 200 to 1500 ° similarly to the first manufacturing method. However, 4/5 or more of the thickness of the LOCOS oxide film 10a (including the PAD oxide film 10) may be removed.
Oa including the PAD oxide film 10 may be entirely removed.

By the above steps, as shown in FIG.
The protrusion 6 is formed on the surface of the non-oxidized portion of the silicon substrate 6.
a, the concave portion 6b, and the inclined portion 6c are formed, and a step structure is formed. Next, as shown in FIG. 14, arsenic (As) is used as an n-type impurity for forming a source region and a drain region with an acceleration voltage of about 1 using the nitride film 9 as a mask.
20 keV and injection amount of 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ²
Ion implantation under the conditions of
Anneal at a temperature of 50 ° C. for about 30 minutes. Thus, the source region 1 and the drain region 4 are formed in the concave portion on the silicon substrate 6. Further, similarly to the first manufacturing method, the low-concentration arsenic diffuses into the respective boundaries between the source region 1 and the drain region 4 due to the change in the amount of transmission of the ion beam at both ends 9a and 9b of the nitride film 9. The low-concentration source region 8 and the low-concentration drain region 7 thus formed are formed.

Hereinafter, as shown in FIG. 10, the channel region 5, the gate region 2 and the electrode 15A are formed by the same steps as those described with reference to FIGS.
By forming ~ 15C, the junction field effect transistor shown in FIG. 1 is formed. Although the junction field-effect transistor is formed on the silicon substrate in the above embodiment, the substrate on which the junction field-effect transistor is formed is not limited to the silicon substrate, but may be another semiconductor substrate. In addition, although the nitride film 9 is used as the oxidation-resistant mask, another film may be used as long as it is a film resistant to oxidation.
Furthermore, the conditions for forming the respective diffusion regions such as the gate region, the source region, and the drain region, and the types of impurities are not limited to those described above. For example, as the p-type impurity, besides boron (B), aluminum (Al), gallium (Ga), indium (In) and the like can be used, and as the n-type impurity, antimony (Sb) and the like can be used in addition to phosphorus (P) and arsenic (As).

As described above, the present invention is not limited to the above-described embodiment, and can take various configurations without departing from the gist of the present invention.

[0045]

According to the junction field effect transistor of the present invention, a step in the thickness direction is provided at the boundary between the source / drain region and the surface gate region, and the boundary is formed as an inclined portion. Therefore, the surface gate region and the source / drain region hardly contact each other in a region having a high impurity concentration. Therefore, there is an advantage that the effect of alleviating the electric field particularly at the boundary between the surface gate region and the drain region is increased, and the resistance to impact ionization is improved.

Further, a concentration gradient portion in which impurities are diffused such that the concentration gradually decreases in a direction away from the boundary is formed inside the inclined portion contacting the boundary between the surface gate region and the source / drain region. In this case, the gradient of the impurity concentration distribution at the boundary between the surface gate region and the source / drain region becomes gentle, for example, the intensity of the electric field at the end of the drain region becomes further smaller, and the impact ionization is prevented. Improves resistance.

Further, according to the method of manufacturing a junction field effect transistor of the present invention, a stepped structure and an inclined portion are formed on a semiconductor substrate by oxidation by the LOCOS method, and the formed convex portion is formed on the semiconductor substrate. A surface gate region is formed, and the source / drain regions are formed in the recess. Therefore, the junction field effect transistor of the present invention can be easily manufactured. LOCOS oxidation is C
Since it can be used in a MOS process, there is also an advantage that the junction field effect transistor of the present invention can be formed simultaneously with CMOS without increasing the number of manufacturing steps.

In a first step of the manufacturing method, an oxide film is formed on the semiconductor substrate, and then an oxidation-resistant film is formed partially, and the oxidation-resistant film other than the portion where the oxidation-resistant film is formed is formed. After forming the protrusions and recesses on the surface of the semiconductor substrate by performing oxidation by the LOCOS method so as to make the film thicker, the oxide film on the recesses is etched to make the oxide film thinner. When the two steps are to form the source / drain regions by performing ion implantation through the oxide film on the recesses, the L
The shape of the end portion of the oxidation-resistant film as a mask changes depending on the degree of the OCOS oxidation, and the ion implantation for forming the source / drain regions simultaneously causes the source to be formed at the boundary between the gate region and the source / drain regions. A low concentration diffusion region of the same impurity as the drain region is formed. Therefore, the conventional LDD (Lightly doped drain) can be performed by a single ion implantation process using the oxidation resistant film as a mask.
3) Since the same impurity concentration profile as that of the structure can be formed, the manufacturing process can be simplified. Further, since the gate region can be formed by a self-alignment method, there is an advantage that the degree of integration can be improved.

When the remaining film thickness of the oxide film is set in the range of 200 ° to 1500 ° by the etching in the first step, the surface of the semiconductor substrate is protected well and the remaining oxide film is passed through. Ion implantation can be easily performed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view taken along the line AA in FIG. 2 showing a schematic configuration of a junction field-effect transistor according to an example of an embodiment of the present invention.

FIG. 2 is a plan view showing each diffusion region of a junction field-effect transistor according to an example of an embodiment of the present invention.

3 is a cross-sectional view showing a step of forming a PAD oxide film 10 and a nitride film 9 in a first method for manufacturing the junction field effect transistor of FIG.

FIG. 4 is a cross-sectional view showing a step of forming a LOCOS oxide film 10a in the first manufacturing method.

FIG. 5 is a cross-sectional view showing a state where a part of the LOCOS oxide film 10a has been removed from the state of FIG.

FIG. 6 is a cross-sectional view showing a step of forming a source region 1, a drain region 4, a low-concentration drain region 7, and the like in the first manufacturing method.

FIG. 7 is a cross-sectional view showing a step of forming a back gate region 3 in the first manufacturing method.

FIG. 8 is a cross-sectional view showing a step of forming a channel region 5 in the first manufacturing method.

FIG. 9 is a cross-sectional view showing a step of forming a gate region 2 in the first manufacturing method.

FIG. 10 shows an interlayer insulating film 14 in the first manufacturing method.
FIG. 4 is a cross-sectional view showing a step of forming an electrode and the like.

11 shows a back gate region 3 and a PAD oxide film 1 in a second method of manufacturing the junction field effect transistor shown in FIG. 1;
0 and a cross-sectional view showing a step of forming a nitride film 9.

FIG. 12 is a cross-sectional view showing a step of forming a LOCOS oxide film 10a in the second manufacturing method.

13 is a cross-sectional view showing a state where a part of the LOCOS oxide film 10a has been removed from the state of FIG.

FIG. 14 is a cross-sectional view showing a step of forming a drain region 4, a source region 1, a low-concentration drain region 7, and the like in the second manufacturing method.

FIG. 15 is a cross-sectional view taken along the line BB of FIG. 16 showing an example of a conventional junction field-effect transistor.

FIG. 16 is a plan view showing an example of a conventional junction field effect transistor.

FIG. 17 is a cross-sectional view showing a step of forming a back gate region in a conventional method for manufacturing the junction field effect transistor of FIG.

FIG. 18 is a cross-sectional view showing a step of forming a source region and a drain region in the conventional manufacturing method.

FIG. 19 is a cross-sectional view showing a step of forming a channel region in the conventional manufacturing method.

FIG. 20 is a cross-sectional view showing a step of forming a gate region in the conventional manufacturing method.

FIG. 21 is a cross-sectional view showing a step of forming an interlayer insulating film, electrodes, and the like in the conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Source region 2 Gate region 3 Back gate region 4 Drain region 5 Channel region 6 Silicon substrate 7 Low concentration drain region 8 Low concentration source region 9 Nitride film 10 PAD oxide film (silicon oxide film) 10a LOCOS oxide film 14 Interlayer insulating film 15A , 15B, 15C electrode

Claims (5)

[Claims] 1. A surface gate region of a first conductivity type, source / drain regions of a second conductivity type formed on both sides of the surface gate region, and a second conductivity type formed below the surface gate region. A junction field effect transistor having a channel region, the source / drain region, and a first conductivity type back gate region formed below the channel region; wherein the surface gate region, the source / drain region, A step in the thickness direction is provided between the surface gate region and the source / drain region, and an inclined portion is formed so as to gradually increase in thickness in a direction away from the boundary. Junction type field effect transistor. 2. The junction field-effect transistor according to claim 1, wherein the concentration gradually increases in a direction away from the boundary inside the inclined portion contacting a boundary between the surface gate region and the source / drain region. A junction type field effect transistor comprising a concentration gradient portion in which impurities are diffused so as to be thin. 3. The method according to claim 1, wherein an oxide film is formed on a predetermined semiconductor substrate, and the oxide film is partially oxidized by a LOCOS method. A first step of forming a convex portion and a concave portion on the surface of the semiconductor substrate; and a second step of forming the surface gate region in the convex portion on the surface of the semiconductor substrate and forming the source / drain region in the concave portion. And a method of manufacturing a junction field-effect transistor. 4. The manufacturing method according to claim 3, wherein in the first step, after forming the oxide film on the semiconductor substrate, an oxidation-resistant film is partially formed, and the oxidation-resistant film is formed. In order to increase the thickness of the oxide film other than the portion where the
After forming the convex portions and the concave portions on the surface of the semiconductor substrate by performing oxidation by a COS method, the oxide film is thinned by etching the oxide film on the concave portions, and in the second step, Forming the source / drain regions by ion-implanting the recesses through the oxide film thereon. 5. The junction type electric field according to claim 4, wherein a residual film thickness of said oxide film is set in a range of 200 ° to 1500 ° by etching in said first step. Method for manufacturing effect transistor.