JPH10207867A - Dct circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the discrete cosine transformation(DCT) circuit to deal with both of frame structure and field structure by generating a select signal for indicating any one of plural specific DCTs from a DCT controller and sharing plural specific DCTs by an adder or the like in a DCT operation part. SOLUTION: An input signal includes an 8-bit video signal and a 16-bit header signal. The DCT controller 101 inputs the header signal, generates a select signal for instructing switching between 8×4 DCT and 8×8 DCT and a start control signal and supplies these signals to matrix operation parts 103 to 108, etc. In T1 to T3 matrix operation parts 103, 105, 108, the select signal is inputted and a write address and a read address are switched correspondingly to the switching of 8×4 DCT and 8×8 DCT. An A1 matrix operation part 104 inputs the select signal and switches 8×4 DCT and 8×8 DCT through two code inverters and addition is executed by an adder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding circuit used in digital image compression technology, and more particularly to a DCT circuit for performing a two-dimensional DCT (Discrete Cosine Transform) operation.

[0002]

2. Description of the Related Art In MPEG2, a frame structure for allocating a frame to a picture (picture) and a field structure for allocating a field are mixed and handled. Therefore, the DCT circuit included in the encoding circuit is configured to be able to support both the DCT for the frame structure, that is, both the frame DCT and the DCT for the field structure, that is, the field DCT.

[0003] Both the frame DCT and the field DCT have a block size of 8 x 8 (pixels). by the way,
When an 8 × 8 size DCT is executed on a frame, the block size becomes 8 × 8 even on an actual screen, but when an 8 × 8 size DCT is executed on a field, the block size is 16 × 8 vertically on an actual screen. Becomes When the actual block size on the screen exceeds 8, the deterioration of image quality is conspicuous.

Accordingly, an 8 × 8 DCT (8 × 8D
Called CT. ) In the field,
It is preferable to switch to a DCT of 8 × 4 size (referred to as 8 × 4 DCT) for execution.

[0005]

In the conventional DCT circuit, as described above, when the frame DCT is 8 × 8 DCT and the field DCT is 8 × 4 DCT,
It was necessary to provide a DCT circuit for frame DCT and a DCT circuit for field DCT separately. However, this has the disadvantage of increasing the circuit scale.

[0006] In view of the above, it is an object of the present invention to provide a DCT circuit corresponding to a frame structure and a field structure.

In view of the above, the present invention provides a two-dimensional D having a simpler structure corresponding to a frame structure and a field structure.
An object is to provide a CT circuit.

[0008]

According to the present invention, a DCT is provided.
The circuit has a DCT operation unit for performing a DCT operation on input data, and a DCT controller that generates a select signal indicating one of 8 × 8 DCT and 8 × 4 DCT and supplies the signal to the DCT operation unit. The adder, multiplier and memory included in the operation unit are 8 × 8 DCT and 8 × 4D
It is configured so that it can be shared by both CTs.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an algorithm of a two-dimensional DCT operation used in the present invention will be described. As shown in the following equation, the two-dimensional DCT operation is performed by using an orthogonal matrix of 64 rows and 64 columns.
Represented by the product of two.

[0010]

## EQU1 ## C _OUT = [T3] [M] [A2] [T2] [A
1] [T1] X _IN

The inverse transform operation IDCT is expressed as follows by six products of a transposition matrix of 64 rows and 64 columns.

[0012]

X _IN = [T3] ^T [M] ^T [A2] ^T [T2]
^T [A1] ^T [T1] ^T C _OUT

X _IN and C _OUT are matrices representing input and output data. [T1], [T2], and [T3] are matrices for rearranging data.
M). [A1] [A2] is 0, 1,
This is a matrix composed of only −1, and is calculated by an adder in the DCT circuit. [M] is a matrix for multiplying a real number resulting from a trigonometric function as a coefficient, and is executed by a multiplier in the DCT circuit.

In both the 8 × 8 DCT and the 8 × 4 DCT, the DCT operation and the IDCT operation are performed according to the equations (1) and (2). Are in the same position. This will be described below. In the following, the case where the block size is 8 × 8 and the case where the block size is 8 × 4 are indicated by adding the suffixes 8 × 8 and 8 × 4, respectively.

(1) T matrix The matrices [T1], [T2] and [T3] are used to rearrange the data. In order to know the contents of the data rearrangement, the input data X is assumed as follows.

[0016]

X _IN = (0,1,2,3,4,5,6,7,8,9,10,11,12,13,1
4,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,
31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,4
7,48,49,50,51,52,53,54,56,57,58,59,60,61,62,63)

Here, 0 to 31 correspond to field 1 (8h × 4
v) and 32 to 63 indicate image block data of field 2 (8h × 4v).

In the case of 8 × 8 DCT, the following is _obtained by rearranging the input data X _IN by the matrix [T1] 8 × 8.

[0019]

## EQU4 ## C _OUT = [T1] _8X8 X _IN = (0,7,56,63,1,6,
57,62,2,5,58,61,3,4,59,60,32,39,24,31,33,38,25,30,
34,37,26,29,35,36,27,28,8,15,48,55,9,14,49,54,10,1
3,50,53,11,12,51,52,40,47,16,23,41,46,17,22,42,45,
18,21,43,44,19,20)

As described above, in the operation only for rearranging the data, the value of X _IN in the equation (3) is written to the write address of the memory (RAM), and the value of C _OUT in the equation (4) is stored in the memory (R).
AM) is executed by reading from the read address.

Similarly, the input data X _IN is _converted into a matrix [T2]
_8X8 , [T3] _{Rearrangement} by _8X8 is as follows.

[0022]

## _EQU5 ## C _OUT = [T2] _8X8 X _IN = (0,60,4,56,8,5
2,12,48,16,44,20,40,24,36,28,32,13,61,29,45,9,57,2
5,41,5,53,21,37,1,49,17,33,50,62,54,58,34,46,38,4
2,18,30,22,26,2,14,6,10,63,3,59,7,55,11,51,47,19,4
3,23,39,27,35,31) C _OUT = [T3] _8X8 X _IN = (0,16,32,8,48,12,17,39,
23,33,1,52,4,57,2,18,44,27,43,28,34,9,56,14,49,10,
54,13,19,41,24,45,29,40,25,35,60,6,61,3,62,7,63,2
0,38,30,46,22,36,53,11,50,15,59,31,37,21,47,58,5,5
5,26,42,51)

In the case of 8 × 4 DCT, the input data X _IN is rearranged by matrices [T1] _8X4 , [T2] _8X4 , [T3] _8X4 as follows.

[0024]

C _OUT = [T1] _8X4 X _IN = (0,7,1,6,2,5,3,
4,8,15,9,14,10,13,11,12,16,23,17,22,18,21,19,20,2
4,31,25,30,26,29,27,28,32,29,33,38,34,37,35,36,40,
47,41,46,42,45,43,44,48,55,49,54,50,53,51,52,56,6
3,57,62,58,61,59,60) C _OUT = [T2] _8X4 X _IN = (0,30,8,22,16,14,24,6,
2,28,10,20,18,12,26,4,7,25,15,17,23,9,31,1,5,27,1
3,19,21,11,29,3,32,62,40,54,48,46,56,38,34,60,42,5
2,50,44,58,36,39,57,47,49,55,41,63,33,37,59,45,51,
53,43,61,35) C _OUT = [T3] _8X4 X _IN = (0,1,8,16,9,2,3,10,17,2
4,25,18,11,4,5,12,19,26,27,20,13,6,7,14,21,28,29,2
2,15,23,30,31,32,33,40,48,41,34,35,42,49,56,57,50,
43,36,37,44,51,58,59,52,45,38,39,46,53,60,61,54,4
7,55,62,63)

(2) A matrix The matrix [A1] [A2] is composed of only 0, 1, and -1 elements. The matrix [A1] includes 16 4 × 4 matrices [a1] ⁰ along the diagonal as shown below, and the other parts are 0.

[0026]

(Equation 7)

This 4 × 4 matrix [a1] ⁰ is 8 × 8 DC
In the case of T and the case of 8 × 4 DCT, they are expressed as follows, respectively.

[0028]

(Equation 8)

The matrix [A2] is composed of four 16 × 16 matrices [a2] ⁰ , [a
2] ¹ , [a2] ² , [a2] ³ , and the other parts are 0
It is.

[0030]

(Equation 9)

The four 16 × 16 matrices [a2] ⁱ (i
= 0, 1, 2, 3) is expressed as follows.

[0032]

(Equation 10)

This 16 × 16 matrix [a2] ⁱ (i = 0,
4, 8 × 8 matrix [a
2 ₁₁ ] ⁱ , [a 2 ₁₂ ] ⁱ , [a 2 ₂₁ ] ⁱ , [a 2 ₂₂ ] ⁱ
(I = 0, 1, 2, 3) is expressed as follows.

[0034]

[Equation 11]

[0035]

(Equation 12)

[0036]

(Equation 13)

[0037]

[Equation 14]

Note that + represents 1 and-represents -1.

(3) M Matrix The matrix [M] is a 16 × 4 matrix [m] ⁱ (i = 0, 1, 2, 3,... 1) along the diagonal as shown below.
5), and the other parts are zero.

[0040]

(Equation 15)

In the case of 8 × 8 DCT, 16 4 × 4 matrices [m] ⁱ (i = 0, 1, 2, 2) included in this matrix [M]
3... 15) are expressed as follows.

[0042]

(Equation 16)

Here, each matrix [m] ⁱ (i = 0, 1, 2,
The coefficient of 3 ... 15) is cos (nπ / 16) (n =
0, 1, 2, 3... 15). As a specific example of the coefficient, a coefficient rounded to 16 bits by a hexadecimal number is shown.

[0044]

[Equation 17]

Similarly, in the case of 8 × 4 DCT, matrix [M]
16 × 4 matrix [m] ⁱ (i = 0,1,
2, 3... 15) are expressed as follows.

[0046]

(Equation 18)

Here, each matrix [m] ⁱ (i = 0, 1, 2,
3... 15) is √2cos (nπ / 16) (n
= 0, 1, 2, 3... 15). As a specific example of the coefficient, a coefficient rounded to 16 bits by a hexadecimal number is shown.

[0048]

[Equation 19]

In the above description, 8 × 4 DCT and 8 × 8D
In CT, it can be seen that the effective components (elements other than 0) of the matrix have the same position and only different values. Therefore, a memory (RAM), an adder, and a multiplier corresponding to these matrices can be shared.

FIG. 1 shows a configuration example of a two-dimensional DCT circuit according to the present invention. The DCT circuit according to the present embodiment includes a DCT controller 101, a head register 102, matrix operation units 103 to 108 for calculating respective matrices of the DCT, and a head controller.
And a selector 109.

The input signal includes an 8-bit video signal and a 16-bit header signal. DCT / Controller 101
Inputs a header signal and outputs 8 × 4 DCT and 8 × 8 DCT
Signal (SEL signal) for instructing the switching of the signals, and a start control signal (CTR) for instructing the start of the operation of each circuit.
L signal), a head register 102, matrix operation units 103 to 108, and a head selector 109.
Supply to

The head register 102 outputs the video signal to D
During the CT operation, the header signal is accumulated. The matrix operation units 103 to 106 receive an 8-bit video signal, perform a DCT operation, and supply the obtained 16-bit signal to the head selector 109.

First, the T1 matrix operation unit 103
The bit video signal is calculated by the equation (8 × 8 DCT) of Equation 4 or Equation 6
Rearrangement of data represented by the first expression (8 × 4 DCT) of the following expression is performed. Data for 4 clocks is held for 4 clocks, and output as a signal of 8 bits × 4 lines.

The A1 matrix operation unit 104 receives an 8-bit × 4 line signal and performs an addition operation represented by the equations (7) and (8). The signal of 8 bits × 4 lines is added four times to output a signal of 10 bits × 4 lines. The T2 matrix operation unit 105 has 10 bits ×
A signal of four lines is input, and the first equation (8 × 8D
CT) and the data expressed by the second expression (8 × 4 DCT) of Expression 6 are rearranged. Data for 16 clocks is held for 16 clocks and output as a signal of 10 bits × 16 lines.

The A2 matrix operation unit 106 receives a signal of 10 bits × 16 lines and performs an addition operation represented by the equations (9) to (14). A signal of 13 bits × 4 lines is output. M matrix operation unit 107
Is obtained by inputting a signal of 13 bits × 4 lines,
A multiplication operation represented by Expression 19 is performed. It is output as a 16-bit signal.

The T3 matrix operation unit 108 receives a 16-bit signal and inputs the first expression (8 × 8 DC
T) and the third expression (8 × 4 DCT) of Expression 6 is rearranged. The data for 16 clocks is held for 16 clocks and output as a 16-bit signal. The head selector 107 replaces the 16-bit signal obtained by the DCT operation with the header signal output from the head register 102 and outputs it as a 16-bit signal.

Referring to FIG. 2, the configuration and operation of the T1, T2, and T3 matrix calculation units 103, 105, and 108 will be described. Each matrix operation unit includes a counter 201, a memory controller 202, two RAMs 203A,
203B and a selector 204.

The counter 201 generates a count signal having a period of 64 clocks, and outputs the count signal to the memory controller 202.
To supply. The memory controller 202 has a counter 2
A switching signal for instructing to alternately switch between the two RAMs 203A and 203B is generated every 64 clocks by accumulating the count signals supplied from 01. The two RAMs 203A and 203B alternately repeat writing (writing) and reading (read) every 64 words. That is, when one of the two RAMs 203A and 203B is for reading, the other is for writing.

As described above, each RAM 203A, 203
The input data X _IN shown in Expression 1 is written from the write address of B, and the rearranged data C _OUT is read from the read address.

The memory controller 202 has a DCT
A select signal supplied from the controller 101 is input, and a select signal for instructing the selector 204 to switch between 8 × 8 DCT and 8 × 4 DCT is output. In addition, each RA
The write address and read address of M203A and 203B are switched in response to switching between 8 × 8 DCT and 8 × 4 DCT.

Referring to FIG. 3, an example of the configuration and operation of the A1 matrix operation unit 104 of this embodiment will be described. The A1 matrix operation unit 104 includes a counter 301, two sign inverters 302A and 302B, a selector 303, and three adders 304A, 304B and 305. The counter 301 generates a clock signal having a period of four clocks and supplies the clock signal to the sign inverters 302A and 302B. Sign inverter 30
2A and 302B invert the sign in the case of subtraction. 2
One of the two sign inverters 302A and 302B is 8 ×
One for 8DCT and the other for 8 × 4 DCT.

The selector 303 is a DCT / controller 1
01, and switches the input data signal via two sign inverters 302A and 302B. The four data signals passed through the selector 303 are added by three adders 304A, 304B and 305.

Referring to FIG. 4, an example of the configuration and operation of the A2 matrix operation unit 106 of this embodiment will be described. The A2 matrix operation unit 106 includes a counter 401, two sign inverters 402A and 402B, a selector 403, and seven adders 404A, 404B, 404C, 404D, and 406.
A, 406B, 408 and three sign inverters 405A, 4
05B and 407.

The counter 401 generates a clock signal having a period of 64 clocks and supplies it to the sign inverters 402A and 402B. The sign inverters 302A and 302B invert the sign in the case of subtraction. Two sign inverters 402A, 40
2B, one for 8 × 8 DCT and the other for 8 × 4
For DCT.

The selector 403 is a DCT / controller 1
01, and switches the output signals of the two sign inverters 402A and 402B. That is, in the case of 8 × 8 DCT, the first sign inverter 402A
And in the case of 8 × 4 DCT, it is connected to the output side of the second sign inverter 402B.

The eight data passed through the selector 403 are added to seven adders 404A to 404D, 406A and 406B.
And 408. The adder 406A,
406B and 408 add the data passed through the sign inverters 405A, 405B and 407.

Referring to FIG. 5, an example of the configuration and operation of the M matrix operation unit 107 of this embodiment will be described. The M matrix operation unit 107 includes a counter 501, two coefficient selectors 502A and 502B, a selector 503, and four multipliers 5
04A, 504B, 504C, and 504D, three adders 505A, 505B, and 506, and a rounder 507.

The counter 501 generates a clock signal having a period of 64 clocks and supplies it to the coefficient selectors 502A and 502B. Of the two coefficient selectors 502A and 502B,
One is for 8 × 8 DCT and the other is for 8 × 4 DCT.

The selector 503 is a DCT / controller 1
01, and switches the output signals of the two coefficient selectors 502A and 502B. That is, in the case of 8 × 8 DCT, the first coefficient selector 502A
, And in the case of 8 × 4 DCT, to the output side of the second coefficient selector 502B.

The four coefficients output from the selector 503 correspond to four multipliers 504A, 504B, 504, respectively.
C, 504D. Each multiplier 504A, 504
B, 504C and 504D multiply input data by coefficients. The outputs of the multipliers 504A, 504B, 504C, 504D are added by three adders 505A, 505B, 506.

The output of the last adder 506 is
7 and the output data is rounded to 16 bits.

Although the embodiments of the present invention have been described in detail, the present invention is not limited to these examples, and various modifications can be made within the scope of the invention described in the claims. It will be understood by those skilled in the art.

[0073]

According to the present invention, 8 × 8 DCT and 8 × 4
The DCT circuit configured to adaptively switch the DCT has an advantage that the circuit configuration can be simplified because the arithmetic circuit is shared.

According to the present invention, 8 × 8 DCT and 8 × 4D
In the DCT circuit configured to adaptively switch the CT, since the adder, the multiplier, and the memory are shared, there is an advantage that the manufacturing cost of the DCT circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a DCT circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a T1, T2, and T3 matrix operation unit according to the present invention.

FIG. 3 is a block diagram illustrating a configuration example of an A1 matrix operation unit according to the present invention.

FIG. 4 is a block diagram illustrating a configuration example of an A2 matrix operation unit according to the present invention.

FIG. 5 is a block diagram illustrating a configuration example of an M matrix operation unit according to the present invention.

[Explanation of symbols]

101 DCT controller, 102 head register, 103 T1 matrix operation unit, 104
A1 matrix operation unit, 105 T2 matrix operation unit, 106 A2 matrix operation unit, 107
M matrix operation unit, 108 T3 matrix operation unit, 109 head selector

Claims (3)

[Claims] 1. A DC for performing a DCT operation on input data.
And a DCT controller for generating a select signal indicating one of 8 × 8 DCT and 8 × 4 DCT and supplying the signal to the DCT calculator.
The adder, multiplier and memory included in the operation unit are 8 × 8D
A DCT circuit characterized in that it can be shared by both CT and 8 × 4 DCT. 2. The DCT circuit according to claim 1, wherein the DCT operation unit is configured to rearrange input data using the memory. 3. A head register for storing a head signal of an input signal, a header signal from the head register,
A DCT circuit, comprising: a head selector for combining output signals from a CT operation unit.