JP3371481B2 - Digital arithmetic unit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital arithmetic unit capable of highly efficient image compression and shortening the longest processing time, and more particularly to a field DCT for image data in real space. And frame DCT
The present invention relates to a digital arithmetic device for appropriately calculating and calculating DCT.

[0002]

2. Description of the Related Art Frame data included in image data in a real space is composed of, for example, two field data A and B as shown in FIG. When compressing image data in the real space, the frame data is divided into block data corresponding to, for example, 8 × 16 pixels, and the discrete cosine for converting the image data in the real space into data in the frequency space in units of this block data. Transform (DCT: Discrete Cosine
Transformation). For example, the image data [X] in the real space of 8 × 8 pixels is converted into the data [C] in the frequency space by DC.
The conversion formula for T conversion is represented by the following formula (1), and since the output sequence is approximately uncorrelated, the DCT output is converted to PC.
The M coding enables highly efficient compression coding.

[0003]

[Equation 1]

The matrix [P] in the above equation (1) is defined by the following equation (2).

[0005]

[Equation 2]

The image data in the real space generally changes smoothly, and when converted into the data in the frequency space, there is almost no high frequency component, and the data amount can be reduced.

The block data 102 shown in FIG.
This is data composed of 8 × 16 pixel data included in the frame data. As shown in FIG. 6, the block data 102 includes pixel data “Aij” (0 ≦ i, j ≦ 7) belonging to the field data A and pixel data “Bij” (0 ≦ i, belonging to the field data B. j ≦ 7) is included.

When the image data in the real space is a still image, as shown in FIG. 6, the block data 102 is converted into pixel data Aij (0≤i≤7, 0≤j≤3) and pixel data Bij ( 8 ≦ i ≦ 7, 0 ≦ j ≦ 3) 8
Frame block FR which is block data of × 8 pixels
M1 and pixel data Aij (0 ≦ i ≦ 7, 4 ≦ j ≦ 7)
And a frame block FRM2, which is 8 × 8 pixel block data composed of pixel data Bij (0 ≦ i ≦ 7, 4 ≦ j ≦ 7).
Two-dimensional 8 × 8 DCT is independently executed for 1 and frame block FRM2. In this case, since the image data in the real space is a still image, the pixel data Ai
There is no temporal difference between the data indicated by j and the pixel data Bij, and there is a close correlation between the data in the frame block FRM1 and the data in the frame block FRM2, which is smooth, and Good compression is possible. The DCT used in such an image compression method is called a frame DCT.

On the other hand, when the image data in the real space is a moving image including a violent movement, when the two-dimensional 8 × 8 DCT is executed by dividing the frame block FRM1 and the frame block FRM2 as shown in FIG. The correlation between the pixel data Aij and the pixel data Bij forming the FRM1 and the frame block FRM2 becomes low, and the compression efficiency is lowered. Therefore, when the image data in the real space is a moving image including a vigorous movement, the block data 102 is composed of pixel data Aij (0 ≦ i ≦ 7, 0 ≦ j ≦ 7) as shown in FIG. Field block FLD1 which is block data of 8 × 8 pixels and pixel data Bij (0 ≦ i ≦ 7, 0 ≦ j ≦
It is divided into a field block FLD2 which is block data of 8 × 8 pixels constituted by 7), and the two-dimensional 8 × 8 DCT is independently executed for each of the field block FLD1 and the field block FLD2. The DCT used in such an image compression method is called a field DCT. Hereinafter, a conventional image compression DSP (hereinafter, referred to as VDSP) will be described. Conventional VDS
P uses the Hadamard transform, which requires less calculation than DCT, and uses real space frame blocks FRM1 and FRM.
2, the frequency space data is calculated from the field blocks FLD1 and FLD2, and based on the calculation result, the superiority or inferiority of the compression efficiency between the frame DCT and the field DCT is compared.

FIG. 8 is a block diagram of a conventional VDSP 41. As shown in FIG. 8, the VDSP 41 has a 64-word working memory WM4, WM6, a DCT calculation circuit 8,
10, a control circuit 12, and a frame / field DCT switching detection circuit CMP14. WM4 and WM6
Is connected to the frame memory FM2 via the bus 16,
WM4 and WM6 are connected via bus 18 and
4 and DCT calculation circuit 8 are connected via a bus 20, WM6 and DCT calculation circuit 10 are connected via a bus 22, and CMP 14 is connected to WM4 and WM6 via a bus 24 and a bus 26, respectively.

In the VDSP 41, when executing the frame DCT, the DCT calculation circuit 8 is used to perform the DCT calculation of the frame block FRM1, and the DCT calculation circuit 10 is used to perform the DCT calculation of the frame block FRM2, resulting in an enormous amount of data. The DCT calculations having different calculation amounts are executed in parallel. On the other hand, in the VDSP 41, the field DCT
In the case of executing, the DCT calculation circuit 8 is used to perform the DCT calculation of the field block FLD1, and the DCT calculation circuit 10 is used to perform the DCT calculation of the field block FLD2 to calculate the DCT having a huge amount of calculation. Are executed in parallel.

In the CMP 14, the frame block FRM
1, FRM2 and field blocks FLD1, FL
Perform the Hadamard transform of D2. The conversion formula for Hadamard conversion of the image data [X] in the real space of 8 × 8 pixels into the data [C] in the frequency space is defined by the following formula (3), and the approximate spectrum is obtained only by the sum-difference calculation. Is DC
It is smaller than the case of T and can be sufficiently processed by CMP14 alone.

[0013]

[Equation 3]

The matrix [H] in the above equation (3) is defined by the following equation (4).

[Equation 4]

9 and 10 show a conventional VDSP 41.
3 is a flowchart of a calculation process in FIG. Step S1: Based on the control signals CS2, CS4, CS6 output from the control circuit 12 to FM2, WM4 and WM6, the image data in the real space stored in FM2 is 8 × 16 pixel data as shown in FIG. The configured block data 102 is transferred to the VDSP 41 via the bus 16. At this time, of the pixel data included in the block data 102, the field block FLD of FIG.
Pixel data Aij belonging to 1 (0 ≦ i ≦ 7, 0 ≦ j ≦
7) is stored in WM4 and field block FLD2
Pixel data Bij belonging to (0 ≦ i ≦ 7, 0 ≦ j ≦ 7)
Are stored in WM6.

Step S2: From the control circuit 12 to WM4,
Based on the control signals CS4 and CS6 output to the WM6, the pixel data Aij (0 ≦ i ≦ stored in the WM4 is stored.
7, 0 ≦ j ≦ 7) is output to the CMP 14 via the bus 24, and the pixel data Bij (0 ≦ i ≦) stored in the WM 6 is stored.
7, 0 ≦ j ≦ 7) is output to the CMP 14 via the bus 26. Then, based on the control signal CS14 output from the control circuit 12 to the CMP14, Hadamard conversion of the frame blocks FRM1 and FRM2 and the field blocks FLD1 and FLD2 is executed using the pixel data Aij and Bij input in the CMP14. To be done.

Step S3: Hadamard transform on the field blocks FLD1 and FLD2 executed in step S2 and the frame blocks FRM1 and FRM.
The results with the Hadamard transform for 2 are compared and the DCT
Is executed, it is determined which of the field DCT and the frame DCT is superior. Then, if the determination result indicates that the field DCT is superior to the frame DCT, the process of step S7 is executed, and if not, the process of step S4 is executed.

Step S7: This is executed when it is determined that the frame DCT in step S3 is superior.
At this time, the field block FLD of FIG.
The pixel data belonging to 1 is stored, and the pixel data belonging to the frame block FRM1 shown in FIG. 6 is Bi.
Since j (0 ≦ i ≦ 7, 0 ≦ j ≦ 3) does not exist, the DCT calculation circuit 8 remains in the frame block F as it is.
Unable to perform DCT calculation of RM1. Also,
Pixel data belonging to the field block FLD1 of FIG. 8 is stored in the WM 6, and Aij (0 ≦ i which is pixel data belonging to the frame block FRM2 of FIG. 6 is stored.
≦ 7, 4 ≦ j ≦ 7) does not exist, so D
The CT calculation circuit 10 cannot execute the DCT calculation of the frame block FRM2.

Therefore, from the control circuit 12 to WM4, WM6
Bij (0 ≦ i ≦ 7, 4 ≦ j ≦ 7) and A via the bus 18 based on the control signals CS4 and CS6 output to
Swap processing with ij (0 ≦ i ≦ 7, 0 ≦ j ≦ 3) is performed. That is, Aij (0 ≦
i ≦ 7, 4 ≦ j ≦ 7) is transferred, and Bij (0 ≦ i ≦ 7, 0 ≦ j ≦ 3) is transferred from WM6 to WM4, so that 32 words are transferred between WM4 and WM6. Data is swapped.

As a result, the pixel data Aij (0.ltoreq.0.ltoreq.0) which belongs to the frame block FRM1 of FIG.
i ≦ 7, 0 ≦ j ≦ 3) and Bij (0 ≦ i ≦ 7, 0 ≦
j ≦ 3) is stored, and in step S4, Aij and Bij are transferred from the WM 4 to the DCT calculation circuit 8 via the bus 20, and the DCT calculation circuit 8 executes the DCT calculation of the frame block FRM1. Bus 2
It is output to WM4 via 0. At the same time, the pixel data Aij (0 ≦ i ≦ 7, 4 ≦ j ≦ 7) and Bij (0) that belong to the frame block FRM2 of FIG.
.Ltoreq.i.ltoreq.7, 4.ltoreq.j.ltoreq.7) are stored, and in step S4, Aij and Bij are transferred from the WM 6 to the DCT calculation circuit 10 via the bus 22, and the DCT calculation circuit 10 calculates the DCT of the frame block FRM2. Executed,
The calculation result is output to the WM 6 via the bus 22.

Step S4: When step S7 is executed, the above-mentioned processing is executed. On the other hand, if step S7 is not executed and the process of step S4 is executed directly from step S3, the pixel data Aij (0 ≦ i ≦ 7, which is pixel data already belonging to the field block FLD1 of FIG. Since 0 ≦ j ≦ 7) is stored, the WM4 based on the control signals CS4 and CS8 output from the control circuit 12 to the WM4 and DCT calculation circuit 8 is stored.
From the pixel data A to the DCT calculation circuit 8 via the bus 20.
ij is output, and the DCT calculation circuit 8 executes the DCT calculation of the field block FLD1. Also, WM6
Since Bij (0 ≦ i ≦ 7, 0 ≦ j ≦ 7) which is the pixel data belonging to the field block FLD2 of FIG. 8 has already been stored in, the control circuit 12 outputs it to the WM6 and the DCT calculation circuit 10. The DCT calculation circuit 1 from the WM 6 via the bus 22 based on the control signals CS6 and CS10.
The pixel data Bij is output to 0, and the DCT calculation circuit 10
At the DCT calculation of the field block FLD2 is executed.

Step S5: From the control circuit 12 to WM4,
The field blocks FLD1, FLD2 or the frame block FRM1 calculated in the DCT calculation circuits 8 and 10 in step S4 based on the control signals CS4, CS6, CS8 and CS10 output to the WM6 and DCT calculation circuits 8 and 10. , FRM2 DCT calculation results are stored in WM4,6.

Step S6: From the control circuit 12 to FM2,
Control signals CS2, CS4 output to WM4, WM6
Based on CS6, the calculation result is read from WM4 and output to FM2 via bus 16, and the calculation result is read from WM6 and output to FM2 via bus 16.

FIG. 11A is a diagram for explaining the processing time of the VDSP 41 when the judgment result in step S3 of FIG. 9 indicates that the field DCT is superior to the frame DCT. In this case, as shown in FIG. 11A, the processing time of the field block FLD1 by the DCT calculation circuit 8 and the DCT calculation circuit 1
Since the processing time of the field block FLD2 by 0 overlaps, the total processing time is CMP14.
Is the sum of the processing time of the above and the processing time of the FLD 1 by the DCT calculation circuit 8. In the above example, the case where the pixel data belonging to the field block FLD1 is stored in the WM4 from the FM2 via the bus 16 and the pixel data belonging to the field block FLD2 is stored in the WM6 has been described. However, the pixels belonging to the frame block FRM1 are stored in the WM4. When data is stored and pixel data belonging to the frame block FRM2 is stored in the WM6, the field DC
When T is executed, time is required for swap processing of 32-word data, and the entire processing time ends at time T1 as shown in FIG. 11B.

FIG. 11B is a diagram for explaining the processing time of the VDSP 41 when the judgment result in step S3 indicates that the frame DCT is superior to the field DCT. In this case, FIG.
As shown in (B), since the time spent for the swap processing of the 32-word data in step S7 is required, the total processing time is the processing time by the CMP 14, the swap processing time, and the frame block FR by the DCT 8.
It is the sum of the processing time of M1 and the processing time ends at time T1.

[0026]

However, as described above, in the calculation processing by the conventional VDSP 41, WM4 and W
The presence or absence of the swap processing of 32-word data performed with M6 depends on the determination result of step S3 shown in FIG. 9 (the determination result of whether the field DCT or the frame DCT is selected). There is a problem in that the time is not constant, and in the worst case, the 32-word swap processing prolongs the processing time.

It is an object of the present invention to provide a digital arithmetic unit capable of obtaining a high image compression efficiency and keeping the DCT calculation time short and constant.

[0028]

In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, the digital arithmetic unit of the present invention has a first field and a second field.
The image frame data of the real space composed of fields is divided into a first block composed of a predetermined number of pixel data belonging to the same field, or a first block composed of the predetermined number of pixel data belonging to different fields. the second block as a unit, the pixel <br/> at least two of the first arithmetic means and second arithmetic means for performing a first orthogonal transform to convert to data in the frequency space, to the first computing means first storage means for supplying data, a second storage means for supplying the pixel data to said second calculation means, wherein
Read from the first storage means and the second storage means
Using the pixel data thus generated, a second orthogonal transform having a smaller calculation amount than that of the first orthogonal transform is executed in units of the first block and the second block, and the execution result is obtained. Based on the above, based on the first block and the second block, a selection unit that selects a block that can obtain a higher compression efficiency than when the image frame data is subjected to the first orthogonal transformation, and the selection. Means before
The first storage means when the first block is selected
The first block of the first field stored in
3/4 of the first pixel data that makes up the
Note that the first pixel data and the selection means are the second block data.
Stored in the first storage means when the user selects
Of the second pixel data forming the second block,
Half the number of the second pixel data and the first storage
Means for storing the initial state, and the selecting means stores the first state.
When the block 1 is selected, it is recorded in the second storage means.
The first block of the second field stored
Before the number of 3/4 of the second pixel data that constitutes
Note that the second pixel data and the selection means are the second block data.
Is stored in the second storage means when the user selects
Of the first pixel data forming the second block,
Half the number of the first pixel data and the second pixel data
The storage means stores the initial state, and the selection means
When the first block is selected, the first memory
The second pixel data stored in the column
Is transferred to the storage means and stored in the second storage means.
Transfer the first pixel data to the first storage means.
And when the selecting means selects the second block
The first image stored in the first storage means.
Of the raw data, the second data stored in the second storage means
The first pixel data forming the block of
Stored in the second storage means and stored in the second storage means.
In the first storage means of the second pixel data
The second pixel forming the second block to be stored
Storage control means for transferring data to the first storage means .

In the digital arithmetic unit of the present invention, as described above, the data belonging to the first block and the second block are stored in the first block and the second block. In either case of selecting the second block and the second block, the first arithmetic operation is performed so that the data exchange amounts between the first storage means and the second storage means are equal to each other. It is necessary to exchange data between the first storage means and the second storage means regardless of which block is used as the unit by the means and the second calculation means. But
The time spent in DCT calculation can be constant.

[0030]

In the digital arithmetic unit of the present invention, the first block and the second block are initialized to the first storage means and the second storage means under the control of the storage control means.
Regardless of which block is selected, the data is stored such that the amount of data exchanged between the first storage means and the second storage means becomes equal.

Then, the determining means sets the image frame data to a first block composed of a plurality of predetermined data belonging to the same field and a second block composed of a plurality of predetermined data belonging to different fields. The second orthogonal transform having a smaller calculation amount than that of the first orthogonal transform is executed in the unit of the block, and the image of the first block and the second block is calculated based on the execution result. When the first orthogonal transform is performed on the data related to the frame, a block for performing the orthogonal transform that can obtain high compression efficiency is determined.

Then, based on the control of the storage control means,
The first storage means and the second storage means are arranged so that the data of the unit for performing the orthogonal transformation determined by the determination means is stored in the first storage means and the second storage means.
Data is exchanged with the storage means.

Then, the data stored in the first storage means and the second storage means are supplied to the first arithmetic unit and the second arithmetic unit, respectively, and the supplied data is used. The first orthogonal transform is executed by the first arithmetic unit and the second arithmetic unit.

[0034]

【Example】

A VDSP as an embodiment of the digital arithmetic unit of the present invention will be described. VDSP of this embodiment
Is a digital arithmetic device with a constant overall processing time and capable of shortening the longest processing time. Figure 1
It is a block diagram of VDSP1 of the present embodiment. VD shown in FIG.
SP1 has the same configuration as the conventional VDSP 41 shown in FIG. 8, but the data stored as an initial state in the WM 44 and WM 46 and the procedure of the calculation processing are VDSP 4
Different from 1.

In the VDSP 1 of this embodiment, the conventional VDS is used.
Similar to P41, the image data in the real space stored in the FM2 is input via the bus 16 as the block data 102 composed of 8 × 16 pixel data as shown in FIG. 1 is divided into block data 30 and block data 32, the block data 30 is stored in the WM 44 as an initial state, and the block data 32 is stored in the WM 46 as an initial state.

As shown in FIG. 1, the block data 30 includes pixel data Aij (0≤i≤7, 0≤j≤5).
And Bij (0 ≦ i ≦ 7, 2 ≦ j ≦ 3) belong. In addition, the block data 32 includes Aij which is pixel data.
(0 ≦ i ≦ 7, 6 ≦ j ≦ 7) and Bij (0 ≦ i ≦
7, 0 ≦ j ≦ 1, 4 ≦ j ≦ 7) belongs.

The block data 30 and 32 are configured as described above, regardless of whether the field DCT or the frame DCT is executed.
The processing time is made constant by equalizing the amount of data exchange between the VDSP and the conventional VDSP.
This is because the total processing time can be shortened as compared with the worst case of the related art by suppressing the number of words to 32 or less in the case of 41.

That is, when the determination result in the CMP 14 indicates that the field DCT is superior to the frame DCT, Bij (0 ≦ i ≦) between the WM 44 and the WM 46 with respect to the WM 44 to the WM 46.
7, 2 ≦ j ≦ 3) and Aij (0 ≦ i ≦ 7, 6 ≦ j ≦ 7) from the WM 46 to the WM 44. The data amount to be swapped is 16 words. Is. On the other hand, when the determination result in the CMP 14 indicates that the frame DCT is superior to the field DCT, the W between the WM 44 and the WM 46 is
From A44 to WM46, Aij (0 ≦ i ≦ 7, 4 ≦
j ≦ 5) and transfers Bi from WM46 to WM44
It is sufficient to transfer j (0 ≦ i ≦ 7, 0 ≦ j ≦ 1), and the amount of data to be swapped is 16 words.
Therefore, regardless of whether the field DCT or the frame DCT is selected, the amount of data to be swap-transferred is 16 words, which is the same as the conventional V
It can be suppressed to 32 words or less in the case of the DSP 41, the longest swap processing time performed between the WM 44 and the WM 46 can be shortened, and the longest processing time in the VDSP 41 can be shortened.

The procedure of calculation processing in the VDSP 1 of this embodiment will be described below. 2 and 3 are VDS
It is a flowchart of the calculation process in P1. Step S11: Control signals CS2, CS44 output from the control circuit 12 to the FM2, WM44 and WM46,
Based on CS46, the pixel data Aij (0
≦ i ≦ 7, 0 ≦ j ≦ 7) is read out, and the pixel data Aij (0 ≦ i ≦ 7, 0 ≦ j is transferred to the WM 44 via the bus 16.
≦ 5) is stored as an initial state, and the pixel data Aij (0 ≦ i ≦ 7, 6 ≦ j ≦ 7) is stored in the WM 46 as an initial state. Step S12: Control signals CS2, CS44 output from the control circuit 12 to the FM2, WM44 and WM46,
Based on CS46, the pixel data Bij (0
≦ i ≦ 7, 0 ≦ j ≦ 7) is read, and the pixel data Bij (0 ≦ i ≦ 7, 2 ≦ j) is transferred to the WM 46 via the bus 16.
≦ 3) is stored as an initial state, and the pixel data Aij (0 ≦ i ≦ 7, 0 ≦ j ≦ 1, 4 ≦ j ≦ 7) is stored in the WM 46 as an initial state. That is, at the end of step S12, the block data 30 shown in FIG. 1 is stored in the WM 44 as the initial state, and the block data 32 is stored in the WM 46 as the initial state.

Step S13: Control circuit 12 to WM4
4, control signal CS4 output to WM46 and CMP14
Based on 4, 46 and 14, the pixel data Aij and Bij belonging to the block data 30 and the block data 32 shown in FIG. 1 are output from the WM 44 and WM 46 to the CMP 14 via the bus 24 and the bus 26. And
In the CMP 14, using the pixel data Aij and Bij,
The frame blocks FRM1 and FRM shown in FIG. 6 described above.
2 and the field block FLD1 shown in FIG.
The Hadamard transform is performed in units of FLD2.

Step S14: Hadamard transform in units of the field blocks FLD1 and FLD2 executed in step S13 and the frame block FRM1,
Based on the result of the Hadamard transform in FRM2 as a unit, it is determined which of the field DCT and the frame DCT is superior. Then, if the determination result indicates that the field DCT is superior to the frame DCT, the process of step S15 is executed, and if not, the process of step S19 is executed.

Step S15: Step S16 described later
In step 1, processing for storing data necessary for performing the field DCT in the WM 44 and the WM 46 is performed. That is, the block data 30 of FIG.
Pixel data belonging to the field block FLD1 shown in FIG. 7 is stored.
Since (0 ≦ i ≦ 7, 6 ≦ j ≦ 7) does not exist, the DCT calculation circuit 8 directly leaves the field block F
The DCT calculation of LD1 cannot be performed. Also,
Pixel data belonging to the block data 32 of FIG. 1 is stored in the WM 46, and Bij (0 ≦ i ≦ which is pixel data belonging to the field block FLD2 shown in FIG. 7 is stored.
7, 2 ≦ j ≦ 3) does not exist, so DC
The DCT calculation of the field block FLD2 cannot be executed in the T calculation circuit 10.

Therefore, from the control circuit 12 to WM44, WM
Based on the control signals CS44, 46 output to 46,
Aij (0 ≦ i ≦ 7, 6 ≦ j ≦ 7) via the bus 18
And Bij (0 ≦ i ≦ 7, 2 ≦ j ≦ 3) are swapped. That is, from WM44 to WM46, Bij
(0 ≦ i ≦ 7, 2 ≦ j ≦ 3) is transferred, and WM46 sends W
By transferring Aij (0 ≦ i ≦ 7, 6 ≦ j ≦ 7) to the M44, 16 between the WM44 and the WM46.
Perform word data swap processing.

As a result, the pixel data Aij belonging to the field block FLD1 of FIG. 7 is stored in the WM 44.
(0 ≦ i ≦ 7, 0 ≦ j ≦ 7) is stored, and at the same time, the WM
Bij (0 ≦ i ≦ 7, 0 ≦ j ≦ 7), which is pixel data belonging to the field block FLD2 of FIG. 7, is stored in 46.

Step S19: Step S16 described later
Data required for performing frame DCT in W
Processing for storing in M44 and WM46 is performed.
That is, the pixel data belonging to the block data 30 of FIG. 1 is stored in the WM 44, and Bij (0 ≦ i) which is the pixel data belonging to the frame block FRM1 of FIG.
≦ 7, 0 ≦ j ≦ 1) does not exist, so D
D of the frame block FRM1 in the CT calculation circuit 8
Unable to perform CT calculation. Pixel data belonging to the block data 32 of FIG. 1 is stored in the WM 46, and Aij (0 ≦ i ≦ 7, 4 ≦ j ≦, which is pixel data belonging to the frame block FRM2 shown in FIG.
Since 5) does not exist, the DCT calculation circuit 1 remains as it is.
At 0, the DCT calculation of frame block FLD2 cannot be performed.

Therefore, from the control circuit 12 to WM44, WM
Bij (0 ≦ i ≦ 7, 0 ≦ j ≦ based on the control signals CS44 and CS46 output to the bus 46 via the bus 18.
1) and Aij (0 ≦ i ≦ 7, 4 ≦ j ≦ 5) are swapped. That is, Ai from WM44 to WM46
j (0 ≦ i ≦ 7, 4 ≦ j ≦ 5) is transferred, and Bij (0 ≦ i ≦ 7, 0 ≦ j ≦ 1) is transferred from the WM 46 to the WM 44, so that between the WM 44 and the WM 46. In 1
6-word data swap processing is performed.

As a result, the pixel data Aij (0) belonging to the frame block FRM1 shown in FIG. 6 is stored in the WM 44.
≤ i ≤ 7, 0 ≤ j ≤ 3) and Bij (0 ≤ i ≤ 7, 0)
.Ltoreq.j.ltoreq.3) is stored, and at the same time, the WM 46 has pixel data Ai belonging to the frame block FRM2 of FIG.
j (0 ≦ i ≦ 7, 4 ≦ j ≦ 7) and Bij (0 ≦ i ≦
7, 4 ≦ j ≦ 7) is stored.

Step S16: From the control circuit 12 to WM4
4, the control signal CS44 output to the DCT calculation circuit 8,
Based on CS8, pixel data is output from the WM 44 to the DCT calculation circuit 8 via the bus 20, and the DCT calculation circuit 8 executes DCT calculation. At the same time, WM4
6 from the DCT calculation circuit 1 via the bus 22
It is output to 0, and the DCT calculation circuit 10 executes the DCT calculation.

At this time, if step S15 is executed, the frame block FLD1 shown in FIG.
Which is pixel data belonging to Aij (0 ≦ i ≦ 7, 0 ≦ j
≦ 7) is stored, and at the same time, WM, which is pixel data belonging to the frame block FLD2 of FIG. 7, is stored in the WM 46.
Since (0 ≦ i ≦ 7, 0 ≦ j ≦ 7) is stored, these pixel data are output to the DCT calculation circuits 8 and 10, and the DCT calculation circuits 8 and 10 execute the field DCT. .

On the other hand, when step S19 is executed, the WM 44 has pixel data Aij (0≤i≤7, 0≤j≤) which is pixel data belonging to the frame block FRM1 of FIG.
3) and Bij (0 ≦ i ≦ 7, 0 ≦ j ≦ 3) are stored, and at the same time, the frame block FR of FIG.
Aij (0 ≦ i ≦ 7, 4 which is pixel data belonging to M2
.Ltoreq.j.ltoreq.7) and Bij (0.ltoreq.i.ltoreq.7, 4.ltoreq.j.ltoreq.7) are stored, so these pixel data are output to the DCT calculation circuits 8 and 10, and the DCT calculation circuits 8 and 10 respectively. , The frame DCT is executed.

Step S17: From the control circuit 12 to WM4
4, the field block FLD1, FLD2 or the frame calculated in the DCT calculation circuits 8 and 10 in step S4 based on the control signals CS44, CS46, CS8 and CS10 output to the WM46 and the DCT calculation circuits 8 and 10, respectively. DCT of blocks FRM1 and FRM2
The calculation result is stored in the WMs 4 and 6.

Step S18: FM from the control circuit 12
2, control signal CS2 output to WM44, WM46,
Based on CS44 and CS46, the above calculation result is read from the WM44 and output to the FM2 via the bus 16.
In addition, the above calculation result is read from the WM 46 and the bus 16
Is output to FM2 via.

FIG. 4A is a diagram for explaining the processing time of the VDSP 1 when the determination result in step S14 indicates that the field DCT is superior to the frame DCT. In this case, FIG. 4 (A)
As shown in FIG. 11, as in the case of the conventional VDSP 41 shown in FIG.
Since the processing time of D1 and the processing time of the frame block FLD2 by the DCT calculation circuit 10 overlap, and the processing time spent for the data swap processing of 16 words between the WM44 and WM46 in step S15 is required. The total processing time is the sum of the processing time of CMP, the swap processing time, and the processing time of the field block FLD1 by the DCT calculation circuit 8. Therefore, the overall processing time of the VDSP 1 in this case is longer than the overall processing time of the conventional VDSP 41 shown in FIG. 11 (A), but shorter than the worst case processing time shown in FIG. 11 (B). Become.

On the other hand, FIG. 4B is a diagram for explaining the processing time of the VDSP 1 when the judgment result in step S14 shows that the frame DCT is superior to the field DCT. In this case,
As shown in (B), as in the case of the conventional VDSP 41, the field block FLD1 by the DCT calculation circuit 8 is used.
And the processing time of the field block FLD2 by the DCT calculation circuit 10 overlap, and
1 between WM44 and WM46 in step S19
Since the processing time spent for the 6-word data swap processing is required, the total processing time is the sum of the processing time by the CMP 14, the swap processing time, and the processing time of the field block FLD1 by the DCT calculation circuit 8. Therefore, the overall processing time of the VDSP 1 in this case is shorter than the swap processing time of 16 words as compared with the swap processing time of 32 words, and therefore compared with the overall processing time of the conventional VDSP 41 shown in FIG. Becomes shorter.

As a result, in VDSP1, step S1
Regardless of whether the field DCT or the frame DCT is selected in 4, the entire processing time becomes constant and is shorter than the longest processing time in the conventional VDSP 41. In the VDSP 1 of the present embodiment, generally, as described in the related art, if the image data in the real space relates to an image with a small motion such as a still image, the frame DCT is selected, and the image data in the real space is selected. Field D if the video is about a moving image
CT is selected.

According to the VDSP 1 of this embodiment, a 16-word data swap process may be performed between the WM 44 and the WM 46 regardless of whether the field DCT or the frame DCT is executed. As described above, the 32-word data swap processing is not performed between the WM 44 and the WM 46, and the maximum processing time can be shortened. Further, according to the VDSP 1 of the present embodiment, the processing time is constant regardless of whether the field DCT or the frame DCT is executed.
When the subsequent processing is performed using the processing result of the VDSP 1, the processing can be easily controlled.

According to the digital arithmetic unit of the present invention,
When performing orthogonal transformation using either the first block or the second block as a unit, the first storage means and the second storage means have the same data amount to be exchanged, and Since the size is relatively small, the time spent for data exchange can be shortened to a constant value. As a result, according to the digital arithmetic unit of the present invention, the longest processing time can be shortened, and when the subsequent processing is performed using the processing result, the processing can be easily controlled .

[Brief description of drawings]

FIG. 1 is a configuration diagram of a VDSP according to an embodiment of a digital arithmetic unit of the present invention.

FIG. 2 is a flowchart of a calculation process in the VDSP shown in FIG.

FIG. 3 is a flowchart of a calculation process in the VDSP shown in FIG.

FIG. 4 is a diagram for explaining a processing time of the VDSP shown in FIG.

FIG. 5 is a diagram for explaining image frame data.

FIG. 6 is a diagram for explaining a frame DCT.

FIG. 7 is a diagram for explaining a field DCT.

FIG. 8 is a block diagram of a conventional VDSP.

9 is a flowchart of a calculation process in the VDSP shown in FIG.

10 is a flowchart of a calculation process in the VDSP shown in FIG.

FIG. 11 is a diagram for explaining a processing time of the VDSP shown in FIG.

[Explanation of symbols]

1 ... VDSP 2 ... FM (frame memory) 4, 6, 44, 46 ... WM (64-word working memory) 8, 10 ... DCT calculation circuit 12 ... Control circuit 14 ... CMP (frame / field DCT switching detection circuit) 16, 18, 20, 22, 24, 26 ... Bus FRM1, FRM2 ... Frame block FLD1, FLD2 ... Field block

Claims (2)

(57) [Claims] 1. A first field and a second field
The image space data of the real space composed of the first space is composed of a predetermined number of pixel data belonging to the same field.
Block or the belonging to different fields
At least two first calculation means and second calculation means for performing a first orthogonal transformation for transforming the data into frequency space data in units of a second block composed of a predetermined number of pixel data; First storage means for supplying the pixel data to the calculation means, second storage means for supplying the pixel data to the second calculation means, the first storage means and the second storage means Read from
A second orthogonal transform having a smaller calculation amount than that of the first orthogonal transform is executed using the output pixel data as a unit of the first block and the second block, and the execution result is obtained. based on the first block and of the second block, and selecting means for selecting a block which can obtain high compression efficiency than in the case of orthogonal transform of the said image frame data first, the Before when the selecting means selects the first block
Of the first field stored in the first storage means.
Of the first pixel data forming the first block,
3/4 number of the first pixel data and the selection means
Selects the second block, the first storage
A second block forming said second block stored in the means
Half of the pixel data and the second pixel data
Is stored in the first storage means as an initial state, and
When the selecting means selects the first block, the first block is selected.
2 of the second field stored in a second storage means
Of the second pixel data forming the first block,
3/4 number of the second pixel data and the selecting means
Selects the second block, the second storage
Means for storing the second block stored in the means
One half of the first pixel data of the first pixel data
Data as an initial state in the second storage means,
When the selecting means selects the first block,
The second pixel data stored in the first storage means.
Data to the second storage means, and the second storage means
The first pixel data stored in the column
Was transferred to the storage hand stage, said selection means said second block
Is stored in the first storage means when is selected.
Of the first pixel data stored in the second storage means.
The first pixel data forming the second block to be stored.
Data to the second storage means, and the second storage means
Of the second pixel data stored in a column
The second block to be stored in one storage means
A digital operation device comprising: storage control means for transferring the second pixel data to the first storage means . 2. The digital arithmetic unit according to claim 1, wherein the first orthogonal transform is a discrete cosine transform, and the second orthogonal transform is a Hadamard transform.